JP2013229850A - Bootstrap switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bootstrap switch circuit that implements a reduced on-resistance and area of a bootstrap switch by improving a bootstrap level without reducing each switch size and increasing an on-resistance of a gate control section nor without increasing a bootstrapping capacitor.SOLUTION: The bootstrap switch circuit includes an inverter circuit for improving a bootstrap level of a gate potential of the main switch. Specifically, a switch section is disposed to selectively input a supply voltage or a ground voltage into the gate control section for the bootstrap switch.

Description

  The present invention relates to a bootstrap switch circuit, and more particularly to a bootstrap switch circuit capable of controlling the gate voltage of a bootstrap switch when the switch is turned on and improving the bootstrap amount with a small area.

  In recent years, electronic devices that need to convert analog signals into digital signals, such as various image sensors and image processing apparatuses, are required to process a large amount of data at high speed. However, the on-resistance of field effect transistors such as MOSFETs tends to increase due to a decrease in power supply voltage accompanying the miniaturization of elements. Further, the on-resistance of the MOSFET is dependent on the input voltage, and a signal sampled by such a switch includes many distortion components in the output waveform. There is a bootstrap switch circuit as a switch in which the on-resistance of the switch does not depend on the input voltage while reducing the on-resistance of the switch.

  FIG. 4 shows a bootstrap circuit that has been widely used so far (see, for example, JP-T-2008-533824). The circuit of FIG. 4 includes NMOS transistors MN1 to MN10, PMOS transistors MP1 and MP2, an inverter INV, capacitors C1, C2, and C3, an input node IN to which an input voltage VIN is input, and an output that outputs an output voltage VOUT. A node OUT, clock signal nodes PHI and PHIZ, a high-potential power supply voltage VDD, and a low-potential power supply voltage VSS are included. Here, the NMOS transistor MN1 is a bootstrap switch, and the clock signal nodes PHI and PHIZ are in a reverse phase relationship and alternately output the voltages VDD and VSS. The power supply voltage VSS on the low potential side is grounded.

  The drains of the NMOS transistors MN8 and MN9 are connected to the power supply voltage VDD. The gate of the NMOS transistor MN8 is connected to the top plate of the capacitor C2, and the source is connected to the top plate of the capacitor C1. The gate of the NMOS transistor MN9 is connected to the top plate of the capacitor C1, and the source is connected to the top plate of the capacitor C2. Further, the bottom plate of the capacitor C1 is connected to the clock signal node PHIZ, and the bottom plate of the capacitor C2 is connected to the OUT side of the inverter INV. A clock signal node PHIZ is connected to the IN side of the inverter INV. The NMOS transistors MN8 and MN9, the capacitors C1 and C2, and the inverter INV form a charge pump.

  The drain of the NMOS transistor MN10 is connected to the power supply voltage VDD, the gate is connected to the gate of the NMOS transistor MN9, and the source is connected to the top plate of the capacitor C3. The drain of the NMOS transistor MN7 is connected to the bottom plate of the capacitor C3, the gate is connected to the clock signal node PHIZ, and the source is connected to the power supply voltage VSS.

  The source of the PMOS transistor MP2 is connected to the power supply voltage VDD, the drain is connected to the drain of the NMOS transistor MP4, and the gates of the PMOS transistor MP2 and the NMOS transistor MN4 are connected to the clock signal node PHI. The source of the NMOS transistor MN4 is connected to the bottom plate of the capacitor C3.

  The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN4 are connected to the gate of the PMOS transistor MP1 and the drain of the NMOS transistor MN3. The source of the PMOS transistor MP1 is connected to the top plate of the capacitor C3, and the drain is connected to the respective gates of the NMOS transistors MN1, MN2, and MN3.

  The drain of the NMOS transistor MN5 is connected to the gates of the NMOS transistors MN1, MN2, and MN3, the gate is connected to the power supply voltage VDD, and the source is connected to the drain of the NMOS transistor MN6. The NMOS transistor MN6 has a gate connected to the clock signal node PHIZ and a source connected to the power supply voltage VSS.

  The input node IN and the source of the NMOS transistor MN1 are connected to the source of the NMOS transistor MN2, and the output node OUT is connected to the drain of the NMOS transistor MN1.

  The circuit of FIG. 4 operates as follows. First, consider a charge pump formed by NMOS transistors MN8 and MN9, capacitors C1 and C2, and an inverter INV. This works as follows. First, the voltage applied to the capacitors C1 and C2 is set to zero.

  When the clock signal PHIZ goes high, the voltage on the bottom plate of the capacitor C1 rises to the power supply voltage VDD. In this state, the bottom plates of the capacitors C2 and C3 become VSS and are grounded, so that the capacitors C2 and C3 are charged up to the voltage of the top plate VDD-VTHN (VTHN is the threshold voltage of the NMOS transistors MN9 and MN10).

  When the clock signal PHIZ goes low, the top plate of the capacitor C2 is boosted to 2VDD-VTHN. The capacitor C1 is charged through the NMOS transistor MN8 and becomes VDD.

  When PHIZ goes high again at the next stage, the capacitor C1 is charged to the power supply voltage VDD, so the top plate of the capacitor C1 is 2VDD, and the capacitors C2 and C3 are fully charged to VDD.

  In steady state, capacitors C1, C2, C3 are charged to VDD and the top plate voltage of capacitors C1 and C2 varies between VDD and 2VDD. A conventional bootstrap switch reaches its steady state after at least one clock period.

  Assuming that all capacitors are charged to the power supply voltage VDD, the bootstrap switch operates as follows.

  When PHIZ goes high, the bottom plate of the capacitor C2 is grounded and the NMOS transistor MN10 is turned on, so that the capacitor C3 is charged to the power supply voltage VDD. The switch PMOS transistor MP2 is also turned on, and the PMOS transistor MP1 is turned off because the gate of the PMOS transistor MP1 is driven to the power supply voltage VDD. Further, the NMOS transistor MN6 is turned on, and thus MN5 is also turned on, so that the gate terminal of the NMOS transistor MN1 that is a bootstrap switch is grounded. Since the gate terminal of the NMOS transistor MN1 is grounded, the NMOS transistors MN3, MN2, and MN1 are turned off. During this stage, the NMOS transistor MN1 disconnects the input node IN from the output node OUT, and charges the capacitor C3 to the power supply voltage VDD.

  When PHIZ goes low, the NMOS transistor MN6 is off, so the gate terminal of MN1 becomes high impedance. Initially, the bottom plate of the capacitor C3 is floating, but the NMOS transistor MN4 is turned on, and the PMOS transistor MP1 is immediately turned on to connect the capacitor C3 between the gate and source of the PMOS transistor MP1, and the capacitor C3 The charge accumulated in starts to flow to the gate terminal of the NMOS transistor MN1. When the gate voltage of the NMOS transistor MN1 rises, the NMOS transistor MN2 is turned on, and the bottom plate of the capacitor C3 is directed to the input voltage VIN. Therefore, the top plate of the capacitor C3 is pushed up near the voltage VDD + VIN. Eventually, this voltage appears at the gate of NMOS transistor MN1, so that MN1 is fully turned on, connecting input node IN and output node OUT. The NMOS transistor MN2 is completely turned on to connect the input node IN and the bottom plate of the capacitor C3, and the NMOS transistor MN3 is completely turned on to drive the gate of the PMOS transistor MP1 to the input voltage level. To do.

  Here, the size of the bootstrap amount in this circuit is strictly considered. First, when PHIZ is high, the amount of charge Q3 = C3 (VDD−VSS) stored in the capacitor C3. At this time, since the NMOS transistors MN5 and MN6 are on, the potential of the node N1 is VSS.

  Next, when PHIZ goes low, the PMOS transistor MP1 is turned on, and the charge accumulated in the capacitor C3 is the parasitic capacitance of the gate terminals of the NMOS transistors MN2 and MN3 including the bootstrap switch NMOS transistor MN1 and the parasitic capacitance of the drain terminal of the PMOS transistor MP1. The capacitance is distributed to the parasitic capacitance of the wiring of the node N1. Further, it is distributed to the parasitic capacitance of the source terminal of the NMOS transistor MN5 and the drain terminal of the NMOS transistor transistor MN6 and the parasitic capacitance of the wiring of the node N5, and the potential of the node N5 becomes VDD-VHTN, and the NMOS transistor MN5 is turned off. If the total amount of these parasitic capacitances is CPARA, and the potential of the node N1 after bootstrapping is VG, from the charge conservation law, Q3 = C3 (VDD−VSS) = C3 (VG−VIN) + CPARA (VG−VSS) and VG VG = C3 / (C3 + CPARA) × (VDD + VIN). If the parasitic capacitance CPARA is larger than the capacitor C3, the bootstrap amount is less than VDD + VIN, and the on-resistance of the bootstrap switch NMOS transistor MN1 may not be sufficiently lowered.

  In view of the above problems, an object of the present invention is to provide a bootstrap switch circuit capable of controlling the gate voltage of a bootstrap switch when the switch is turned on and improving the bootstrap amount with a small area.

  In order to achieve the above object, a bootstrap switch circuit according to the present invention is configured as follows.

  An inverter circuit is provided for improving the bootstrap amount of the gate potential of the main switch.

Specifically, the bootstrap switch circuit according to the present invention is connected to the input terminal and the output terminal, and a first control signal generated based on the first clock signal is input to the control terminal, and the bootstrap switch is turned on. The first MOS transistor and one end thereof are connected to the first power supply terminal, and the control terminal of the first MOS transistor is changed to the first power supply terminal by being turned on / off based on the first clock signal. The second MOS transistor to be electrically connected, one end is connected to the second power supply terminal, the other end is connected to the second MOS transistor, and based on the second clock signal having a phase opposite to that of the first clock signal. The third MOS transistor which is controlled to be turned on and off and has a role of protecting the second MOS transistor, and the second and third MOS transistors It is continued, the control terminal is characterized in that and a fourth MOS transistor connected to said second power supply terminal.

The second MOS transistor of the bootstrap switch circuit according to the present invention is connected between the first power supply terminal and the other end of the fourth MOS transistor, and is based on the first clock signal. On / off control is performed, and the third MOS transistor is connected between the second power supply terminal and the other end of the fourth MOS transistor, and is controlled on / off based on the second clock signal.
It is characterized by that.

A bootstrap switch circuit according to the present invention includes a first capacitor,
A fifth MOS transistor connected between the second power supply terminal and one end of the first capacitor and controlled to be turned on and off based on the first control signal; a first power supply terminal; and the first power supply terminal A sixth MOS transistor connected to the other end of the capacitor and controlled to be turned on / off based on the first clock signal, and one end connected to the second power supply terminal and the first clock signal input from the control terminal A seventh MOS transistor that is on / off controlled based on the first MOS transistor, and an eighth MOS transistor that has one end connected to the other end of the first capacitor and is on / off controlled based on the third clock signal input from the control terminal; The ninth end is connected to one end of the first capacitor, and outputs the first control signal from the other end by the on / off control based on the second control signal input from the control end. The second control signal is output from the other ends of the seventh MOS transistor and the eighth MOS transistor by on / off control of the seventh MOS transistor and the eighth MOS transistor. Is connected between one end of the first MOS transistor and the other end of the first capacitor, and is on / off controlled based on the first control signal input from the control end. The tenth MOS transistor is connected between the control terminal of the ninth MOS transistor and the other end of the first capacitor, and is on / off controlled based on the first control signal input from the control terminal. And an eleventh MOS transistor.

  The second clock signal and the third clock signal of the bootstrap switch circuit according to the present invention are the same.

  In addition, the third clock signal of the bootstrap switch circuit according to the present invention has a phase opposite to that of the first clock signal, the falling position is the same as the second clock signal, but the rising position is the second clock signal. It is characterized by being delayed from the clock signal.

  The fifth MOS transistor of the bootstrap switch circuit according to the present invention is characterized in that a third control signal is connected to a control terminal, and the third control signal and a charge pump for generating the third control signal are provided. .

Further, the charge pump of the bootstrap switch circuit according to the present invention includes a second capacitor to which the first clock signal is applied at one end, the other end of the second capacitor, and the second power supply end. A twelfth MOS transistor connected between the first and second MOS transistors, a third capacitor having one end applied with the inverted signal of the first clock signal and the other end connected with the control end of the twelfth MOS transistor;
The second power supply terminal is connected to one end, the other terminal of the third capacitor and the control terminal of the thirteenth MOS transistor are connected to the other terminal, and the other terminal of the second capacitor is connected to the control terminal. A third MOS signal, and the third control signal is supplied from the other end of the second capacitor.

  The bootstrap switch circuit according to the present invention further includes a switched capacitor circuit in which an input voltage is connected to an input terminal, and a fourth capacitor for sampling an input signal is connected to an output terminal of the bootstrap switch. Features.

  According to the present invention, the bootstrap amount can be improved without increasing the on-resistance by reducing the size of each switch of the gate control unit, and without increasing the bootstrap capacitor. In addition, the area can be reduced.

It is a circuit diagram of a bootstrap switch circuit according to the present embodiment. It is a circuit diagram of the 2nd form of the bootstrap switch circuit concerning this embodiment. It is a timing chart of the circuit diagram of the 2nd form of the bootstrap switch circuit concerning this embodiment. It is a circuit diagram of the bootstrap switch circuit comprised using a prior art.

  A bootstrap circuit according to this embodiment is shown in FIG. The circuit of FIG. 1 includes NMOS transistors MN1-MN10, PMOS transistors MP1-MP3, an inverter INV, capacitors C1, C2, and C3, an input node IN to which an input voltage VIN is input, and an output that outputs an output voltage VOUT. It includes a node OUT, clock signal nodes PHI and PHIZ, a high-potential power supply voltage VDD, and a low-potential power supply voltage VSS. The NMOS transistor MN1 is a bootstrap switch. The clock signal nodes PHI and PHIZ have a reverse phase relationship, and alternately output the voltages VDD and VSS. The power supply voltage VSS on the low potential side is grounded.

  The NMOS transistors MN8 and MN9, the capacitors C1 and C2, and the inverter INV form the same charge pump as the conventional bootstrap circuit shown in FIG.

  The drain of the NMOS transistor MN10 is connected to the power supply voltage VDD, the gate is connected to the gate of the NMOS transistor MN9, and the source is connected to the top plate of the capacitor C3. The drain of the NMOS transistor MN7 is connected to the bottom plate of the capacitor C3, the gate is connected to the clock signal node PHIZ, and the source is connected to the power supply voltage VDD.

  The source of the PMOS transistor MP2 is connected to the power supply voltage VDD, the drain is connected to the drain of the NMOS transistor MN4, and the gates of the PMOS transistor MP2 and NMOS transistor MN4 are each connected to the clock signal node PHI. The source of the NMOS transistor MN4 is connected to the bottom plate of the capacitor C3.

  The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN4 are connected to the gate of the PMOS transistor MP1 and the drain of the NMOS transistor MN3. The source of the PMOS transistor MP1 is connected to the top plate of the capacitor C3, and the drain is connected to the respective gates of the NMOS transistors MN1, MN2, and MN3.

  The power supply voltage VDD is connected to the gate of the NMOS transistor MN5, the drain is connected to the respective gates of the NMOS transistors MN1, MN2, and MN3, and the source is connected to the drain of the NMOS transistor MN6 and the drain of the PMOS transistor MP3. The source of the PMOS transistor MP3 is connected to the power supply voltage VDD, and the gate is connected to the clock signal node PHIZ. The NMOS transistor MN6 has a gate connected to the clock signal node PHIZ and a source connected to the power supply voltage VSS.

  The input node IN and the source of the NMOS transistor MN1 are connected to the source of the NMOS transistor MN2, and the output node OUT is connected to the drain of the NMOS transistor MN1.

  The operation of the bootstrap switch circuit having the above configuration will be described below.

  When PHIZ goes high, the bottom plate of the capacitor C1 is grounded and the NMOS transistor MN10 is turned on, so that the capacitor C3 is charged to the power supply voltage VDD. The PMOS transistor MP2 is also turned on, and the PMOS transistor MP1 is turned off because the gate of the PMOS transistor MP1 is driven to the power supply voltage VDD. In addition, since the NMOS transistor MN6 is turned on and NM5 is also turned on, the gate terminal of the NMOS transistor MN1 is grounded. Since the gate terminal of the NMOS transistor MN1 is grounded, the NMOS transistors MN3, MN2, and MN1 are turned off. During this stage, the bootstrap switch NMOS transistor MN1 disconnects the input node IN from the output node OUT and charges the capacitor C3 to the power supply voltage VDD.

  When PHIZ goes low, the NMOS transistor MN6 is turned off, the PMOS transistor MP3 is turned on, the charge from the power supply is accumulated in the parasitic capacitance CPARA, and the potential of the gate terminal of the bootstrap switch NMOS transistor MN1 is raised to near the power supply voltage VDD. And At the same time, the bottom plate of the capacitor C3 is floating, but the NMOS transistor MN4 is turned on, and the PMOS transistor MP1 is immediately turned on to connect the capacitor C3 between the gate and the source of the PMOS transistor MP1, and the capacitor C3 The electric charge accumulated in the capacitor starts to flow to the gate terminal of the bootstrap switch NMOS transistor MN1. Thereafter, the bottom plate of the capacitor C3 goes to the input voltage VIN, so that the top plate of the capacitor C3 is pushed up near the voltage VDD + VIN. Eventually, this voltage appears at the gate of NMOS transistor MN1, so that NMOS transistor MN1 is fully turned on and connects input node IN and output node OUT. At this time, the node N5 is kept at VDD-VTHN. When VREF + VIN, which is the potential of the node N1, is applied to the drain of the MN6, an excessive potential difference is generated between the source and the drain of the MN6, and it is highly likely that the MN6 will be destroyed, but the MN5 sets the drain voltage of the MN6 to VREF−VTNH. By maintaining, the destruction of MN6 is prevented and MN6 is protected. The NMOS transistor MN2 is completely turned on to connect the input node IN and the bottom plate of the capacitor C3, and the NMOS transistor MN3 is completely turned on to drive the gate of the PMOS transistor MP1 to the input voltage level. To do.

  That is, the parasitic capacitance CPARA including the gate terminal of the main switch MN1 has a charge flowing from the power supply voltage VDD via the NMOS transistor MN5 and the PMOS transistor MP3 and a charge accumulated in the capacitor C3 and flowing via the PMOS transistor MP1. As a result, compared with the conventional circuit in which the potential of the gate terminal of the bootstrap switch NMOS transistor MN1 is increased only by the electric charge accumulated in the capacitor C3, the proposed circuit does not reduce the parasitic capacitance CPARA, that is, the NMOS transistor MN1. The bootstrap amount can be improved without reducing the area and increasing the on-resistance and without increasing the capacitor C3.

  FIG. 2 shows a second form of the bootstrap circuit according to the present embodiment. The circuit of FIG. 2 is very similar to the circuit of FIG. 1, but the clock signal for driving the NMOS transistor MN4 is changed from PHI to PHIA.

  FIG. 3 is a timing chart of clock signals for controlling the bootstrap circuit shown in FIG. The clock signals PHI and PHIZ have a reverse phase relationship. The clock signal PHIA is a signal whose falling position is the same as that of PHI, but whose rising position is slightly delayed from PHI.

  The operation of the bootstrap switch circuit having the above configuration will be described below.

  When PHIZ is high, the operation is exactly the same as the circuit of FIG.

  When PHIZ goes low, the NMOS transistor MN6 is turned off, the PMOS transistor MP3 is turned on, the charge from the power supply is accumulated in the parasitic capacitance CPARA, and the potential of the gate of the bootstrap switch NMOS transistor MN1 is raised to near the power supply voltage VDD. To do. At this time, since PHIA is still low, the NMOS transistor MN4 and the PMOS transistor MP1 remain off. Charge from the power supply voltage VDD flows through the NMOS transistor MN5 and the PMOS transistor MP3 into the node N1 on the gate side of the NMOS transistors MN1, MN2, and MN3, and when the potential of the node N1 becomes VDD−VTNH, the NMOS transistors MN1, MN2 , MN3 is turned on, and the NMOS transistor MN5 is turned off. Thereafter, when PHIA goes high, the NMOS transistor MN4 is turned on, and the PMOS transistor MP1 is immediately turned on to connect the capacitor C3 between the gate and source of the PMOS transistor MP1, and the charge accumulated in the capacitor C3. Begins to flow to the gate side of the NMOS transistor MN1. At this time, since the potential of the node N1 on the gate side of the NMOS transistor MN1 has already risen to VDD-VTHN or a potential sufficiently close thereto, the decrease in the amount of bootstrap due to the charge distribution of the capacitor C3 is minimized. be able to. If the potential of the node N1 at this time is VG, from the charge conservation law, Q3 = C3 (VDD−VSS) = C3 (VG−VIN) + CPARA (VG− (VDD−VTHN)). C3 (VDD + VIN) + CPARA (VDD−VTHN)) / (C3 + CPARA).

  By applying the bootstrap switch circuit shown in FIG. 1 or FIG. 2 to the switch portion of the switched capacitor circuit, a switched capacitor circuit that can keep the on-resistance of the switch constant and small regardless of the input signal is realized in a small area. be able to.

MN1 to MN10 NMOS transistors MP1 to MP3 PMOS transistor INV Inverter C1 to C3 Capacitor IN Input node OUT Output node PHI, PHIZ, PHIA Clock signal node VDD, VSS Power supply voltage N1 to N5 node

Claims (8)

A first MOS transistor connected to the input terminal and the output terminal, the first control signal generated based on the first clock signal is input to the control terminal, and constitutes a bootstrap switch;
A second MOS transistor having one end connected to a first power supply terminal and controlled to be turned on and off based on the first clock signal, thereby electrically connecting the control terminal of the first MOS transistor to the first power supply terminal;
A third MOS transistor having one end connected to the second power supply end and the other end connected to the second MOS transistor and controlled to be turned on / off based on a second clock signal having a phase opposite to that of the first clock signal When,
A fourth MOS transistor having a role of protecting the second MOS transistor, connected to the second and third MOS transistors, and having a control terminal connected to the second power supply terminal;
A bootstrap switch circuit comprising: The second MOS transistor is connected between the first power supply terminal and the other end of the fourth MOS transistor, and is on / off controlled based on the first clock signal.
The third MOS transistor is connected between the second power supply terminal and the other end of the fourth MOS transistor, and is on / off controlled based on the second clock signal. 2. The bootstrap switch circuit according to 1. A first capacitor;
A fifth MOS transistor connected between the second power supply terminal and one end of the first capacitor and controlled to be turned on and off based on the first control signal;
A sixth MOS transistor connected to the first power supply terminal and the other end of the first capacitor and controlled to be turned on / off based on a first clock signal;
A seventh MOS transistor having one end connected to the second power supply terminal and controlled to be turned on / off based on a first clock signal input from the control end;
An eighth MOS transistor having one end connected to the other end of the first capacitor and controlled to be turned on / off based on the third clock signal input from the control end;
A ninth MOS transistor having one end connected to one end of the first capacitor and outputting a first control signal from the other end by on / off control based on a second control signal input from the control end; The second control signal is a signal output from the other ends of the seventh MOS transistor and the eighth MOS transistor by on / off control of the seventh MOS transistor and the eighth MOS transistor. A transistor,
A tenth MOS transistor connected between one end of the first MOS transistor and the other end of the first capacitor and controlled to be turned on / off based on the first control signal input from a control end;
An eleventh MOS transistor connected between a control end of the ninth MOS transistor and the other end of the first capacitor and controlled to be turned on / off based on the first control signal input from the control end;
The bootstrap switch circuit according to claim 1, further comprising:   4. The bootstrap switch circuit according to claim 1, wherein the second clock signal and the third clock signal are the same.   The third clock signal has a phase opposite to that of the first clock signal, the falling position is the same as the second clock signal, but the rising position is delayed from the second clock signal. Item 4. The bootstrap switch circuit according to Item 1. 6. The bootstrap switch according to claim 1, further comprising: a third control signal connected to a control terminal of the fifth MOS transistor, and the third control signal and a charge pump for generating the third control signal. circuit. The charge pump is
A second capacitor having one end applied with the first clock signal;
A twelfth MOS transistor connected between the other end of the second capacitor and the second power supply end;
A third capacitor having one end applied with an inverted signal of the first clock signal and the other end connected to the control end of the twelfth MOS transistor;
The second power supply terminal is connected to one end, the other terminal of the third capacitor and the control terminal of the thirteenth MOS transistor are connected to the other terminal, and the other terminal of the second capacitor is connected to the control terminal. A thirteenth MOS transistor;
With
The bootstrap switch circuit according to any one of claims 1 to 6, wherein the third control signal is supplied from the other end of the second capacitor. A bootstrap switch circuit according to any one of claims 1 to 7,
A switched capacitor circuit in which an input voltage is connected to an input terminal of the bootstrap switch circuit, and a fourth capacitor for sampling an input signal is connected to an output terminal of the bootstrap switch.

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