JP5702357B2 - Bootstrap switch circuit - Google Patents

Description

  The present invention relates to a bootstrap switch circuit, and more particularly to a bootstrap switch circuit capable of controlling the gate voltage of a bootstrap switch when the switch is turned off and improving the response in a small area.

  In recent years, electronic devices that need to convert analog signals into digital signals, such as various image sensors and image processing apparatuses, are required to process a large amount of data at high speed. However, the on-resistance of field effect transistors such as MOSFETs tends to increase due to a decrease in power supply voltage accompanying the miniaturization of elements. Further, the on-resistance of the MOSFET is dependent on the input voltage, and a signal sampled by such a switch includes many distortion components in the output waveform. There is a bootstrap switch circuit as a switch in which the on-resistance of the switch does not depend on the input voltage while reducing the on-resistance of the switch.

  A bootstrap circuit that has been widely used so far is shown in FIG. 2 (see, for example, JP-T-2008-533824). The circuit of FIG. 2 outputs NMOS transistors MN1 to MN10, PMOS transistors MP1 and MP2, an inverter INV, capacitors C1, C2, and C3, an input node IN to which an input voltage VIN is input, and an output voltage VOUT. It includes an output node OUT, clock signal nodes PHI and PHIZ, a high-potential power supply voltage VDD, and a low-potential power supply voltage VSS. Here, the NMOS transistor MN1 is a bootstrap switch, and the clock signal nodes PHI and PHIZ are in a reverse phase relationship and alternately output the voltages VDD and VSS. The power supply voltage VSS on the low potential side is grounded.

  The drains of the NMOS transistors MN8 and MN9 are connected to the power supply voltage VDD. The gate of the NMOS transistor MN8 is connected to the top plate of the capacitor C2, and the source is connected to the top plate of the capacitor C1. The gate of the NMOS transistor MN9 is connected to the top plate of the capacitor C1, and the source is connected to the top plate of the capacitor C2. Further, the bottom plate of the capacitor C1 is connected to the clock signal node PHIZ, and the bottom plate of the capacitor C2 is connected to the OUT side of the inverter INV. A clock signal node PHIZ is connected to the IN side of the inverter INV. The NMOS transistors MN8 and MN9, the capacitors C1 and C2, and the inverter INV form a charge pump.

  The drain of the NMOS transistor MN10 is connected to the power supply voltage VDD, the gate is connected to the gate of the NMOS transistor MN9, and the source is connected to the top plate of the capacitor C3. The drain of the NMOS transistor MN7 is connected to the bottom plate of the capacitor C3, the gate is connected to the clock signal node PHIZ, and the source is connected to the power supply voltage VSS.

  The source of the PMOS transistor MP2 is connected to the power supply voltage VDD, the drain is connected to the drain of the NMOS transistor MP4, and the gates of the PMOS transistor MP2 and the NMOS transistor MN4 are connected to the clock signal node PHI. The source of the NMOS transistor MP4 is connected to the bottom plate of the capacitor C3.

  The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN4 are connected to the gate of the PMOS transistor MP1 and the drain of the NMOS transistor MN3. The source of the PMOS transistor MP1 is connected to the top plate of the capacitor C3, and the drain is connected to the respective gates of the NMOS transistors MN1, MN2, and MN3.

  The drain of the NMOS transistor MN5 is connected to the gates of the NMOS transistors MN1, MN2, and MN3, the gate is connected to the power supply voltage VDD, and the source is connected to the drain of the NMOS transistor MN6. The NMOS transistor MN6 has a gate connected to the clock signal node PHIZ and a source connected to the power supply voltage VSS.

  The input node IN to which the input voltage VIN is input and the source of the NMOS transistor MN1 are connected to the source of the NMOS transistor MN2, and the output node OUT that outputs the output voltage VOUT is connected to the drain of the NMOS transistor MN1.

  The circuit of FIG. 2 operates as follows. First, consider a charge pump formed by NMOS transistors MN8 and MN9, capacitors C1 and C2, and an inverter INV. This works as follows. First, the voltage applied to the capacitors C1 and C2 is set to zero.

  When the clock signal PHIZ goes high, the voltage on the bottom plate of the capacitor C1 rises to the power supply voltage VDD. In this state, the bottom plates of the capacitors C2 and C3 become the power supply voltage VSS and are grounded, so that the capacitors C2 and C3 are charged up to the voltage of the top plate VDD-VTNH (VTHN is the threshold voltage of the NMOS transistors MN9 and MN10). The

  When the clock signal PHIZ goes low, the top plate of the capacitor C2 is boosted to 2VDD-VTHN. The capacitor C1 is charged through the switch MN8 and becomes VDD.

  When PHIZ goes high again at the next stage, capacitor C1 is charged to VDD, so the top plate of capacitor C1 is 2VDD and capacitors C2 and C3 are fully charged to VDD.

  In steady state, capacitors C1, C2, C3 are charged to VDD and the top plate voltage of capacitors C1 and C2 varies between VDD and 2VDD. A conventional bootstrap switch reaches its steady state after at least one clock period.

  Assuming that all capacitors are charged to the power supply voltage VDD, the bootstrap switch operates as follows.

  When PHIZ goes high, the bottom plate of the capacitor C2 is grounded and the NMOS transistor MN10 is turned on, so that the capacitor C3 is charged to VDD. The PMOS transistor MP2 is also turned on and the gate of the PMOS transistor MP1 is driven to VDD so that the PMOS transistor MP1 is turned off. Further, MN6 is turned on, and thus MN5 is also turned on, so that the gate terminal of the NMOS transistor MN1, which is a bootstrap switch, is grounded. When the gate terminal of MN1 is grounded, the NMOS transistors MN3, MN2, and MN1 are turned off. During this stage, the NMOS transistor MN1 disconnects the input node IN from the output node OUT and charges the capacitor C3 to VDD.

  When PHIZ goes low, the NMOS transistor MN6 is turned off, so that the gate terminal of MN1 becomes high impedance. Initially, the bottom plate of the capacitor C3 is floating, but the switch MN4 is turned on, and the PMOS transistor MP1 is immediately turned on to connect the capacitor C3 between the gate and source of the PMOS transistor MP1, and the capacitor C3 The accumulated charge starts to flow to the gate terminal of the NMOS transistor MN1. When the gate voltage of the NMOS transistor MN1 rises, the NMOS transistor MN2 turns on, and the bottom plate of the capacitor C3 rises to the input voltage VIN. For this reason, the top plate of the capacitor C3 is pushed up to the power supply voltage VDD + the input voltage VIN. Eventually, this voltage appears at the gate of NMOS transistor MN1, so that MN1 is fully turned on, connecting input node IN and output node OUT. The NMOS transistor MN2 is also completely turned on to connect the input node IN and the bottom plate of the capacitor C3, and the NMOS transistor MN3 is completely turned on to drive the gate of the PMOS transistor MP1 to the input voltage level. To do.

  Here, consider a state in which PHIZ transitions from low to high. The initial value of the potential of the node N1 connected to the gates of the NMOS transistors MN1, MN2, and MN3 is VDD + VIN, and the initial value of the potential of the node N5 connected to the source of the transistor MN5 and the drain of the MN6 is VDD−VTHN. In addition, the transistor MN5 is off. When PHIZ goes high, transistor MN6 is turned on and the potential at node N5 drops. As a result, the NMOS transistor MN5 starts to turn on gradually, the potential of the node N1 starts to drop, and finally the NMOS transistors MN1, MN2, and MN3 are completely turned off.

  As described above, in the process in which the bootstrap switch is turned off, the NMOS transistor MN5 is turned on after the NMOS transistor MN6 is turned on in FIG. And may cause a sampling error. Further, if it takes time to decrease the potential of the node N1, the NMOS transistors MN2 and MN3 cannot be turned off easily, and the potential of the node N4 does not increase easily. As a result, the PMOS transistor MP1 cannot be turned off, and an operation failure may occur in which the NMOS transistor MN1 cannot be turned off for a long time without the potential of the node N1 being lowered from the potential of the capacitor C3 top plate.

  In view of the above problems, an object of the present invention is to provide a bootstrap switch circuit capable of controlling the gate voltage of a bootstrap switch when the switch is turned off and improving the response with a small area.

  In order to achieve the above object, a bootstrap switch circuit according to the present invention is configured as follows.

  And a switch for switching the gate voltage of the switch of the gate control unit between a power supply voltage and a reference voltage for extracting charges accumulated in the gate of the switch of the input / output unit.

Specifically, the bootstrap switch circuit according to the present invention is connected to the input terminal and the output terminal, and a first control signal generated based on the first clock signal is input to the control terminal, and the bootstrap switch is turned on. a first MOS transistor constituting one end connected to the first power supply terminal, said first power supply terminal of the control terminal of said first MOS transistor in the first to be on-off controlled based on the clock signal A second MOS transistor connected to the second MOS transistor, and has a role of protecting the second MOS transistor, is connected to the second MOS transistor, and a control terminal is switched to a second power supply terminal or a reference power supply terminal. third MOS transistor and, selectively enterable the voltage of the second power supply terminal or the reference power source terminal to the control terminal of said third MOS transistor And a fourth and fifth MOS transistors constituting the switching unit to said fourth MOS transistor is connected between the control terminal of said third MOS transistor and said second power supply terminal On / off control is performed based on the first clock signal input to the control terminal, and the fifth MOS transistor is connected between the reference power supply terminal and the control terminal of the third MOS transistor. On / off control is performed based on a second clock signal having a phase opposite to that of the first clock signal input to the first clock signal .

The bootstrap switch circuit according to the present invention is connected to a first capacitor, between the reference power supply terminal and one end of the first capacitor, and is on-off controlled based on a third control signal. A seventh MOS transistor connected to the first power supply terminal and the other end of the first capacitor and controlled to be turned on / off based on the first clock signal, and one end connected to the reference power supply terminal It is connected, and an eighth MOS transistor of the first on-off control based on a clock signal input from the control terminal, one end connected to the other end of said first capacitor, said first input from the control terminal A ninth MOS transistor which is controlled to be turned on / off based on the clock signal 2 and one end connected to one end of the first capacitor and input from the control end A tenth MOS transistor that outputs the first control signal from the other end by on / off control based on a control signal, wherein the second control signal is the eighth MOS transistor and the ninth MOS transistor. said the on-off control is a first 8 MOS transistor and the signal output from the other end of said ninth MOS transistor, and MOS transistor 10, one end and the first capacitor of said first MOS transistor An eleventh MOS transistor connected between the other end and controlled to be turned on / off based on the first control signal input from the control end; a control end of the tenth MOS transistor; and a first capacitor A twelfth M connected to the other end and on / off controlled based on the first control signal input from the control end. Characterized in that it comprises a S transistor.

Moreover, bootstrap switch circuit according to the present invention, wherein the third control signal is connected to the control terminal of the sixth MOS transistor, further comprising a charge pump for generating the third control signal Features.

Moreover, bootstrap switch circuit according to the present invention, the charge pump includes a second capacitor, wherein the first clock signal is applied to one end, the other end of the second capacitor and the second power supply a thirteenth MOS transistor connected between the end, the inverted signal of the one end first clock signal is applied, a third capacitor control end of the thirteenth MOS transistor is connected to the other end And the other end of the third capacitor and the control end of the thirteenth MOS transistor are connected to the other end, and the other end of the second capacitor is connected to the control end. 14 is connected , and the third control signal is supplied from the other end of the second capacitor.

  In the bootstrap switch circuit according to the present invention, an input voltage is connected to an input terminal of the bootstrap switch circuit, and a fourth capacitor for sampling an input signal is connected to an output terminal of the bootstrap switch circuit. It further has a data circuit.

  According to the present invention, the gate voltage of the switch of the input / output unit can be quickly lowered without increasing the size of each switch of the gate control unit, and the responsiveness when the bootstrap switch is turned off can be improved.

It is a circuit diagram of a bootstrap switch circuit according to the present embodiment. It is a circuit diagram of the bootstrap switch circuit comprised using a prior art.

  A bootstrap circuit according to this embodiment is shown in FIG. The circuit of FIG. 1 outputs NMOS transistors MN1 to MN12, PMOS transistors MP1 and MP2, an inverter INV, capacitors C1, C2, and C3, an input node IN to which an input voltage VIN is input, and an output voltage VOUT. It includes an output node OUT, clock signal nodes PHI and PHIZ, a high-potential power supply voltage VDD, and a low-potential power supply voltage VSS. The NMOS transistor MN1 is a bootstrap switch. The clock signal nodes PHI and PHIZ have a reverse phase relationship, and alternately output the voltages VDD and VSS. The power supply voltage VSS on the low potential side is grounded.

  The NMOS transistors MN8 and MN9, the capacitors C1 and C2, and the inverter INV form the same charge pump as the conventional bootstrap circuit shown in FIG.

  The drain of the NMOS transistor MN10 is connected to the reference voltage VREF, the gate is connected to the gate of the NMOS transistor MN9, and the source is connected to the top plate of the capacitor C3. The drain of the NMOS transistor MN7 is connected to the bottom plate of the capacitor C3, the gate is connected to the clock signal node PHIZ, and the source is connected to the power supply voltage VSS.

  The source of the PMOS transistor MP2 is connected to the reference voltage VREF, the drain is connected to the drain of the NMOS transistor MP4, and the gates of the PMOS transistor MP2 and NMOS transistor MN4 are each connected to the clock signal node PHI. The source of the NMOS transistor MN4 is connected to the bottom plate of the capacitor C3.

  The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN4 are connected to the gate of the PMOS transistor MP1 and the drain of the NMOS transistor MN3. The source of the PMOS transistor MP1 is connected to the top plate of the capacitor C3, and the drain is connected to the respective gates of the NMOS transistors MN1, MN2, and MN3.

  The drain of the NMOS transistor MN11 is connected to the power supply voltage VDD, the gate is connected to the clock signal node PHIZ, the drain of the MN12 is connected to the reference voltage VREF, and the gate is connected to the clock signal node PHI. The sources of the NMOS transistors MN11 and MN12 are connected to the gate of the NMOS transistor MN5. The drain of the NMOS transistor MN5 is connected to the gates of the NMOS transistors MN1, MN2, and MN3, and the source is connected to the drain of the NMOS transistor MN6. The NMOS transistor MN6 has a gate connected to the clock signal node PHIZ and a source connected to the power supply voltage VSS.

  The input node IN and the source of the NMOS transistor MN1 are connected to the source of the NMOS transistor MN2, and the output node OUT is connected to the drain of the NMOS transistor MN1.

  The operation of the bootstrap switch circuit having the above configuration will be described below.

  When PHIZ goes high, the bottom plate of the capacitor C1 rises to the power supply voltage VDD and the top plate becomes 2VDD. As a result, the NMOS transistor MN10 is turned on, and the capacitor C3 is charged to the reference voltage VREF. Here, it is noted that the reference voltage VREF is equal to or lower than the power supply voltage VDD and sufficiently higher than VTHN. The PMOS transistor MP2 is also turned on, and the PMOS transistor MP1 is turned off because the gate of the PMOS transistor MP1 is driven to the reference voltage VREF. Further, since the NMOS transistor MN6 is turned on and MN5 is also turned on, the gate of the NMOS transistor MN1 is grounded. When the gate terminal of MN1 is grounded, the NMOS transistors MN3, MN2, and MN1 are turned off. During this stage, the NMOS transistor MN1 disconnects the input node IN from the output node OUT and charges the capacitor C3 to VREF.

  When PHIZ goes low, the NMOS transistor MN6 is turned off, so that the gate terminal of MN1 becomes high impedance. Initially, the bottom plate of the capacitor C3 is floating, but the NMOS transistor MN4 is turned on, and the PMOS transistor MP1 is immediately turned on to connect the capacitor C3 between the gate and source of the PMOS transistor MP1, and the capacitor C3 The electric charge accumulated in starts to flow to the gate of the main switch MN1. When the gate voltage of the NMOS transistor MN1 rises, the NMOS transistor MN2 is turned on, and the bottom plate of the capacitor C3 rises to the input voltage VIN. For this reason, the top plate of the capacitor C3 is pushed up to the reference voltage VREF + the input voltage VIN. Eventually, this voltage appears at the gate of NMOS transistor MN1, so that NMOS transistor MN1 is fully turned on and connects input node IN and output node OUT. The NMOS transistor MN2 is completely turned on to connect the input node IN and the bottom plate of the capacitor C3, and the NMOS transistor MN3 is completely turned on to drive the gate of the PMOS transistor MP1 to the input voltage level. To do. At this time, since the NMOS transistor 12 is on, the gate voltage of the NMOS transistor MN5 becomes the reference voltage VREF, and the potential of the node N5 connected to the source of the transistor MN5 and the drain of the MN6 becomes VREF−VTHN. That is, when VREF + VIN, which is the potential of the node N1, is applied to the drain of the MN6, there is a high possibility that an excessive potential difference occurs between the source and the drain of the MN6 and the MN6 is destroyed. By maintaining VTHN, it is possible to prevent destruction of MN6, so that MN5 can protect MN6.

  Next, consider a state in which PHIZ transitions from low to high. Since the transistor MN11 is turned on when PHIZ becomes high, the gate voltage of the transistor MN5 becomes VDD. Since the initial value of the potential of the node N1 connected to the respective gates of the NMOS transistors MN1, MN2, and MN3 is VREF + VIN, the initial value of the potential of the node N5 is VREF−VTHN, and VDD> VREF, the transistor MN5 is completely Turn on. Therefore, the potential of the node N1 can be quickly lowered without waiting for the NMOS transistor MN6 to turn on and the potential of the node N5 to drop. As a result, it is possible to improve the response when the bootstrap switch is turned on and off without increasing the area of the transistors MN5 and MN6.

  By applying the bootstrap switch circuit shown in FIG. 1 to the switch portion of the switched capacitor circuit, the switched capacitor circuit has a constant on-resistance of the switch regardless of the input signal, and has a small area and good responsiveness when the switch is turned off. Can be realized.

MN1-MN12 NMOS transistor MP1, MP2 PMOS transistor INV Inverter C1-C3 Capacitor IN Input node OUT Output node PHI, PHIZ Clock signal node VDD, VSS Power supply voltage N1-N5 node

Claims (5)

A first MOS transistor connected to the input terminal and the output terminal, the first control signal generated based on the first clock signal is input to the control terminal, and constitutes a bootstrap switch;
One end connected to a first power supply terminal, a second MOS transistor for connecting the control terminal of the first MOS transistor to the first power supply terminal by being on-off controlled based on the first clock signal ,
A third MOS transistor having a role of protecting the second MOS transistor and connected to the second MOS transistor, the control terminal being switched to the second power supply terminal or the reference power supply terminal ;
Fourth and fifth MOS transistors constituting a switch unit that allows a voltage at the second power supply terminal or the reference power supply terminal to be selectively input to a control terminal of the third MOS transistor;
Equipped with a,
The fourth MOS transistor is connected between the second power supply terminal and the control terminal of the third MOS transistor, and is on / off controlled based on the first clock signal input to the control terminal,
The fifth MOS transistor is connected between the reference power supply terminal and the control terminal of the third MOS transistor, and has a second clock signal having a phase opposite to that of the first clock signal input to the control terminal. The bootstrap switch circuit is controlled on and off based on the circuit. A first capacitor;
A sixth MOS transistor connected between the reference power supply terminal and one end of the first capacitor and controlled to be turned on / off based on a third control signal;
A seventh MOS transistor connected to the first power supply terminal and the other end of the first capacitor and controlled to be turned on and off based on the first clock signal;
One end connected to said reference power terminal, an eighth MOS transistor on-off controlled based on the first clock signal input from the control terminal,
A ninth MOS transistor having one end connected to the other end of the first capacitor and controlled to be turned on / off based on the second clock signal input from the control end;
A tenth MOS transistor having one end connected to one end of the first capacitor and outputting the first control signal from the other end by on / off control based on a second control signal input from the control end; , the second control signal is the eighth MOS transistor and the signal output from the other end of said eighth MOS transistor and the ninth MOS transistor by on-off control of said ninth MOS transistor, A tenth MOS transistor;
An eleventh MOS transistor connected between one end of the first MOS transistor and the other end of the first capacitor and controlled to be turned on / off based on the first control signal input from a control end;
A twelfth MOS transistor connected between the control end of the tenth MOS transistor and the other end of the first capacitor and controlled to be turned on / off based on the first control signal input from the control end;
The bootstrap switch circuit according to claim 1, comprising: Wherein said third control signal to the control terminal of the sixth MOS transistor is connected, the bootstrap switch according to claim 2, further comprising a charge pump for generating the third control signal Circuit . The charge pump is
A second capacitor said first clock signal is applied to one end,
A thirteenth MOS transistor connected between the other end of the second capacitor and the second power supply end;
A third capacitor having one end applied with an inverted signal of the first clock signal and the other end connected to the control end of the thirteenth MOS transistor;
The second power supply end is connected to one end, the other end of the third capacitor and the control end of the thirteenth MOS transistor are connected to the other end, and the other end of the second capacitor is connected to the control end. A fourteenth MOS transistor ,
With
The bootstrap switch circuit according to claim 3 , wherein the third control signal is supplied from the other end of the second capacitor. The switched-capacitor circuit further comprising a switched capacitor circuit in which an input voltage is connected to an input terminal of the bootstrap switch circuit and a fourth capacitor for sampling an input signal is connected to an output terminal of the bootstrap switch circuit. 5. The bootstrap switch circuit according to any one of 1 to 4 .

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