JP2004153124A - Method of treating substrate and method of forming wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a reliable and favorable connection that contributes to the further scale down of a device by completely suppressing the occurrence of short circuits between metal layers (particularly, wiring structures) and between wires, particularly, Cu-containing wiring formed by a damascene method. <P>SOLUTION: In order to obtain a favorable wiring structure, a Cu oxide formed on the exposed surface of Cu can be reduced sufficiently, the thermal expansion of the exposed surface of Cu can be prevented, and annealing performed by using a hydrogen gas as reducing gas is performed under a condition that a annealing temperature and annealing pressure are adjusted to 200-350°C and ≤80 Pa, respectively. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for processing a substrate and a method for forming a wiring structure mainly used for a semiconductor device, and is particularly applied when forming a wiring structure in which a wiring is made of a material containing at least copper (Cu).
[0002]
[Prior art]
In recent years, with the increase in the degree of integration of semiconductor elements and the reduction in chip size, miniaturization of wiring and multilayer wiring have been accelerated. In a logic device having such a multilayer wiring, the wiring delay is becoming one of the dominant factors of the device signal delay. The signal delay of the device is proportional to the product of the wiring resistance and the wiring capacitance. Therefore, it is important to reduce the wiring resistance and the wiring capacitance in order to improve the wiring delay.
[0003]
Therefore, formation of a Cu wiring has been studied in order to reduce the wiring capacity. It is difficult to process Cu. Therefore, a so-called damascene structure, in which a wiring groove formed in an interlayer insulating film is filled with Cu via a barrier metal film, is attracting attention as a suitable structure when applying it to wiring. ing.
[0004]
[Problems to be solved by the invention]
When a Cu wiring having a damascene structure is formed, a part of the surface of the lower Cu wiring is exposed from the via hole formed in the interlayer insulating film when the lower Cu wiring and the upper Cu wiring are connected. At this time, the surface is oxidized to form a Cu oxide, which may cause a connection failure. Therefore, in order to obtain good connection, it is necessary to perform a substrate treatment for reducing Cu oxide as a pretreatment for forming a barrier metal film. As this substrate treatment, for example, a treatment of removing Cu oxide by so-called reverse sputter etching (Ar reverse sputtering) using Ar ions is mainly used.
[0005]
However, in the pre-processing by Ar reverse sputtering, the shoulder of the wiring groove formed in the interlayer insulating film is also etched, and a short circuit may occur between adjacent wirings. Further, Cu is resputtered at the bottom of the via hole connected to the wiring groove, and there is a concern that Cu adheres to the inner wall surface of the via hole and a short circuit occurs between adjacent via holes.
[0006]
The present invention has been made to solve the above-mentioned problems, and completely suppresses a short circuit between metal layers (especially, a wiring structure) to contribute to further miniaturization of a device. It is an object of the present invention to provide a substrate processing method and a method for forming a wiring structure, which can realize a good connection between Cu-containing wirings in a damascene method and obtain a highly reliable device.
[0007]
[Means for Solving the Problems]
As a result of intensive studies, the inventor has conceived the following aspects of the invention.
[0008]
In the substrate processing method of the present invention, a part of the surface of the metal layer made of a material containing copper is exposed from the insulating layer above the substrate, and hydrogen gas is used as a reducing gas for the part of the surface. And performing a hydrogen annealing process on the substrate under the conditions that the processing temperature is 200 ° C. to 350 ° C. and the processing pressure is 80 Pa or more.
[0009]
The method of forming a wiring structure according to the present invention includes a step of forming a second insulating film on a first insulating film formed so as to cover a lower wiring formed of a material containing copper above a substrate; Processing the second insulating film so as to expose a part of the surface of the wiring, and using a hydrogen gas as a reducing gas for a part of the surface, and setting the processing temperature to 200 ° C. to 350 ° C. And a step of performing a hydrogen annealing treatment on the substrate under a condition that the processing pressure is set to 80 Pa or more, and a step of burying a processed portion of the second insulating film and forming an upper wiring connected to the wiring.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
-Basic gist of the present invention-
First, the basic gist of the present invention will be described together with its working principle.
In the present invention, a metal oxide film formed on an exposed surface of a metal layer made of a material containing copper (here, for convenience, the surface of a lower Cu wiring in a damascene method is the exposed surface, and Cu oxide is the metal oxide film. In this case, a hydrogen annealing process using H ₂ gas as a reducing gas is used instead of performing the Ar reverse sputtering process or the like.
[0011]
It is known that the above-mentioned hydrogen annealing treatment is performed under the conditions of, for example, a treatment temperature of 360 ° C., a treatment pressure of 6 Pa, and a treatment time of 90 seconds. However, in this case, Cu on the exposed surface at the bottom of the via hole formed in the interlayer insulating film thermally expands, and stress is generated in the interlayer insulating film and the wiring structure, so that a sufficient connection cannot be obtained.
[0012]
From the viewpoint of reliably reducing the Cu oxide without causing inconveniences such as thermal expansion of Cu on the exposed surface by the hydrogen annealing treatment, each condition of the annealing treatment, specific Specifically, it was conceived to optimize the treatment temperature at a low temperature and the treatment pressure at a high pressure from the correlation between the two.
[0013]
(Experiment 1)
Here, the treatment temperature and the treatment time were fixed, and the reduction pressure of the Cu oxide film was examined by changing the treatment pressure, while the treatment pressure and the treatment time were fixed, and the reduction ability of the Cu oxide film was examined by changing the treatment temperature. . Specifically, after forcibly oxidizing the surface of the Cu film formed by sputtering, annealing treatment was performed using H ₂ gas, and the oxygen concentration by SIMS was measured as an index of the reducing ability.
[0014]
FIG. 1 shows the relationship between the processing pressure and the oxygen concentration, and FIG. 2 shows the relationship between the processing temperature and the oxygen concentration. In FIG. 1, the processing temperature is 250 ° C. and the processing time is 90 seconds. In FIG. 2, the processing pressure is 180 Pa and the processing time is 90 seconds.
As shown in FIG. 1, it can be seen that an extremely low oxygen concentration of 4 × 10 ^{22 to} 5 × 10 ²² (atoms / cc) is obtained by setting the processing pressure to a high pressure condition of about 80 Pa or more. On the other hand, as shown in FIG. 2, when the processing temperature is about 200 ° C. to 350 ° C., it can be seen that the oxygen concentration becomes sufficiently low. Further, FIG. 2 shows the results based on the processing temperature of 360 ° C., the processing pressure of 6 Pa, and the processing time of 90 seconds, which are the recommended conditions of the manufacturer, and shows a relatively high oxygen concentration under the conditions.
[0015]
(Experiment 2)
Based on the results of Experiment 1, the optimum range of the processing temperature and the processing pressure was examined in order to perform the appropriate reduction treatment of the Cu oxide in view of good wiring connection.
[0016]
FIG. 3 shows the results of measuring the reflection intensity of the Cu film surface when the surface of the Cu film formed by sputtering was forcibly oxidized and reduced under various conditions by annealing using H ₂ gas as an index of the reducing ability. FIG. Again, the processing time was set to 90 seconds.
Thus, it can be seen that even at a relatively low processing temperature of about 250 ° C., a sufficient reflection intensity can be obtained by setting the processing pressure to about 80 Pa or more. In this case, the reflection intensity is not sufficiently high under the conditions of 200 ° C. and 80 Pa. However, here, the most important parameters of the reducing ability are considered to be limited to the processing temperature and the processing pressure. It is estimated that a sufficient reflection intensity can be obtained by setting the target time, for example, about 100 seconds to 120 seconds.
[0017]
(Experiment 3)
The present inventor considered a further technique added to the above-described hydrogen annealing treatment in order to suppress the processing temperature to a low temperature from the viewpoint of reliably preventing inconvenience such as thermal expansion of Cu at the bottom portion of the via hole. First, the inventors conceived of performing hydrogen annealing after degassing moisture contained in the substrate by vacuum annealing.
[0018]
Therefore, in order to specifically verify the technical idea, the oxygen concentration was measured in the same manner as in Experiment 1 based on a comparison between the case where the vacuum annealing was performed prior to the hydrogen annealing and the case where only the hydrogen annealing was performed. . Here, the conditions of the vacuum annealing treatment were a processing pressure (5 × 10 ⁻⁶ Pa or less), a processing temperature of 250 ° C., and a processing time of 90 seconds. The conditions of the hydrogen annealing processing were a processing pressure of 180 Pa, a processing time of 90 seconds, and a processing temperature of 200 seconds. 2 ° C. and 250 ° C.
[0019]
FIG. 4 shows the measurement results. Here, for reference, the oxygen concentration when only vacuum annealing is performed is described. Note that the oxygen concentration in the initial state (initial) of the Cu surface is additionally shown.
As described above, the combined use of the hydrogen annealing and the vacuum annealing, which is the pre-treatment, reduces the oxygen concentration almost uniformly as compared with the case of only the hydrogen annealing, and has a better reduction ability. Was obtained.
[0020]
Thus, based on the results of Experiments 1 to 3, while preventing inconveniences such as thermal expansion of the Cu-exposed surface, sufficient reduction of the Cu oxide on the Cu-exposed surface was realized, and a favorable wiring structure was obtained. In order to obtain hydrogen annealing, hydrogen annealing using hydrogen gas as a reducing gas may be performed under the conditions of a processing temperature of 200 ° C. to 350 ° C. and a processing pressure of 80 Pa or less. This effect becomes more remarkable by performing the vacuum annealing before the hydrogen annealing.
[0021]
-Specific embodiment of the wiring structure forming method-
Based on the basic gist of the present invention described above, a specific embodiment in which the present invention is applied to a method of forming a Cu wiring by a damascene method (here, a so-called dual damascene method) will be described in detail with reference to the drawings. In the present embodiment, a general MOS transistor is taken as an example of a semiconductor device, and the present invention is applied to the formation of the wiring structure.
[0022]
5 and 6 are schematic sectional views showing the method for forming the wiring structure according to the present embodiment in the order of steps.
In forming this wiring structure, a MOS transistor structure having a gate electrode and a source / drain is formed on a silicon wafer. The present invention is applied to a wiring structure electrically connected to, for example, a gate electrode of the MOS transistor structure.
[0023]
First, as shown in FIG. 5A, a gate electrode 3 is patterned via a gate insulating film 2 in a silicon semiconductor substrate 1 in an active region defined by an element isolation structure 31 by, for example, STI (Shallow Trench Isolation) method. After forming the sidewall insulating films 32 on both sides of the gate electrode 3, the source / drain 4 is formed on the surface layer of the semiconductor substrate 1 on both sides of the gate electrode 3. Then, a silicide layer 5 made of CoSi _x (for example, X = 2) is formed on each surface of the gate electrode 3 and the source / drain 4 to form a salicide structure.
[0024]
Subsequently, after a silicon nitride film 33 is formed by a CVD method so as to cover the gate electrode 3, a PSG (phosphosilicate glass) film 6 is deposited. Then, a contact hole exposing a part of the surface of the gate electrode 3 is formed in the PSG film 6 and the silicon nitride film 33 by photolithography and subsequent etching, and thereafter, a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical) method. A W plug 7 that fills this contact hole with tungsten (W) is formed by a polishing method or the like.
[0025]
Subsequently, a lower Cu wiring is formed by a so-called damascene method.
Specifically, first, as shown in FIG. 5B, an organic SOD (Spin On Diffusion) film, here a polyarylether-based low dielectric constant film, is formed on the PSG film 6 so as to cover the surface of the W plug 7. After applying 8, a silicon oxide film 9 is deposited, and an interlayer insulating film 11 composed of the low dielectric constant film 8 and the silicon oxide film 9 is formed. Note that the SOD includes SOG (Spin On Glass).
[0026]
Subsequently, as shown in FIG. 5C, a photoresist (not shown) is applied on the interlayer insulating film 11, and the photoresist is processed into a wiring shape by photolithography. Next, the interlayer insulating film 11 is dry-etched using the photoresist as a mask to form a wiring groove 12 in the interlayer insulating film 11 according to the shape of the photoresist.
[0027]
Subsequently, as shown in FIG. 5D, a barrier metal film 13 made of a high melting point metal, here Ta, is further formed on the interlayer insulating film 11 so as to cover the inner wall surface of the wiring groove 12 as a seed metal film. A Cu film 14a is continuously deposited and formed in a vacuum by a sputtering apparatus. Here, it is desirable to form the barrier metal film 13 and the Cu film 14a continuously in a vacuum.
[0028]
Subsequently, using the Cu film 14a as an electrode, a Cu film 14b is formed to a thickness to fill the wiring groove 12 by plating. In order to separate the Cu films 14a and 14b by the damascene method, the Cu films 14a and 14b and the barrier metal film 13 are polished by a CMP (Chemical Mechanical Polishing) method, and the Cu films 14a and 14b and the barrier metal film are formed only in the wiring grooves 12. 13, the lower Cu wiring 15 is formed.
[0029]
Subsequently, as shown in FIG. 5E, a silicon nitride film 16 whose main purpose is to prevent Cu diffusion is formed on the interlayer insulating film 11 so as to cover the lower Cu wiring 15.
[0030]
Subsequently, an upper Cu wiring electrically connected to the lower Cu wiring 15 via the via hole is formed.
[0031]
Specifically, first, as shown in FIG. 6A, after a silicon oxide film 17 is formed so as to cover the surface of the lower Cu wiring 15, an organic SOD film, here, a polyarylether-based low dielectric constant film is used. Then, a silicon oxide film 19 is formed, and an interlayer insulating film 21 composed of the silicon nitride film 16, the silicon oxide film 17, the low dielectric constant film 18, and the silicon oxide film 19 is formed.
[0032]
Subsequently, as shown in FIG. 6B, a portion serving as a wiring pattern is first formed on a silicon nitride film (not shown) on the silicon oxide film 19 by photolithography and subsequent etching. Subsequently, a via hole 22 is formed in the interlayer insulating film 21 so as to expose a part of the surface of the lower Cu wiring 15. At this time, the silicon nitride film 16 is left extremely thin on the lower Cu wiring 15 without completely exposing a part of the surface of the lower Cu wiring 15, that is, a state in which a part of the surface is almost exposed. You may make it.
[0033]
Then, the silicon oxide film 19 is etched using the wiring pattern (not shown) previously formed on the silicon nitride film as a hard mask and the low dielectric constant film 18 of the interlayer insulating film 21 as an etching stopper. The wiring groove 23 is formed by etching the low dielectric constant film 18 as an etching stopper.
[0034]
Subsequently, as shown in FIG. 6C, the above-described hydrogen annealing using H ₂ gas as a reducing gas is performed to reduce and remove the Cu oxide on the surface of the lower Cu wiring 15 to remove the lower Cu wiring. The Cu surface of the wiring 15 is exposed. As specific conditions for the annealing, the annealing is performed at a processing temperature of 200 ° C. to 350 ° C. and a processing pressure of 80 Pa or more, here 250 ° C. and 80 Pa.
[0035]
Subsequently, as shown in FIG. 6D, a barrier metal film 24 made of a refractory metal, here Ta, is further formed on the interlayer insulating film 21 so as to cover the wiring groove 23 and the inner wall surface of the via hole 22. A Cu film 25a is continuously deposited and formed in a vacuum by a sputtering apparatus as a seed metal film. Here, it is desirable to form the barrier metal film 24 and the Cu film 25a continuously in a vacuum.
[0036]
Subsequently, using the Cu film 25a as an electrode, a Cu film 25b is formed by plating so as to fill the wiring groove 23 and the via hole 22.
[0037]
Then, in order to separate the Cu films 25a and 25b by the damascene method, the Cu films 25a and 25b and the barrier metal film 24 are polished by the CMP method, and the Cu films 25a and 25b and the An upper layer Cu wiring 26 is formed while leaving the barrier metal film 24.
[0038]
As described above, a wiring structure in which the lower Cu wiring 15 and the upper Cu wiring 26 are electrically connected via the via holes 22 is completed. Further, the above-described damascene method may be repeated to form a wiring structure connected to the upper Cu wiring 26.
[0039]
Thereafter, through further formation of an interlayer insulating film, a via hole, a wiring, and the like, a MOS transistor having the wiring structure is completed.
[0040]
As described above, according to the present embodiment, the short circuit between the Cu wiring structures by the damascene method is completely suppressed, which contributes to further miniaturization of the device, and the gap between the lower Cu wiring 15 and the upper Cu wiring 26 is reduced. And a highly reliable MOS transistor can be obtained.
[0041]
-Modification-
Here, a modified example of the present embodiment will be described.
In this modification, first, as in the present embodiment, after going through the respective steps shown in FIGS. 5A to 5E, 6A and 6B, as shown in FIG. Prior to the hydrogen annealing, the semiconductor substrate 1 is annealed in a vacuum at a processing temperature of 250 ° C. for a processing time of 90 seconds. Thereafter, the above-described hydrogen annealing using H ₂ gas as a reducing gas is performed to reduce and remove the Cu oxide on the surface of the lower Cu wiring 15 to expose the Cu surface of the lower Cu wiring 15. As specific conditions for the annealing, the annealing is performed at a processing temperature of 200 ° C. to 350 ° C. and a processing pressure of 80 Pa or more, here 250 ° C. and 80 Pa.
[0042]
Thereafter, similarly to the present embodiment, the MOS transistor having the wiring structure is formed through the steps shown in FIGS. 6C and 6D and the formation of further interlayer insulating films, via holes, wirings, and the like. To complete.
[0043]
In this modification, a processing apparatus having the structure shown in FIG. 8 is used. This chamber includes at least five chambers 101 to 105 as shown in the drawing. The chamber 101 performs the above-described vacuum annealing process, the chamber 102 performs the above-described hydrogen annealing process, and the chamber 103 forms a barrier metal made of Ta. The process of forming the film 24 and the Cu film 25a, which is a seed metal film, and the process of forming the Cu film 25b by the plating method in the chamber 104 are performed by transporting the semiconductor substrate 1 in this order by the transport chamber 105 in a vacuum state. Run continuously. Thus, a series of main steps can be performed without exposing the semiconductor substrate 1 to the atmosphere.
[0044]
As described above, according to the present embodiment, the short circuit between the Cu wiring structures by the damascene method is completely suppressed, which contributes to further miniaturization of the device, and the gap between the lower Cu wiring 15 and the upper Cu wiring 26 is reduced. Can be realized, and a highly reliable MOS transistor can be obtained.
[0045]
In this embodiment and its modifications, a MOS transistor is exemplified as a semiconductor device. However, the present invention is not limited to this. All semiconductor devices having Cu wiring by a damascene method to achieve high integration and miniaturization are provided. It is preferable to apply the wiring structure.
[0046]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0047]
(Supplementary Note 1) A part of the surface of the metal layer made of a material containing copper is exposed from the insulating layer above the substrate, and hydrogen gas is used as a reducing gas for the part of the surface, and the processing temperature is reduced. A substrate annealing method, wherein the substrate is subjected to hydrogen annealing at a temperature of 200 ° C. to 350 ° C. and a processing pressure of 80 Pa or more.
[0048]
(Supplementary note 2) The substrate processing method according to Supplementary note 1, wherein the substrate is annealed in a vacuum before the hydrogen annealing treatment, and then the hydrogen annealing treatment is performed without exposing the substrate to the atmosphere. .
[0049]
(Supplementary Note 3) The substrate processing method according to Supplementary Note 1 or 2, wherein the insulating layer includes an organic SOD material.
[0050]
(Supplementary Note 4) The substrate processing method according to Supplementary Note 3, wherein the organic SOD material includes at least a polyarylether-based low dielectric constant material.
[0051]
(Supplementary note 5) The substrate processing method according to any one of Supplementary notes 1 to 4, wherein the metal layer is a wiring.
[0052]
(Supplementary Note 6) a step of forming a second insulating film on the first insulating film formed so as to cover a lower wiring formed of a material containing copper above the substrate;
Processing the second insulating film so as to expose a part of the surface of the wiring;
Using a hydrogen gas as a reducing gas for a part of the surface, performing a hydrogen annealing process on the substrate under the conditions that the processing temperature is 200 ° C. to 350 ° C. and the processing pressure is 80 Pa or more;
Burying a processed part of the second insulating film and forming an upper layer wiring connected to the wiring.
[0053]
(Supplementary Note 7) The method further includes a step of annealing the substrate in a vacuum before the hydrogen annealing.
7. The method for forming a wiring structure according to claim 6, wherein after the annealing, the hydrogen annealing is performed without exposing the substrate to the atmosphere.
[0054]
(Supplementary note 8) The method for forming a wiring structure according to supplementary note 6 or 7, wherein the second insulating film includes an organic SOD material.
[0055]
(Supplementary note 9) The method for forming a wiring structure according to supplementary note 8, wherein the organic SOD material includes at least a polyarylether-based low dielectric constant material.
[0056]
(Supplementary note 10) The method for forming a wiring structure according to any one of Supplementary notes 6 to 9, wherein the upper layer wiring is made of a material containing copper.
[0057]
(Supplementary Note 11) When processing the second insulating film, after forming a connection hole exposing a part of the surface of the metal layer in the second insulating film, a wiring shape is formed in the second insulating film. Form wiring grooves,
The method for forming a wiring structure according to any one of claims 6 to 10, wherein the upper layer wiring is formed so as to fill the connection hole and the wiring groove after the hydrogen annealing treatment.
[0058]
(Supplementary Note 12) After forming the connection hole and the wiring groove and performing the hydrogen annealing treatment, the adhesion between the lower wiring and the upper wiring so as to cover the inner wall surface of the connection hole and the wiring groove. 12. The method for forming a wiring structure according to claim 11, further comprising a step of forming a base film for improving the wiring structure.
[0059]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the short circuit between metal layers (especially wiring structure) is completely suppressed and it contributes to further miniaturization of a device, and reliable connection between wirings, especially favorable connection between Cu-containing wirings in a damascene method. And a highly reliable device can be obtained.
[Brief description of the drawings]
FIG. 1 is a characteristic diagram showing a relationship between a processing pressure and an oxygen concentration in a hydrogen annealing process according to the present embodiment.
FIG. 2 is a characteristic diagram showing a relationship between a processing temperature and an oxygen concentration in a hydrogen annealing process according to the present embodiment.
FIG. 3 is a characteristic diagram showing a relationship between a processing condition of a hydrogen annealing process and a reflection intensity of a Cu film surface.
FIG. 4 is a characteristic diagram showing a relationship between a processing temperature and an oxygen concentration based on a comparison between a case where vacuum annealing is performed prior to hydrogen annealing and a case where only hydrogen annealing is performed.
FIG. 5 is a schematic cross-sectional view showing a method of forming a wiring structure according to the present embodiment in the order of steps;
FIG. 6 is a schematic cross-sectional view showing a method of forming a wiring structure according to the present embodiment in the order of steps, following FIG. 5;
FIG. 7 is a schematic cross-sectional view showing a step of performing a two-stage annealing process in a method of forming a wiring structure according to a modification of the present embodiment.
FIG. 8 is a schematic diagram illustrating a schematic configuration of a processing apparatus used in a modified example of the present embodiment.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 silicon semiconductor substrate 2 gate insulating film 3 gate electrode 4 source / drain 5 silicide layer 6 PSG film 7 W plug 8, 18 low dielectric constant film 9, 17, 19 silicon oxide film 11, 21 interlayer insulating film 12, 23 wiring groove 13, 24 Barrier metal films 14a, 14b, 25a, 25b Cu film 15 Lower Cu wiring 16, 19, 33 Silicon nitride film 22 Via hole 26 Upper Cu wiring 31 STI element isolation structure 32 Side wall insulating film

Claims (8)

A part of the surface of the metal layer made of a material containing copper is exposed from the insulating layer above the substrate, and hydrogen gas is used as a reducing gas for the part of the surface, and the processing temperature is set to 200 ° C. A substrate processing method, wherein the substrate is subjected to hydrogen annealing at 350 ° C. and a processing pressure of 80 Pa or more. 2. The substrate processing method according to claim 1, wherein the substrate is annealed in a vacuum before the hydrogen annealing, and then the hydrogen annealing is performed without exposing the substrate to the atmosphere. 3. The substrate processing method according to claim 1, wherein the metal layer is a wiring. Forming a second insulating film on a first insulating film formed so as to cover a lower wiring made of a material containing copper above the substrate;
Processing the second insulating film so as to expose a part of the surface of the wiring;
Using a hydrogen gas as a reducing gas for a part of the surface, performing a hydrogen annealing process on the substrate under the conditions that the processing temperature is 200 ° C. to 350 ° C. and the processing pressure is 80 Pa or more;
Burying a processed part of the second insulating film and forming an upper layer wiring connected to the wiring. Prior to the hydrogen annealing, the method further includes annealing the substrate in a vacuum.
The method according to claim 4, wherein after the annealing, the hydrogen annealing is performed without exposing the substrate to the atmosphere. The method according to claim 4, wherein the upper layer wiring is made of a material containing copper. In processing the second insulating film, a connection hole exposing a part of the surface of the metal layer is formed in the second insulating film, and then a wiring groove having a wiring shape is formed in the second insulating film. And
The method according to any one of claims 4 to 6, wherein after the hydrogen annealing, the upper layer wiring is formed so as to fill the connection hole and the wiring groove. After forming the connection hole and the wiring groove and performing the hydrogen annealing treatment, to improve the adhesion between the lower wiring and the upper wiring so as to cover the inner wall surface of the connection hole and the wiring groove. 8. The method for forming a wiring structure according to claim 7, further comprising a step of forming a base film.

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