JP2004140263A - Method for substrate treatment and method for forming wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for substrate treatment which obtains successful connection between lower layer Cu wiring and upper layer Cu wiring in a damascene method by simultaneously carrying out reduction treatment to an oxidized Cu exposure surface and degassing an SOD film by the same process in spite of reducing wiring resistance by using the SOD film. <P>SOLUTION: In order to obtain successful wiring structure by satisfying all of the respective view points of the sufficient reduction of a Cu oxide on the Cu exposure surface, sufficient degassing from an interlayer insulating film including the SOD film, and the prevention of thermal expansion on the Cu exposure surface, annealing using reduction gas containing hydrogen is carried out under a condition that a treatment temperature is ≤350°C and that a treatment time ranges from 300 sec to 600 sec. <P>COPYRIGHT: (C)2004,JPO

Description

【００１８】
表１から、処理温度を４００℃としたアニール処理では、ＮＨ_３ガスの分圧を変えても反射率にさほど差は見られないが、処理温度を３５０℃とした場合では、ＮＨ_３ガスの分圧が高い方が還元能力に優れていることが判る。
【００１９】
そこで、表１の測定の場合とは異なる基板を用い、ＮＨ_３ガスの分圧を固定し、特に処理温度を４００℃とした場合における適正な処理時間を調べた。測定結果を表２に示す。ここでは、混合ガスを構成するＮＨ_３／Ｎ_２を３８５０ｃｃ／２８００ｃｃ、ＮＨ_３ガスの分圧を２．２Ｔｏｒｒ（≒２９３（Ｐａ））とした。
【００２０】
【表２】

【００２１】
表２から、処理温度を４００℃としたアニール処理では、処理時間が６０秒でも十分な還元能力が見られることが判る。処理温度を３５０℃とした場合では、４００℃の処理と比較すれば劣るものの、通常の還元能力としては遜色ないものである。
【００２２】
更に、表１，表２の測定の場合とは異なる基板を用い、表２の測定と同様に混合ガスを構成するＮＨ_３／Ｎ_２を３８５０ｃｃ／２８００ｃｃ、ＮＨ_３ガスの分圧を２．２Ｔｏｒｒ（≒２９３（Ｐａ））とし、波長６３３ｎｍの光における反射率を、処理温度３００℃の場合を含めて測定した。測定結果を表３に示す。
【００２３】
【表３】

【００２４】
表３から、処理温度を３００℃としたアニール処理では還元能力は不十分であるが、４００℃では十分な還元能力が得られることが再確認され、３５０℃では処理時間１８０秒でも高い還元能力が示された。
【００２５】
同様に、Ｃｕ膜を上記のようにスパッタ形成し、大気中で１５０℃、１０分の条件でその表面を強制的に酸化した状態で、還元ガスをＨ_２ガス及びＮ_２ガスの混合ガスとしてアニール処理を実行した場合の還元能力を調べた。定結果を表３に示す。処理温度３５０℃の場合について、Ｈ_２ガスの分圧を３Ｔｏｒｒ（≒４００（Ｐａ））とした場合について相対的反射率（％）を測定した。
【００２６】
【表４】

【００２７】
表４から、処理温度３５０℃、処理時間１８０秒のＨ_２アニール処理により、十分な還元能力が見られることが判る。
【００２８】
以上の結果から、ＮＨ_３ガス又はＨ_２ガスを含む還元ガスを用いたアニール処理において、露出Ｃｕ表面を十分に還元するという観点では、処理温度を４００℃とすれば短時間の処理で十分な還元が得られ、３５０℃でも処理時間を比較的長く（３００秒以上）とすれば良好な還元が得られる。
【００２９】
（実験２）
ところで、アニール処理においては、その条件次第でビア孔の底部で露出したＣｕ表面が熱膨張することがあるため、これを抑えることが必要となる。そこで、処理温度４００℃及び３００℃の場合について処理時間を変え、ダマシン法により、上記のＮＨ_３ガスを用いたアニール処理を行い形成された配線構造の断面状態を走査型電子顕微鏡（ＳＥＭ）にて調べた。
【００３０】
観察結果を図１に示す。
当該アニール処理を行わずに形成された配線構造の断面状態の参照写真（Ｒｅｆ．（Ｎｏ　ＡＮＬ））（（ａ））と比較して、処理温度４００℃（（ｂ））では短時間処理、具体的には処理時間が６０秒でもビア孔の底部で露出したＣｕ表面に熱膨張が生じていることが判る。これに対して、処理温度３５０℃（（ｃ））では長時間処理、具体的には処理時間が３００秒でもビア孔の底部で露出したＣｕ表面には熱膨張が見られず、６００秒で軽度の熱膨張が見られる程度である。なお、一般的にガスの還元能力を考慮すれば、Ｈ_２ガスを含む還元ガスを用いたアニール処理でも上記と同様な結果が得られるものと十分な確度をもって推定される。
【００３１】
以上の結果から、ＮＨ_３ガス又はＨ_２ガスを含む還元ガスを用いたアニール処理において、露出Ｃｕ表面の熱膨張を防止するという観点では、処理温度を３５０℃以下とすれば比較的長時間（３００秒以上）の処理時間でも熱膨張を抑止することができる。この場合、処理時間は３００秒〜６００秒が適正範囲である。
【００３２】
（実験３）
続いて、当該アニール処理による脱ガス能力について調べた。ここでは、層間絶縁膜として有機ＳＯＤ膜であるポリアリールエーテル系の材料（いわゆるＳｉＬＫ）を用い、当該アニール処理を行った後、昇温脱離分光法（ＴＤＳ：Ｔｈｅｒｍａｌ　Ｄｅｐｏｓｉｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）により脱ガス特性を測定した。
【００３３】
測定結果を図２及び図３に示す。
図２では、ＮＨ_３ガスを含む還元ガスを用いた処理温度４００℃のアニール処理を行った際の脱ガス特性を、図３では、ＮＨ_３ガスを含む還元ガスを用いた処理温度３５０℃のアニール処理を行った際の脱ガス特性をそれぞれ示しており、各図において、ＳＯＤ膜からの脱ガスとして最も問題視される水（水蒸気）について、室温から６００℃程度まで昇温させた際の脱ガス量（即ち、アニール処理後の層間絶縁膜における残存ガス量）を相対値で表している。
【００３４】
図２に示すように、当該アニール処理を行わずに測定した場合の脱ガス特性（Ｒｅｆ．（Ｎｏ　ＡＮＬ））（（ａ））と比較して、処理温度４００℃では、処理時間が１８０秒（（ｂ））では未だ十分な脱ガスはなされていないが、処理時間を３００秒（（ｃ））とすれば脱ガスが十分に完了することが判る。
【００３５】
また、図３に示すように、Ｒｅｆ．（Ｎｏ　ＡＮＬ）　（（ａ））と比較して、処理温度３５０℃でも、処理時間が１８０秒（（ｂ））では未だ十分な脱ガスはなされていないが、処理時間を３００秒（（ｃ））とすれば脱ガスが十分に完了することが判る。即ち、当該アニール処理による層間絶縁膜からの脱ガス量は、処理温度には殆ど依存せず、処理時間に大きく依存することが判明した。なお、一般的なアニール処理による脱ガスを考慮すれば、Ｈ_２ガスを含む還元ガスを用いたアニール処理でも上記と同様な結果が得られるものと十分な確度をもって推定される。
【００３６】
以上の結果から、層間絶縁膜にＳＯＤ膜を適用した場合、ＮＨ_３ガス又はＨ_２ガスを含む還元ガスを用いたアニール処理において、処理時間を３００秒以上とすれば、十分な脱ガス特性が得られる。
【００３７】
このように、実験１〜３の諸結果に基づいて、Ｃｕ露出表面のＣｕ酸化物の十分な還元、ＳＯＤ膜を含む層間絶縁膜からの十分な脱ガス、及びＣｕ露出表面における熱膨張の防止の各観点を全て満足し、良好な配線構造を得るには、水素を含有する還元ガスを用いたアニール処理を、処理温度を３５０℃以下、且つ処理時間を３００秒〜６００秒の条件で実行すれば良い。
【００３８】
−配線構造の形成方法の具体的な実施形態−
上述した本発明の基本骨子を踏まえ、本発明をダマシン法（ここではいわゆるデュアルダマシン法）によるＣｕ配線の形成方法に適用した具体的な実施形態について、図面を参照しながら詳細に説明する。本実施形態では、半導体装置として一般的なＭＯＳトランジスタを例に採り、その配線構造の形成に本発明を適用する。
【００３９】
図４及び図５は、本実施形態による配線構造の形成方法を工程順に示す概略断面図である。
この配線構造を形成するにあたり、シリコンウェーハ上にゲート電極、ソース／ドレインを備えたＭＯＳトランジスタ構造を形成する。そして、このＭＯＳトランジスタ構造の例えばゲート電極と電気的に接続される配線構造に本発明が適用される。
【００４０】
先ず、図４（ａ）に示すように、シリコン半導体基板１に例えばＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｌａｔｉｏｎ）法による素子分離構造３１で画定された活性領域において、ゲート絶縁膜２を介してゲート電極３をパターン形成し、このゲート電極３の両側面にサイドウォール絶縁膜３２を形成した後、ゲート電極３の両側の半導体基板１の表層にソース／ドレイン４を形成する。そして、ゲート電極３及びソース／ドレイン４の各表面にＣｏＳｉ_Ｘ（例えばＸ＝２）からなるシリサイド層５を形成し、サリサイド構造とする。
【００４１】
続いて、ゲート電極３を覆うように、ＣＶＤ法によりシリコン窒化膜３３を形成した後、ＰＳＧ（Ｐｈｏｓｐｈｏ　ｓｉｌｉｃａｔｅ　Ｇｌａｓｓ）膜６を堆積する。そして、フォトリソグラフィー及びこれに続くエッチングにより、ゲート電極３の表面の一部を露出させるコンタクト孔をＰＳＧ膜６及びシリコン窒化膜３３に形成した後、ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法及びＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法等によりこのコンタクト孔をタングステン（Ｗ）で充填するＷプラグ７を形成する。
【００４２】
続いて、いわゆるダマシン法により下層Ｃｕ配線を形成する。
具体的には、先ず図４（ｂ）に示すように、Ｗプラグ７の表面を覆うようにＰＳＧ膜６上に有機ＳＯＤ膜、ここではポリアリールエーテル系の低誘電率膜８を塗布した後、シリコン酸化膜９を堆積し、低誘電率膜８及びシリコン酸化膜９からなる層間絶縁膜１１を形成する。
【００４３】
続いて、図４（ｃ）に示すように、層間絶縁膜１１上にフォトレジスト（不図示）を塗布し、フォトリソグラフィーによりフォトレジストを配線形状に加工する。次に、このフォトレジストをマスクとして層間絶縁膜１１をドライエッチングし、層間絶縁膜１１にフォトレジストの形状に倣った配線溝１２を形成する。
【００４４】
続いて、図４（ｄ）に示すように、ＮＨ_３ガスを含む還元ガスを用いた上述のアニール処理を実行し、層間絶縁膜１１（特に低誘電率膜８）を脱ガス処理する。このとき、Ｗの酸化、４００℃程度におけるＷの熱膨張は問題とならないため、処理時間の上限は主に脱ガス特性及びＳＯＤ膜の膜質変化の観点による制限から、当該アニール処理の具体的条件としては、処理温度を４００℃以下、且つ処理時間を３００秒以上の条件、ここでは３５０℃且つ３００秒で行う。
【００４５】
続いて、図４（ｅ）に示すように、配線溝１２の内壁面を覆うように、層間絶縁膜１１上にＴａからなるバリアメタル膜１３を、更にシード金属膜としてＣｕ膜（不図示）をスパッタ装置により真空中で連続的に堆積形成する。ここで、ＲＦ処理とバリアメタル膜１３及びシード金属膜の形成は真空中で連続的に行なうことが望ましい。
【００４６】
続いて、シード金属膜を電極として、メッキ法により配線溝１２内を埋め込む膜厚にＣｕ膜１４を形成する。ダマシン法によるＣｕ膜１４の分離のため、ＣＭＰ法によりＣｕ膜１４及びバリアメタル膜１３を研磨して配線溝１２内のみにＣｕ膜１４及びバリアメタル膜１３を残し、下層Ｃｕ配線１５を形成する。
【００４７】
図４（ｆ）に示すように、Ｃｕの拡散防止を主目的とするシリコン窒化膜１６を下層Ｃｕ配線１５を覆うように層間絶縁膜１１上に形成する。
【００４８】
続いて、下層Ｃｕ配線１５とビア孔を介して電気的に接続される上層Ｃｕ配線を形成する。
【００４９】
具体的には、先ず図５（ａ）に示すように、下層Ｃｕ配線１５の表面を覆うようにシリコン酸化膜１７を形成した後、有機ＳＯＤ膜、ここではポリアリールエーテル系の低誘電率膜１８を塗布し、更にシリコン酸化膜１９を形成し、シリコン窒化膜１６、シリコン酸化膜１７、低誘電率膜１８、及びシリコン酸化膜１９からなる層間絶縁膜２１を形成する。
【００５０】
続いて、図５（ｂ）に示すように、フォトリソグラフィー及びこれに続くエッチングにより、先ずシリコン酸化膜１９上のシリコン窒化膜（不図示）に配線パターンとなる部分を形成する。続いて、下層Ｃｕ配線１５の表面の一部を露出させるように、層間絶縁膜２１にビア孔２２を形成する。このとき、下層Ｃｕ配線１５の表面の一部を完全には露出させることなく、下層Ｃｕ配線１５上でシリコン窒化膜１６を極薄に残し、言わば前記表面の一部をほぼ露出させた状態となるようにしても良い。
【００５１】
そして、先にシリコン窒化膜に形成した配線パターン（不図示）をハードマスクとして、層間絶縁膜２１の低誘電率膜１８をエッチングストッパーとしてシリコン酸化膜１９をエッチングし、続いてシリコン酸化膜１７をエッチングストッパーとして低誘電率膜１８をエッチングし、配線溝２３を形成する。
【００５２】
続いて、図５（ｃ）に示すように、ＮＨ_３ガスを含む還元ガスを用いた上述のアニール処理を実行し、下層Ｃｕ配線１５の表面におけるＣｕ酸化物を還元して除去し、下層Ｃｕ配線１５のＣｕ表面を露出させるとともに、層間絶縁膜１１（特に低誘電率膜１８）を脱ガス処理する。当該アニール処理の具体的条件としては、処理温度を３５０℃以下、且つ処理時間を３００秒〜６００秒の条件、ここでは３５０℃且つ３００秒で行う。
【００５３】
続いて、図５（ｄ）に示すように、配線溝２３及びビア孔２２の内壁面を覆うように、層間絶縁膜２１上にＴａからなるバリアメタル膜２４を、更にシード金属膜としてＣｕ膜（不図示）をスパッタ装置により真空中で連続的に堆積形成する。ここで、ＲＦ処理とバリアメタル膜２４及びシード金属膜の形成は真空中で連続的に行なうことが望ましい。
【００５４】
続いて、シード金属膜を電極として、メッキ法により配線溝２３内及びビア孔２２内を埋め込む膜厚にＣｕ膜２５を形成する。
【００５５】
そして、ダマシン法によるＣｕ膜２５の分離のため、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法によりＣｕ膜２５及びバリアメタル膜２６を研磨して、配線溝２３内及びビア孔２２内のみにＣｕ膜２５及びバリアメタル膜２４を残し、上層Ｃｕ配線２６を形成する。
【００５６】
以上により、ビア孔２２を介して下層Ｃｕ配線１５と上層Ｃｕ配線２６とが電気的に接続されてなる配線構造が完成する。更に、上述したダマシン法を繰り返し、上層Ｃｕ配線２６と接続される配線構造を形成する場合もある。
【００５７】
しかる後、更なる層間絶縁膜やビア孔、配線等の形成を経て、前記配線構造を備えてなるＭＯＳトランジスタを完成させる。
【００５８】
以上説明したように、本実施形態の基板処理方法によれば、ＳＯＤ膜を用いて配線抵抗の低減化を図るも、酸化したＣｕ露出表面の還元処理及び当該ＳＯＤ膜の脱ガスを同一工程で同時に実行し、ダマシン法における下層Ｃｕ配線１５と上層Ｃｕ配線２６との間の良好な接続を実現し、信頼性の高いＭＯＳトランジスタを得ることができる。
【００５９】
なお、本実施形態では半導体装置としてＭＯＳトランジスタを例示したが、本発明はこれに限定されず、ダマシン法によるＣｕ配線を備えて高集積化・微細化を図る全ての半導体装置に当該配線構造を適用して好適である。
【００６０】
以下、本発明の諸態様を付記としてまとめて記載する。
【００６１】
（付記１）基板の上方で金属層の表面の一部がＳＯＤ膜を含む絶縁層から露出しており、前記表面の一部に対し、水素を含有する還元ガスを用いて、前記処理温度を３５０℃以下、且つ処理時間を３００秒〜６００秒の条件で前記基板をアニール処理することを特徴とする基板処理方法。
【００６２】
（付記２）前記還元ガスは、ＮＨ_３ガス又はＨ_２ガスを含むものであることを特徴とする付記１に記載の基板処理方法。
【００６３】
（付記３）前記ＳＯＤ膜は、低誘電率の有機ＳＯＤ材料を含むことを特徴とする付記１又は２に記載の基板処理方法。
【００６４】
（付記４）前記有機ＳＯＤ材料は、少なくともポリアリールエーテル系の低誘電率材料を含むことを特徴とする付記３に記載の基板処理方法。
【００６５】
（付記５）前記金属層が金属プラグであることを特徴とする付記１〜４のいずれか１項に記載の基板処理方法。
【００６６】
（付記６）前記金属層が配線であることを特徴とする付記１〜４のいずれか１項に記載の基板処理方法。
【００６７】
（付記７）前記配線が銅を含有する金属材料からなることを特徴とする付記６に記載の基板処理方法。
【００６８】
（付記８）基板の上方で金属層を覆うように形成されてなる第１の絶縁膜上に、少なくともＳＯＤ膜を含む第２の絶縁膜を形成する工程と、
前記金属層の表面の一部を露出させるように、前記第２の絶縁膜を加工する工程と、
前記表面の一部に対し、水素を含有する還元ガスを用いて、前記処理温度を３５０℃以下、且つ処理時間を３００秒〜６００秒の条件で前記基板をアニール処理する工程と、
前記第２の絶縁膜の加工部位を埋め込み、金属層と接続される配線を形成する工程と
を含むことを特徴とする配線構造の形成方法。
【００６９】
（付記９）前記還元ガスは、ＮＨ_３ガス又はＨ_２ガスを含むものであることを特徴とする付記８に記載の配線構造の形成方法。
【００７０】
（付記１０）前記ＳＯＤ膜は、低誘電率の有機ＳＯＤ材料を含むことを特徴とする付記８又は９に記載の配線構造の形成方法。
【００７１】
（付記１１）前記有機ＳＯＤ材料は、少なくともポリアリールエーテル系の低誘電率材料を含むことを特徴とする付記１０に記載の配線構造の形成方法。
【００７２】
（付記１２）前記金属層が金属プラグであることを特徴とする付記８〜１１のいずれか１項に記載の配線構造の形成方法。
【００７３】
（付記１３）前記金属層が前記第１の絶縁膜内に形成された下層配線であることを特徴とする付記８〜１１のいずれか１項に記載の配線構造の形成方法。
【００７４】
（付記１４）前記下層配線が銅を含有する金属材料からなることを特徴とする付記１３に記載の配線構造の形成方法。
【００７５】
（付記１５）前記第２の絶縁膜は、他の絶縁膜上に前記ＳＯＤ膜が積層されてなり、
前記第２の絶縁膜を加工するに際して、前記他の絶縁膜に前記金属層の表面の一部を露出させる接続孔を形成した後、前記第２の絶縁膜に配線形状の配線溝を形成し、
前記アニール処理の後、前記接続孔及び前記配線溝を埋め込むように前記配線を形成することを特徴とする付記１３又は１４に記載の配線構造の形成方法。
【００７６】
【発明の効果】
本発明によれば、ＳＯＤ膜を用いて配線抵抗の低減化を図るも、酸化した金属露出表面の還元処理及び当該ＳＯＤ膜の脱ガスを同一工程で同時に実行し、確実な配線間接続、特にダマシン法におけるＣｕ含有配線間の良好な接続を実現し、信頼性の高いデバイスを得ることができる。
【図面の簡単な説明】
【図１】本実施形態によるＮＨ_３ガスを用いたアニール処理を行い形成された配線構造の断面状態を示すＳＥＭによる顕微鏡写真である。
【図２】ＴＤＳにより脱ガス特性を測定した結果を示す特性図である。
【図３】ＴＤＳにより脱ガス特性を測定した結果を示す特性図である。
【図４】本実施形態による配線構造の形成方法を工程順に示す概略断面図である。
【図５】図４に引き続き、本実施形態による配線構造の形成方法を工程順に示す概略断面図である。
【符号の説明】
１　シリコン半導体基板
２　ゲート絶縁膜
３　ゲート電極
４　ソース／ドレイン
５　シリサイド層
６　ＰＳＧ膜
７　Ｗプラグ
８，１８　低誘電率膜
９，１７，１９　シリコン酸化膜
１１，２１　層間絶縁膜
１２，２３　配線溝
１３，２４　バリアメタル膜
１４，２５　Ｃｕ膜
１５　下層Ｃｕ配線
１６，１９，３３　シリコン窒化膜
２２　ビア孔
２６　上層Ｃｕ配線
３１　ＳＴＩ素子分離構造
３２　サイドウォール絶縁膜[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for processing a substrate and a method for forming a wiring structure mainly used for a semiconductor device, and is particularly suitable for application when forming a wiring structure in which a wiring is made of a material containing at least copper (Cu).
[0002]
[Prior art]
In recent years, with the increase in the degree of integration of semiconductor elements and the reduction in chip size, miniaturization of wiring and multilayer wiring have been accelerated. In a logic device having such a multilayer wiring, the wiring delay is becoming one of the dominant factors of the device signal delay. The signal delay of the device is proportional to the product of the wiring resistance value and the wiring capacitance. Therefore, in order to improve the wiring delay, it is important to reduce the wiring resistance value and the wiring capacitance (for example, see Patent Document 1). .).
[0003]
Therefore, formation of a Cu wiring has been studied in order to reduce the wiring resistance. Since it is difficult to process Cu, therefore, a so-called damascene structure, in which a wiring groove formed in an insulating film is filled with Cu via a barrier metal film, is attracting attention as a suitable structure when applying it to wiring. I have.
[0004]
[Patent Document 1]
JP-A-11-87353 (FIG. 5)
[0005]
[Problems to be solved by the invention]
In the case of a Cu wiring having a damascene structure, in order to reduce the wiring capacitance, an organic SOD (Spin On Diffusion), for example, a low dielectric constant material such as a polyarylether-based material is used as the insulating film instead of the conventional SiO _2. It is suitable.
[0006]
By the way, when a Cu wiring having a damascene structure is formed, when the lower Cu wiring and the upper Cu wiring are connected, a part of the surface of the lower Cu wiring is exposed from the insulating film. The surface is oxidized to form a Cu oxide, which may cause a connection failure. Therefore, in order to obtain good connection, it is necessary to perform a substrate treatment for reducing Cu oxide as a pretreatment for forming a barrier metal film. As the substrate processing, plasma processing using NH ₃ gas or H ₂ gas as a reducing gas is mainly used.
[0007]
However, when a low dielectric constant material film such as an organic SOD is used as the insulating film, if the plasma treatment using NH ₃ gas or H ₂ gas is performed, the low dielectric constant material film itself is etched, which is inconvenient. It becomes.
[0008]
Further, when a low dielectric constant material film is used as the insulating film, degassing is apt to occur from the low dielectric constant material film during the manufacturing process, and a reliable degassing process is required to obtain a highly reliable wiring structure. There is.
[0009]
As described above, when forming a Cu wiring structure using the damascene method, it is most effective to use a low-dielectric-constant material film such as organic SOD as an insulating film for burying the Cu wiring structure in order to reduce the wiring capacitance. However, there is a serious problem that it is extremely difficult to desirably eliminate the adverse effect on the process due to reduction and degassing of Cu oxide.
[0010]
The present invention has been made in order to solve the above-mentioned problem, and in order to reduce the wiring capacitance by using an SOD film, the reduction treatment of the oxidized metal exposed surface and the degassing of the SOD film are performed in the same step. It is an object of the present invention to provide a substrate processing method and a method for forming a wiring structure, which can be simultaneously performed to realize a reliable inter-wiring connection, in particular, a good connection between Cu-containing wirings in a damascene method and obtain a highly reliable device. Aim.
[0011]
[Means for Solving the Problems]
As a result of intensive studies, the inventor has conceived the following aspects of the invention.
[0012]
In the substrate processing method of the present invention, a part of the surface of the metal layer is exposed from the insulating layer including the SOD film above the substrate, and a part of the surface is reduced by using a reducing gas containing hydrogen. The substrate is annealed at a processing temperature of 350 ° C. or lower and a processing time of 300 to 600 seconds.
[0013]
In the method for forming a wiring structure according to the present invention, a step of forming a second insulating film including at least an SOD film on a first insulating film formed so as to cover a metal layer above a substrate; Processing the second insulating film so as to expose a part of the surface of the layer, and treating the part of the surface with a reducing gas containing hydrogen, the treatment temperature being 350 ° C. or lower, And a step of annealing the substrate under a processing time of 300 to 600 seconds, and a step of burying a processed portion of the second insulating film and forming a wiring connected to a metal layer.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
-Basic gist of the present invention-
First, the basic gist of the present invention will be described together with its working principle.
In the present invention, when reducing the metal oxide film on the exposed metal surface (here, for convenience, the surface of the lower Cu wiring in the damascene method is referred to as the exposed surface, and the Cu oxide is referred to as the metal oxide film), the SOD film is reduced. In consideration of the effect of the above, an annealing process using a reducing gas containing hydrogen such as NH ₃ gas or H ₂ gas is used instead of performing the plasma process.
[0015]
The present inventor has confirmed that the annealing treatment can reduce the Cu oxide in consideration of performing the degassing which is essential when the SOD film is used, in addition to the reduction of the Cu oxide which is its original purpose. From the viewpoint of reducing the SOD film and sufficiently degassing the SOD film, it has been conceived to optimize each condition of the annealing process, specifically, the processing temperature and the processing time from the correlation between the two.
[0016]
(Experiment 1)
Here, the reduction ability when an annealing process was performed using a reducing gas as a mixed gas of NH ₃ gas and N ₂ gas was examined. Specifically, a Cu film is formed by sputtering, the surface is forcibly oxidized at 150 ° C. for 10 minutes in the air, and then an annealing process is performed using NH ₃ gas. And the reflectance of the Cu film surface after the reduction was measured. Table 1 shows the measurement results. The partial pressure of the NH ₃ gas was set to 1.27 Torr (Ｐａ170 (Pa)) and 2.2 Torr (に つ い て) for the processing temperature of 350 ° C. and the processing time of 300 seconds and the processing temperature of 400 ° C. and the processing time of 180 seconds. 293 (Pa)) and 4.0 (≒ 533 (Pa)) Torr, the relative reflectance (%) was measured.
[0017]
[Table 1]

[0018]
From Table 1, in the annealing treatment for the 400 ° C. The treatment temperature, but not so much difference is seen in reflectance by changing the partial pressure of NH ₃ gas, in the case where the treatment temperature was set to 350 ° C., the NH ₃ gas It can be seen that the higher the partial pressure, the better the reduction ability.
[0019]
Therefore, using a substrate different from the case of the measurement in Table 1, the partial pressure of the NH ₃ gas was fixed, and an appropriate processing time was examined particularly when the processing temperature was 400 ° C. Table 2 shows the measurement results. Here, NH ₃ / N ₂ constituting the mixed gas was 3850 cc / 2800 cc, and the partial pressure of the NH ₃ gas was 2.2 Torr (≒ 293 (Pa)).
[0020]
[Table 2]

[0021]
From Table 2, it can be seen that in the annealing treatment at a treatment temperature of 400 ° C., a sufficient reduction ability is observed even when the treatment time is 60 seconds. When the processing temperature is set to 350 ° C., although it is inferior to the processing at 400 ° C., it is inferior to the normal reducing ability.
[0022]
Further, a substrate different from that used in the measurement of Table 1 and Table 2 was used, and NH ₃ / N ₂ constituting the mixed gas was 3850 cc / 2800 cc and the partial pressure of NH ₃ gas was 2.2 Torr as in the measurement of Table 2. (≒ 293 (Pa)), and the reflectance at 633 nm light was measured including the case where the processing temperature was 300 ° C. Table 3 shows the measurement results.
[0023]
[Table 3]

[0024]
From Table 3, it was reconfirmed that the reducing ability was insufficient by annealing at a processing temperature of 300 ° C., but sufficient reducing ability was obtained at 400 ° C. It has been shown.
[0025]
Similarly, a Cu film is formed by sputtering as described above, and the surface is forcibly oxidized at 150 ° C. for 10 minutes in the air, and a reducing gas is used as a mixed gas of H ₂ gas and N ₂ gas. The reduction ability when the annealing treatment was performed was examined. Table 3 shows the results. When the processing temperature was 350 ° C., the relative reflectance (%) was measured when the partial pressure of the H ₂ gas was 3 Torr (≒ 400 (Pa)).
[0026]
[Table 4]

[0027]
From Table 4, it can be seen that the H ₂ annealing treatment at a treatment temperature of 350 ° C. and a treatment time of 180 seconds shows sufficient reduction ability.
[0028]
From the above results, in the annealing treatment using a reducing gas containing NH ₃ gas or H ₂ gas, from the viewpoint of sufficiently reducing the exposed Cu surface, if the treatment temperature is set to 400 ° C., a short treatment is sufficient. Reduction can be obtained, and good reduction can be obtained even at 350 ° C. if the treatment time is relatively long (300 seconds or more).
[0029]
(Experiment 2)
By the way, in the annealing process, the Cu surface exposed at the bottom of the via hole may thermally expand depending on the condition, and it is necessary to suppress this. Therefore, the processing time was changed for the processing temperatures of 400 ° C. and 300 ° C., and the cross-sectional state of the wiring structure formed by performing the above-described annealing using the NH ₃ gas by the damascene method was observed by a scanning electron microscope (SEM). I checked.
[0030]
The observation results are shown in FIG.
Compared with the reference photograph (Ref. (No ANL)) ((a)) of the cross-sectional state of the wiring structure formed without performing the annealing treatment, the processing temperature is 400 ° C. ((b)), Specifically, it can be seen that thermal expansion occurs on the Cu surface exposed at the bottom of the via hole even when the processing time is 60 seconds. On the other hand, when the processing temperature is 350 ° C. ((c)), the Cu surface exposed at the bottom of the via hole does not show any thermal expansion even when the processing time is long, specifically the processing time is 300 seconds. Only slight thermal expansion is observed. In general, in consideration of the gas reducing ability, it is estimated with sufficient accuracy that the same result as described above can be obtained even in an annealing process using a reducing gas containing H ₂ gas.
[0031]
From the above results, in the annealing using a reducing gas containing NH ₃ gas or H ₂ gas, from the viewpoint of preventing the thermal expansion of the exposed Cu surface, if the processing temperature is set to 350 ° C. or lower, a relatively long time ( Thermal expansion can be suppressed even with a processing time of 300 seconds or more). In this case, the appropriate processing time is 300 seconds to 600 seconds.
[0032]
(Experiment 3)
Subsequently, the outgassing ability by the annealing treatment was examined. Here, a polyarylether-based material (so-called SiLK), which is an organic SOD film, is used as the interlayer insulating film, and after performing the annealing treatment, degassing characteristics are determined by thermal desorption spectroscopy (TDS). Was measured.
[0033]
The measurement results are shown in FIGS.
FIG. 2 shows the degassing characteristics when performing an annealing process at a processing temperature of 400 ° C. using a reducing gas containing NH ₃ gas, and FIG. 3 shows the degassing characteristics at a processing temperature of 350 ° C. using a reducing gas containing NH ₃ gas. The degassing characteristics at the time of performing the annealing treatment are shown, and in each figure, water (steam) which is regarded as the most problematic as degassing from the SOD film when the temperature is raised from room temperature to about 600 ° C. The amount of outgas (that is, the amount of residual gas in the interlayer insulating film after the annealing process) is represented by a relative value.
[0034]
As shown in FIG. 2, compared with the degassing characteristic (Ref. (No ANL)) ((a)) measured without performing the annealing, the processing time was 180 seconds at the processing temperature of 400 ° C. In ((b)), sufficient degassing has not yet been performed, but it can be seen that degassing is sufficiently completed if the processing time is 300 seconds ((c)).
[0035]
In addition, as shown in FIG. (No ANL) Compared to ((a)), even at a processing temperature of 350 ° C., the processing time was 180 seconds ((b)), but sufficient degassing was not yet performed, but the processing time was 300 seconds ((c) )) Indicates that the degassing is sufficiently completed. That is, it has been found that the amount of outgas from the interlayer insulating film by the annealing treatment hardly depends on the processing temperature, but largely depends on the processing time. In consideration of degassing due to general annealing, it is estimated with sufficient accuracy that the same result as described above can be obtained even with annealing using a reducing gas containing H ₂ gas.
[0036]
From the above results, when the SOD film is applied to the interlayer insulating film, if the processing time is set to 300 seconds or more in the annealing process using the reducing gas containing NH ₃ gas or H ₂ gas, sufficient degassing characteristics can be obtained. can get.
[0037]
Thus, based on the results of Experiments 1 to 3, sufficient reduction of the Cu oxide on the Cu-exposed surface, sufficient degassing from the interlayer insulating film including the SOD film, and prevention of thermal expansion on the Cu-exposed surface In order to satisfy all of the above points and obtain a good wiring structure, an annealing process using a reducing gas containing hydrogen is performed at a processing temperature of 350 ° C. or lower and a processing time of 300 seconds to 600 seconds. Just do it.
[0038]
-Specific embodiment of the wiring structure forming method-
Based on the basic gist of the present invention described above, a specific embodiment in which the present invention is applied to a method of forming a Cu wiring by a damascene method (here, a so-called dual damascene method) will be described in detail with reference to the drawings. In the present embodiment, a general MOS transistor is taken as an example of a semiconductor device, and the present invention is applied to the formation of the wiring structure.
[0039]
4 and 5 are schematic sectional views showing the method for forming the wiring structure according to the present embodiment in the order of steps.
In forming this wiring structure, a MOS transistor structure having a gate electrode and a source / drain is formed on a silicon wafer. The present invention is applied to a wiring structure electrically connected to, for example, a gate electrode of the MOS transistor structure.
[0040]
First, as shown in FIG. 4A, a gate electrode 3 is patterned on a silicon semiconductor substrate 1 via a gate insulating film 2 in an active region defined by an element isolation structure 31 by, for example, STI (Shallow Trench Isolation) method. After forming the sidewall insulating films 32 on both sides of the gate electrode 3, the source / drain 4 is formed on the surface layer of the semiconductor substrate 1 on both sides of the gate electrode 3. Then, a silicide layer 5 made of CoSi _x (for example, X = 2) is formed on each surface of the gate electrode 3 and the source / drain 4 to form a salicide structure.
[0041]
Subsequently, after a silicon nitride film 33 is formed by a CVD method so as to cover the gate electrode 3, a PSG (phosphosilicate glass) film 6 is deposited. Then, a contact hole exposing a part of the surface of the gate electrode 3 is formed in the PSG film 6 and the silicon nitride film 33 by photolithography and subsequent etching, and thereafter, a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical) method. A W plug 7 that fills this contact hole with tungsten (W) is formed by a polishing method or the like.
[0042]
Subsequently, a lower Cu wiring is formed by a so-called damascene method.
Specifically, first, as shown in FIG. 4B, an organic SOD film, here, a polyarylether-based low dielectric constant film 8 is applied on the PSG film 6 so as to cover the surface of the W plug 7. Then, a silicon oxide film 9 is deposited, and an interlayer insulating film 11 composed of the low dielectric constant film 8 and the silicon oxide film 9 is formed.
[0043]
Subsequently, as shown in FIG. 4C, a photoresist (not shown) is applied on the interlayer insulating film 11, and the photoresist is processed into a wiring shape by photolithography. Next, the interlayer insulating film 11 is dry-etched using the photoresist as a mask to form a wiring groove 12 in the interlayer insulating film 11 according to the shape of the photoresist.
[0044]
Subsequently, as shown in FIG. 4D, the above-described annealing using a reducing gas containing NH ₃ gas is performed to degas the interlayer insulating film 11 (particularly, the low dielectric constant film 8). At this time, since the oxidation of W and the thermal expansion of W at about 400 ° C. do not pose a problem, the upper limit of the processing time is mainly determined by the degassing characteristics and the change in the film quality of the SOD film. The processing is performed at a processing temperature of 400 ° C. or lower and a processing time of 300 seconds or longer, here, 350 ° C. and 300 seconds.
[0045]
Subsequently, as shown in FIG. 4E, a barrier metal film 13 made of Ta is formed on the interlayer insulating film 11 so as to cover the inner wall surface of the wiring groove 12, and a Cu film (not shown) is further formed as a seed metal film. Is continuously deposited and formed in a vacuum by a sputtering apparatus. Here, it is desirable that the RF treatment and the formation of the barrier metal film 13 and the seed metal film be performed continuously in a vacuum.
[0046]
Subsequently, using the seed metal film as an electrode, a Cu film 14 is formed by plating so as to fill the wiring groove 12. In order to separate the Cu film 14 by the damascene method, the Cu film 14 and the barrier metal film 13 are polished by the CMP method to leave the Cu film 14 and the barrier metal film 13 only in the wiring groove 12 and form the lower Cu wiring 15. .
[0047]
As shown in FIG. 4F, a silicon nitride film 16 mainly for preventing Cu diffusion is formed on the interlayer insulating film 11 so as to cover the lower Cu wiring 15.
[0048]
Subsequently, an upper Cu wiring electrically connected to the lower Cu wiring 15 via the via hole is formed.
[0049]
Specifically, first, as shown in FIG. 5A, after a silicon oxide film 17 is formed so as to cover the surface of the lower Cu wiring 15, an organic SOD film, here, a polyarylether-based low dielectric constant film is used. Then, a silicon oxide film 19 is formed, and an interlayer insulating film 21 composed of the silicon nitride film 16, the silicon oxide film 17, the low dielectric constant film 18, and the silicon oxide film 19 is formed.
[0050]
Subsequently, as shown in FIG. 5B, a portion serving as a wiring pattern is first formed on the silicon nitride film (not shown) on the silicon oxide film 19 by photolithography and subsequent etching. Subsequently, a via hole 22 is formed in the interlayer insulating film 21 so as to expose a part of the surface of the lower Cu wiring 15. At this time, the silicon nitride film 16 is left extremely thin on the lower Cu wiring 15 without completely exposing a part of the surface of the lower Cu wiring 15, that is, a state in which a part of the surface is almost exposed. You may make it.
[0051]
Then, the silicon oxide film 19 is etched using the wiring pattern (not shown) previously formed on the silicon nitride film as a hard mask and the low dielectric constant film 18 of the interlayer insulating film 21 as an etching stopper. The wiring groove 23 is formed by etching the low dielectric constant film 18 as an etching stopper.
[0052]
Subsequently, as shown in FIG. 5C, the above-described annealing treatment using a reducing gas containing NH ₃ gas is performed to reduce and remove the Cu oxide on the surface of the lower Cu wiring 15 to remove the lower Cu Cu. The Cu surface of the wiring 15 is exposed, and the interlayer insulating film 11 (particularly, the low dielectric constant film 18) is degassed. As specific conditions for the annealing, the annealing is performed at a temperature of 350 ° C. or less and a processing time of 300 seconds to 600 seconds, here, 350 ° C. and 300 seconds.
[0053]
Subsequently, as shown in FIG. 5D, a barrier metal film 24 made of Ta is formed on the interlayer insulating film 21 so as to cover the inner wall surfaces of the wiring groove 23 and the via hole 22, and a Cu film is formed as a seed metal film. (Not shown) are continuously deposited and formed in a vacuum by a sputtering apparatus. Here, it is desirable that the RF treatment and the formation of the barrier metal film 24 and the seed metal film are continuously performed in a vacuum.
[0054]
Subsequently, using the seed metal film as an electrode, a Cu film 25 is formed by plating so as to fill the wiring groove 23 and the via hole 22.
[0055]
Then, in order to separate the Cu film 25 by the damascene method, the Cu film 25 and the barrier metal film 26 are polished by a CMP (Chemical Mechanical Polishing) method, and the Cu film 25 and the barrier film are formed only in the wiring groove 23 and the via hole 22. The upper Cu wiring 26 is formed while leaving the metal film 24.
[0056]
As described above, a wiring structure in which the lower Cu wiring 15 and the upper Cu wiring 26 are electrically connected via the via holes 22 is completed. Further, the above-described damascene method may be repeated to form a wiring structure connected to the upper Cu wiring 26.
[0057]
Thereafter, through further formation of an interlayer insulating film, a via hole, a wiring, and the like, a MOS transistor having the wiring structure is completed.
[0058]
As described above, according to the substrate processing method of the present embodiment, while reducing the wiring resistance using the SOD film, the reduction treatment of the oxidized Cu exposed surface and the degassing of the SOD film are performed in the same step. Simultaneously, a good connection between the lower Cu wiring 15 and the upper Cu wiring 26 in the damascene method is realized, and a highly reliable MOS transistor can be obtained.
[0059]
In the present embodiment, a MOS transistor has been exemplified as a semiconductor device. However, the present invention is not limited to this, and the wiring structure is applied to all semiconductor devices provided with Cu wiring by a damascene method to achieve high integration and miniaturization. It is suitable for application.
[0060]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0061]
(Supplementary Note 1) A part of the surface of the metal layer is exposed from the insulating layer including the SOD film above the substrate, and the processing temperature is reduced on a part of the surface by using a reducing gas containing hydrogen. A substrate processing method, wherein the substrate is annealed at a temperature of 350 ° C. or less and a processing time of 300 seconds to 600 seconds.
[0062]
(Supplementary Note 2) The substrate processing method according to Supplementary Note 1, wherein the reducing gas includes NH ₃ gas or H ₂ gas.
[0063]
(Supplementary Note 3) The substrate processing method according to Supplementary Note 1 or 2, wherein the SOD film includes an organic SOD material having a low dielectric constant.
[0064]
(Supplementary Note 4) The substrate processing method according to Supplementary Note 3, wherein the organic SOD material includes at least a polyarylether-based low dielectric constant material.
[0065]
(Supplementary note 5) The substrate processing method according to any one of Supplementary notes 1 to 4, wherein the metal layer is a metal plug.
[0066]
(Supplementary note 6) The substrate processing method according to any one of Supplementary notes 1 to 4, wherein the metal layer is a wiring.
[0067]
(Supplementary note 7) The substrate processing method according to supplementary note 6, wherein the wiring is made of a metal material containing copper.
[0068]
(Supplementary Note 8) a step of forming a second insulating film including at least an SOD film on the first insulating film formed so as to cover the metal layer above the substrate;
Processing the second insulating film so as to expose a part of the surface of the metal layer;
Using a reducing gas containing hydrogen on a part of the surface, annealing the substrate at a processing temperature of 350 ° C. or lower and a processing time of 300 to 600 seconds;
Forming a wiring connected to a metal layer by burying a processed portion of the second insulating film.
[0069]
(Supplementary Note 9) The reducing gas to a method for forming a wiring structure according to note 8, characterized in that those containing NH ₃ gas or H ₂ gas.
[0070]
(Supplementary note 10) The method for forming a wiring structure according to Supplementary note 8 or 9, wherein the SOD film includes an organic SOD material having a low dielectric constant.
[0071]
(Supplementary note 11) The method for forming a wiring structure according to supplementary note 10, wherein the organic SOD material includes at least a polyarylether-based low dielectric constant material.
[0072]
(Supplementary Note 12) The method for forming a wiring structure according to any one of Supplementary Notes 8 to 11, wherein the metal layer is a metal plug.
[0073]
(Supplementary note 13) The method for forming a wiring structure according to any one of Supplementary notes 8 to 11, wherein the metal layer is a lower wiring formed in the first insulating film.
[0074]
(Supplementary note 14) The method for forming a wiring structure according to supplementary note 13, wherein the lower layer wiring is made of a metal material containing copper.
[0075]
(Supplementary Note 15) The second insulating film is formed by stacking the SOD film on another insulating film,
In processing the second insulating film, after forming a connection hole exposing a part of the surface of the metal layer in the other insulating film, a wiring groove having a wiring shape is formed in the second insulating film. ,
15. The method for forming a wiring structure according to claim 13, wherein the wiring is formed so as to fill the connection hole and the wiring groove after the annealing.
[0076]
【The invention's effect】
According to the present invention, while reducing the wiring resistance by using the SOD film, the reduction treatment of the oxidized metal exposed surface and the degassing of the SOD film are simultaneously performed in the same step, and a reliable interconnection connection, particularly, Good connection between Cu-containing wirings in the damascene method can be realized, and a highly reliable device can be obtained.
[Brief description of the drawings]
FIG. 1 is a SEM micrograph showing a cross-sectional state of a wiring structure formed by performing an annealing process using NH ₃ gas according to the present embodiment.
FIG. 2 is a characteristic diagram showing a result of measuring degassing characteristics by TDS.
FIG. 3 is a characteristic diagram showing a result of measuring degassing characteristics by TDS.
FIG. 4 is a schematic cross-sectional view showing a method of forming a wiring structure according to the present embodiment in the order of steps;
FIG. 5 is a schematic cross-sectional view showing a method of forming the wiring structure according to the present embodiment in the order of steps, following FIG. 4;
[Explanation of symbols]
Reference Signs List 1 silicon semiconductor substrate 2 gate insulating film 3 gate electrode 4 source / drain 5 silicide layer 6 PSG film 7 W plug 8, 18 low dielectric constant film 9, 17, 19 silicon oxide film 11, 21 interlayer insulating film 12, 23 wiring groove 13, 24 Barrier metal film 14, 25 Cu film 15 Lower Cu wiring 16, 19, 33 Silicon nitride film 22 Via hole 26 Upper Cu wiring 31 STI element isolation structure 32 Side wall insulating film

Claims (10)

A part of the surface of the metal layer is exposed from the insulating layer including the SOD film. A substrate processing method, wherein the substrate is annealed under conditions of 300 seconds to 600 seconds. The method of claim 1, wherein the reducing gas contains NH ₃ gas or H ₂ gas. 3. The substrate processing method according to claim 1, wherein the SOD film includes a low dielectric constant organic SOD material. The substrate processing method according to claim 1, wherein the metal layer is a wiring. 5. The method according to claim 4, wherein the wiring is made of a metal material containing copper. Forming a second insulating film including at least an SOD film on the first insulating film formed so as to cover the metal layer above the substrate;
Processing the second insulating film so as to expose a part of the surface of the metal layer;
Using a reducing gas containing hydrogen on a part of the surface, annealing the substrate at a processing temperature of 350 ° C. or lower and a processing time of 300 to 600 seconds;
Forming a wiring connected to a metal layer by burying a processed portion of the second insulating film. 7. The method according to claim 6, wherein the reducing gas contains NH ₃ gas or H ₂ gas. The method according to claim 6, wherein the SOD film includes a low dielectric constant organic SOD material. The method according to any one of claims 6 to 8, wherein the metal layer is a lower wiring formed in the first insulating film. The method according to claim 9, wherein the lower layer wiring is made of a metal material containing copper.

Images