JP2004134714A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve avalanche resistance in a super junction semiconductor device having such a parallel pn structure that a drift layer is formed by bonding alternately and repeatedly a drift area formed of an n-type semiconductor area with higher impurity concentration and a partitioning area formed of a p-type semiconductor area. <P>SOLUTION: In a parallel junction layer 2 forming the drift layer that allows a current to flow in an ON state and causes depletion in an OFF state, the concentration of a center 211 is higher than that of a side 212 close to a junction surface with an n-type semiconductor area 220 of the parallel pn junction layer 2, with respect to an impurity concentration in the horizontal direction in a p-type semiconductor area 210. In addition, the concentration of the center 221 is higher than that of a side 222 close to a junction surface with the p-type semiconductor area 210 of the parallel pn junction layer 2, with respect to an impurity concentration in the horizontal direction in the n-type semiconductor area 220. In this case, the total impurity quantity of the p-type semiconductor area 210 is made larger than that of the n-type semiconductor area 220. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, a partition region made of a first conductivity type semiconductor extending from a first main surface side to a second main surface side of a semiconductor substrate and a drift region made of a second conductivity type semiconductor extending similarly thereto are provided. Having a configuration in which parallel pn junction layers are alternately and repeatedly joined in a direction intersecting with the direction in which they extend, in which a current flows when the parallel pn junction layer is in an on state and depletes when the parallel pn junction layer is in an off state. Regarding a semiconductor element to be a layer, in particular, a superconductor capable of achieving both high withstand voltage and large current capacity applicable to MOSFET (insulated gate field effect transistor), IGBT (insulated gate bipolar transistor), bipolar transistor, and the like. The present invention relates to a junction semiconductor device.
[0002]
[Prior art]
Generally, super-junction semiconductor elements are classified into a horizontal element having electrodes formed on one side and a vertical element having electrodes on both sides. In the vertical semiconductor device, the direction in which the drift current flows in the ON state is the same as the direction in which the depletion layer is extended by the reverse bias voltage in the OFF state. In a normal planar n-channel vertical MOSFET, a high-resistance n-channel ⁻ The portion of the drift layer functions as a region where a drift current flows in the vertical direction when in the ON state. Therefore, this n ⁻ If the current path of the drift layer is shortened, the drift resistance is reduced, and the effect that the substantial on-resistance of the MOSFET is reduced is obtained.
[0003]
On the other hand, high resistance n ⁻ The drift layer is depleted when in the off state to increase the breakdown voltage. Therefore, n ⁻ When the thickness of the drift layer is reduced, the width of the drain-base depletion layer which progresses from the pn junction between the P base region and the drift region is reduced, and the critical electric field strength of silicon is quickly reached. . Conversely, in a semiconductor element having a high withstand voltage, n ⁻ Since the drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between the on-resistance and the withstand voltage.
[0004]
It is known that this trade-off relationship is similarly established in semiconductor devices such as IGBTs, bipolar transistors, and diodes. This trade-off relationship is also common to a lateral semiconductor device in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different.
[0005]
As a solution to the above-described problem due to the trade-off relationship, a parallel pn structure in which a drift layer is formed by alternately and repeatedly joining a drift region made of an n-type semiconductor region and a partition region made of a p-type semiconductor region with an increased impurity concentration, Are known (for example, see Patent Literature 1, Patent Literature 2, Patent Literature 3, and Patent Literature 4). In the semiconductor device having such a structure, even when the impurity concentration of the parallel pn structure is high, the depletion layer extends in the lateral direction from each pn junction extending in the vertical direction of the parallel pn structure in the off state, and the entire drift region Is depleted, so that a high breakdown voltage can be achieved.
[0006]
[Patent Document 1]
European Patent No. 0053854
[Patent Document 2]
U.S. Pat. No. 5,216,275
[Patent Document 3]
U.S. Pat. No. 5,438,215
[Patent Document 4]
JP-A-9-26631
[0007]
Here, in order to obtain a low on-resistance while ensuring a withstand voltage in the super-junction semiconductor element, the total impurity amount of the n-type semiconductor region and the p-type semiconductor region is made substantially the same, and the impurity concentration in the depth direction in each region. Must be substantially uniform. For example, in order to make the total impurity amounts of the n-type semiconductor region and the p-type semiconductor region substantially the same, when the widths of the n-type semiconductor region and the p-type semiconductor region are the same, the impurity concentrations may be made substantially the same.
[0008]
[Problems to be solved by the invention]
However, the conventional superjunction semiconductor element has a problem that since the operating resistance at the time of avalanche breakdown becomes negative resistance, local concentration is likely to occur due to the avalanche current, and a sufficient avalanche resistance cannot be secured.
[0009]
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device with improved avalanche withstand capability.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a low resistance layer and a parallel pn junction layer between a first main surface and a second main surface of a semiconductor substrate. Concerning the impurity concentration in the lateral direction in the first conductivity type semiconductor region of the layer, the concentration at the center is higher than the concentration at the side close to the junction surface with the second conductivity type semiconductor region. In the parallel pn junction layer, the first conductivity type semiconductor region and the second conductivity type semiconductor region extend in the vertical direction from the first main surface side to the second main surface side of the semiconductor substrate and alternate in the horizontal direction. To form a structure repeatedly joined. The parallel pn junction layer forms a drift layer that conducts current when in the on state and depletes in the off state.
[0011]
In the present invention, the impurity concentration in the lateral direction in the second conductivity type semiconductor region of the parallel pn junction layer may be substantially uniform. Further, similarly to the above-described lateral impurity concentration in the first conductivity type semiconductor region, the concentration of the parallel pn junction layer at the central portion of the second conductivity type semiconductor region is lower than the concentration at the junction surface with the first conductivity type semiconductor region. It may be higher than the concentration on the near side.
[0012]
Further, in order not to cause a decrease in breakdown voltage, the lateral width of the central portion of the first conductivity type semiconductor region of the parallel pn junction layer is １ ／ of the lateral width of the first conductivity type semiconductor region. It is good to be the following. The same applies to the second conductivity type semiconductor region of the parallel pn junction layer, and the lateral width of the central portion is preferably equal to or less than の of the lateral width of the second conductivity type semiconductor region.
[0013]
Further, the impurity concentration in the vertical direction of the first conductivity type semiconductor region of the parallel pn junction layer may be higher at the center. At this time, the concentration and the thickness in the vertical direction at the end portion on the second main surface side, which is lower in concentration than the center portion, are the same as those in the side portion close to the junction surface with the second conductivity type semiconductor region. It should be almost the same as the width.
[0014]
The same applies to the second conductivity type semiconductor region of the parallel pn junction layer, and the impurity concentration in the central portion in the vertical direction may be high. In the case of the second conductivity type semiconductor region, the concentration and the vertical thickness of the end portion on the first main surface side, which is lower in concentration than the central portion, are closer to the bonding surface with the first conductivity type semiconductor region. It is preferable that the density and the width in the lateral direction are substantially the same. In the case where both the first conductivity type semiconductor region and the second conductivity type semiconductor region of the parallel pn junction layer have a high impurity concentration at the center in the vertical direction, the second main region of the first conductivity type semiconductor region is It is preferable that the vertical thickness of the end on the surface side is smaller than the vertical thickness of the end on the first main surface side of the second conductivity type semiconductor region.
[0015]
Further, the first conductivity type semiconductor region and the second conductivity type semiconductor region of the parallel pn junction layer may be arranged in a stripe shape. When the first conductivity type is p-type and the second conductivity type is n-type, the impurity concentration at the center of the p-type semiconductor region in the parallel pn junction layer is Should be higher than the impurity concentration.
[0016]
According to the present invention, when avalanche occurs in the parallel pn junction layer, holes flow through the central part of the p-type semiconductor region and escape to the electrode due to the potential distribution of the parallel pn junction layer, while electrons flow to the n-type semiconductor. The gas flows through the center of the region and escapes to the electrode. At this time, since the impurity concentration in the center of the p-type semiconductor region is high, the charge balance at the time of avalanche generation is ensured. Further, since the impurity concentration in the central portion of the n-type semiconductor region is high, a charge balance at the time of occurrence of avalanche is secured.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present specification, a direction from the front surface side to the back surface side of the semiconductor substrate is defined as a vertical direction, and a direction crossing the direction is defined as a horizontal direction.
[0018]
Embodiment 1 FIG.
FIG. 1 is a longitudinal sectional view illustrating a configuration of the super junction semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the parallel pn junction layer 2 has a stripe shape in which a p-type semiconductor region 210 extending in a vertical direction and an n-type semiconductor region 220 extending in a vertical direction are alternately and repeatedly joined in a horizontal direction. It has a configuration. Due to the difference in impurity concentration, the p-type semiconductor region 210 is divided into a central portion 211 having a relatively high impurity concentration and a side portion 212 having a relatively low impurity concentration which is closer to the junction surface with the n-type semiconductor region 220. Can be The impurity concentration of the n-type semiconductor region 220 is substantially uniform.
[0019]
Between the parallel pn junction layer 2 and the drain electrode 11 on the back surface of the substrate, n is a low resistance layer. ⁺⁺ It is the drain layer 1. On the substrate surface side, the surface n-type drift region 3, p-type base region 4, p-type ⁺ Contact region 5, n ⁺ A source region 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, and a source electrode 10 are formed.
[0020]
For example, in the p-type semiconductor region 210, the impurity concentration in the central portion 211 is 3.31 × 10 ^Fifteen cm ^-3 And the impurity concentration of the side part 212 is 3.01 × 10 ^Fifteen cm ^-3 It is. The impurity concentration of the n-type semiconductor region 220 is 3.01 × 10 ^Fifteen cm ^-3 It is about. FIG. 2 shows the impurity concentration distribution along AA ′ in FIG.
[0021]
Further, for example, the lateral width of each of p-type semiconductor region 210 and n-type semiconductor region 220 is 7 μm. The width of the central portion 211 of the p-type semiconductor region 210 in the horizontal direction is equal to or less than half the width of the p-type semiconductor region 210 in the horizontal direction, and is, for example, 3 μm. The impurity concentration of the side portion 212 of the p-type semiconductor region 210 is 3.01 × 10 3 ^Fifteen cm ^-3 Is 2 μm in the horizontal direction. The length in the vertical direction of the parallel pn junction layer 2 in the p-type semiconductor region 210 is about 40 μm.
[0022]
FIG. 3 is a diagram showing a current-voltage waveform in a large current region when the concentration of the central portion 211 of the p-type semiconductor region 210 is changed. As is apparent from FIG. 3, when the central portion 211 of the p-type semiconductor region 210 has the same impurity concentration as the side portion 212, that is, when the impurity concentration of the p-type semiconductor region 210 is uniform, it is indicated by a solid line. Thus, in the large current region, the resistance is negative. In this case, the electric field becomes strong in the region where avalanche has occurred, causing avalanche destruction.
[0023]
On the other hand, when the impurity concentration in the central portion 211 of the p-type semiconductor region 210 is high, as shown by a broken line or a dotted line in FIG. ing. In this case, since the avalanche current flows and the breakdown voltage increases, avalanche occurs in the entire high impurity concentration region of the p-type semiconductor region 210. Therefore, concentration of avalanche current does not occur, so that avalanche withstand capability is improved.
[0024]
FIG. 4 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. In the super-junction semiconductor device shown in FIG. 4, the end 213 of the p-type semiconductor region 210 on the substrate back side, that is, n ⁺⁺ The impurity concentration of the portion in contact with the drain layer 1 is substantially the same as the impurity concentration of the side portion 212 described above. FIG. 5 shows an impurity concentration distribution along BB ′ and CC ′ in FIG. Further, n of the p-type semiconductor region 210 ⁺⁺ In a portion (end 213) in contact with drain layer 1, a portion having the same impurity concentration as side portion 212 has a depth of, for example, 2 μm.
[0025]
FIG. 6 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. In the superjunction semiconductor element shown in FIG. 6, the depth of central portion 211 of p-type semiconductor region 210 is, for example, 20 μm, and the depth of n of p-type semiconductor region 210 is n. ⁺⁺ In a portion (end portion 213) in contact with drain layer 1, the depth of a portion having the same impurity concentration as side portion 212 is, for example, 20 μm.
[0026]
According to the first embodiment, when avalanche occurs in parallel pn junction layer 2, holes flow through central portion 211 of p-type semiconductor region 210 to source electrode 10 due to the potential distribution of parallel pn junction layer 2. However, since the impurity concentration in the central portion 211 is high, the charge balance is secured when holes flow and are stored on the surface side. Therefore, the negative resistance is improved, and the avalanche resistance is improved.
[0027]
Although the first conductivity type is described as p-type and the second conductivity type is described as n-type in Embodiment 1, the same applies to the opposite case. That is, electrons generated by avalanche flow through the central portion of the n-type semiconductor region where the impurity concentration is high due to the potential distribution of the parallel pn junction layer, so that the charge balance is secured, the negative resistance is improved, and the avalanche withstand capability is improved. Is improved.
[0028]
Embodiment 2 FIG.
FIG. 7 is a longitudinal sectional view illustrating the configuration of the super junction semiconductor device according to the second embodiment of the present invention. As shown in FIG. 7, in the second embodiment, not only the p-type semiconductor region 210 but also the n-type semiconductor region 220 has a relatively high impurity concentration in the central portion 221 and the p-type semiconductor region due to the difference in impurity concentration. It is divided into a side portion 222 which is close to the junction surface with the region 210 and has a relatively low impurity concentration. However, the impurity concentration of the central portion 211 of the p-type semiconductor region 210 is higher than the impurity concentration of the central portion 221 of the n-type semiconductor region 220. Reference numeral 223 denotes an end of the second conductivity type semiconductor region. Other configurations are the same as those of the first embodiment, and therefore, the same reference numerals as those of the first embodiment are used and the description is omitted.
[0029]
In the second embodiment, for example, in p-type semiconductor region 210, the impurity concentration of central portion 211 is 3.61 × 10 ^Fifteen cm ^-3 And the impurity concentration of the side part 212 is 3.01 × 10 ^Fifteen cm ^-3 It is. In the n-type semiconductor region 220, the impurity concentration of the central portion 221 is 3.31 × 10 ^Fifteen cm ^-3 And the impurity concentration of the side part 222 is 3.01 × 10 ^Fifteen cm ^-3 It is. FIG. 8 shows the impurity concentration distribution along DD ′ in FIG.
[0030]
Further, for example, the lateral width of each of p-type semiconductor region 210 and n-type semiconductor region 220 is 7 μm. The lateral width of central portion 211 of p-type semiconductor region 210 is not more than half the lateral width of p-type semiconductor region 210, and is, for example, 3 μm. The impurity concentration of the side portion 212 of the p-type semiconductor region 210 is 3.01 × 10 3 ^Fifteen cm ^-3 Is 2 μm in the horizontal direction.
[0031]
The lateral width of the central portion 221 of the n-type semiconductor region 220 is equal to or less than の of the lateral width of the n-type semiconductor region 220, for example, 3 μm. The impurity concentration of the side portion 222 of the n-type semiconductor region 220 is 3.01 × 10 3 ^Fifteen cm ^-3 Is 2 μm in the horizontal direction. The length in the vertical direction of the parallel pn junction layer 2 in the p-type semiconductor region 210 is about 40 μm.
[0032]
FIG. 9 shows that the impurity concentration of the central portion 221 and the side portion 222 of the n-type semiconductor region 220 is 3.31 × 10 ^Fifteen cm ^-3 And 3.01 × 10 ^Fifteen cm ^-3 FIG. 4 is a diagram showing a current-voltage waveform in a large current region when the concentration of a central portion 211 of a p-type semiconductor region 210 is changed. As is apparent from FIG. 9, when the total impurity amount of the p-type semiconductor region 210 is equal to or less than the total impurity amount of the n-type semiconductor region 220, the operating resistance is negative as indicated by a solid line or a broken line. . In this case, avalanche destruction is caused.
[0033]
On the other hand, when the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220, the operating resistance is positive as shown by the dotted line, the one-dot chain line or the two-dot chain line in FIG. It has become. Since avalanche occurs in the entire high impurity concentration regions of the p-type semiconductor region 210 and the n-type semiconductor region 220, concentration of avalanche current does not occur, so that avalanche withstand capability is improved. Therefore, it is desirable that the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220 so that the operating resistance becomes positive.
[0034]
FIG. 10 shows that the impurity concentration of the central part 221 and the side part 222 of the n-type semiconductor region 220 is 3.61 × 10 ^Fifteen cm ^-3 And 3.01 × 10 ^Fifteen cm ^-3 FIG. 4 is a diagram showing a current-voltage waveform in a large current region when the concentration of a central portion 211 of a p-type semiconductor region 210 is changed. A similar tendency is recognized from FIG.
[0035]
That is, as shown by a solid line, a broken line, or a dotted line in FIG. 10, when the total impurity amount of the p-type semiconductor region 210 is equal to or less than the total impurity amount of the n-type semiconductor region 220, the operating resistance is negative. On the other hand, as indicated by a one-dot chain line or a two-dot chain line in FIG. 10, when the total impurity amount of the p-type semiconductor region 210 is larger, the operating resistance is positive. Therefore, in the n-type semiconductor region 220, even when the impurity concentration of the central portion 221 is high, the negative resistance is improved if the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220. It can be seen that the avalanche resistance is improved.
[0036]
FIG. 11 is a longitudinal sectional view showing a configuration of a modification of the super junction semiconductor element having the configuration shown in FIG. In the super junction semiconductor device shown in FIG. 11, the end 213 of the p-type semiconductor region 210 on the back surface of the substrate, that is, n ⁺⁺ The impurity concentration of the portion in contact with the drain layer 1 is substantially the same as the impurity concentration of the side portion 212 of the p-type semiconductor region 210. Further, the impurity concentration of the end portion 223 of the n-type semiconductor region 220 on the substrate surface side is substantially the same as the impurity concentration of the side portion 222 of the n-type semiconductor region 220.
[0037]
Further, n of the p-type semiconductor region 210 ⁺⁺ In the portion (end 213) in contact with the drain layer 1, the depth of the portion having the same impurity concentration as the side portion 212 of the p-type semiconductor region 210 is the same as the lateral width of the side portion 212, for example, 2 μm. It is. The same applies to the n-type semiconductor region 220. At the end 223 on the substrate surface side, the depth of the portion having the same impurity concentration as the side 222 of the n-type semiconductor region 220 is the same as that of the side 222 in the lateral direction. It is the same as the width, for example, 2 μm. Therefore, the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220.
[0038]
FIG. 12 is a longitudinal sectional view showing a configuration of a modification of the super junction semiconductor element having the configuration shown in FIG. In the superjunction semiconductor device shown in FIG. 12, the vertical length of central portion 211 of p-type semiconductor region 210 is longer than the vertical length of central portion 221 of n-type semiconductor region 220. For example, the vertical length of central portion 211 of p-type semiconductor region 210 is 30 μm, and the vertical length of central portion 221 of n-type semiconductor region 220 is 20 μm. Also in this example, the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220.
[0039]
FIG. 13 is a longitudinal sectional view showing a configuration of a modification of the super junction semiconductor element having the configuration shown in FIG. The superjunction semiconductor device shown in FIG. 13 has the same dimensions as the example shown in FIG. 12, but as shown in FIG. 14 showing the impurity concentration distribution along EE ′ in FIG. The impurity concentration of the central part 211 and the impurity concentration of the central part 221 of the n-type semiconductor region 220 are the same. Also in this example, the total impurity amount of the p-type semiconductor region 210 is larger than the total impurity amount of the n-type semiconductor region 220.
[0040]
According to the second embodiment described above, when avalanche occurs in parallel pn junction layer 2, holes flow through central portion 211 of p-type semiconductor region 210 to source electrode 10 due to the potential distribution of parallel pn junction layer 2. The electrons flow through the central portion 221 of the n-type semiconductor region 220 and escape to the drain electrode 11. However, since the impurity concentrations of the central portions 211 and 221 are high, the charge balance when holes and electrons flow is increased. Secured. Therefore, the negative resistance is improved, and the avalanche resistance is improved.
[0041]
In the second embodiment, as in the example shown in FIG. 11, the depth of the low impurity concentration end portion of the p-type semiconductor region 210 on the back surface side of the substrate is equal to the low impurity concentration side portion of the p-type semiconductor region 210. If the depth of the low impurity concentration end portion of the n-type semiconductor region 220 on the substrate surface side is the same as the width of the low impurity concentration side portion 222 of the n-type semiconductor region 220, Thus, the effect that the reduction in the breakdown voltage is reduced is obtained.
[0042]
Next, the manufacturing processes of the various super-junction semiconductor devices described above will be described in the following third to eighth embodiments.
[0043]
Embodiment 3 FIG.
15 to 17 are views showing a manufacturing process of the super junction semiconductor device having the configuration shown in FIG. First, an n-type epitaxial growth layer 32 is grown on the n-type low-resistance layer 31 having a high impurity concentration to a thickness of, for example, about 45 μm. At this time, for example, the impurity concentration of the n-type low resistance layer 31 is about 2 × 10 ¹⁸ cm ^-3 And the impurity concentration of the n-type epitaxial growth layer 32 is 3.01 × 10 ^Fifteen cm ^-3 It is.
[0044]
Next, an oxidation process is performed to grow an oxide film 33 having a thickness of, for example, about 3 μm on the surface of the n-type epitaxial growth layer 32. Then, a part of the oxide film 33 is removed by photolithography to form a mask oxide film having an opening 34 having a width of about 7 μm (FIG. 15A). Next, an etching process is performed using the mask oxide film to form, for example, a trench 35 having a depth of about 47 μm (FIG. 15B).
[0045]
Next, a first p-type epitaxial growth layer 36 made of boron-doped silicon is grown along the side walls and the bottom of the trench 35 to a thickness of, for example, about 2 μm (FIG. 15C). It is desirable that the impurity concentration of the first p-type epitaxial growth layer 36 is substantially the same as that of the n-type epitaxial growth layer 32. Therefore, the impurity concentration of first p-type epitaxial growth layer 36 is, for example, about 3.01 × 10 ^Fifteen cm ^-3 It is.
[0046]
Subsequently, the amount of boron is increased inside the first p-type epitaxial growth layer 36 to grow the second p-type epitaxial growth layer 37 to a thickness of, for example, about 1.5 μm. When filling the trench 35 with silicon, the silicon grows from the side wall of the trench 35. Therefore, by embedding the second p-type epitaxial growth layer 37 in the trench 35 with a thickness of 1.5 μm, a high impurity concentration region (the second region) having a width of 3 μm is formed at the center of the p-type semiconductor region in the trench 35. Is formed (FIG. 16A). The impurity concentration of second p-type epitaxial growth layer 37 is, for example, about 3.31 × 10 ^Fifteen cm ^-3 It is.
[0047]
Thereafter, the oxide film 33 on the surface is removed (FIG. 16B), and the exposed surface is polished by chemical mechanical polishing (hereinafter referred to as CMP) to a thickness of, for example, about 5 μm (FIG. 16B). 16 (c)). In FIG. 16C, a portion 38 indicated by a two-dot chain line is a portion that has been removed by CMP.
[0048]
Next, cleaning and the like are performed, for example, heat treatment is performed at 1150 ° C. for 120 minutes. During this heat treatment, the portions of the first p-type epitaxial growth layer 36 and the second p-type epitaxial growth layer 37 on the low resistance layer 31 side of about 2 μm are diffused from the high concentration low resistance layer 31. At a depth of (FIG. 17). In FIG. 17, this lost portion is indicated by reference numeral 39. Thereafter, a structure of the MOSFET is formed on the surface on the side polished by the CMP, and a super-junction semiconductor device having the configuration shown in FIG. 1 is obtained.
[0049]
Here, the low resistance layer 31 is n ⁺⁺ It becomes the drain layer 1. Further, the n-type epitaxial growth layer 32 becomes the n-type semiconductor region 220 of the parallel pn junction layer 2. Further, the first p-type epitaxial growth layer 36 and the second p-type epitaxial growth layer 37 are respectively formed on the side portion 212 and the relatively low impurity concentration side portion 212 of the p-type semiconductor region 210 of the parallel pn junction layer 2. The central portion 211 has a high impurity concentration.
[0050]
According to the above-described process, the parallel pn junction layer 2 finally has a depth of about 40 μm due to the polishing amount (about 5 μm) by the above-described CMP and the disappearance amount (about 2 μm) by diffusion from the low-resistance layer 31. . In the step shown in FIG. 15B, the depth of the trench 35 is determined in consideration of the amount of disappearance due to CMP and diffusion. That is, to obtain the parallel pn junction layer 2 having a depth of about 40 μm, the depth of the trench 35 is set to 47 μm as described above in order to expect a loss of about 7 μm.
[0051]
In the above-described process, the heat treatment is performed at 1150 ° C. for 120 minutes in the process illustrated in FIG. 17, but when the diffusion from the low-resistance layer 31 is sufficient due to the heat history at the time of forming the surface MOSFET structure. Then, the heat treatment temperature and time may be appropriately adjusted in consideration of the heat history of the surface MOSFET manufacturing process.
[0052]
Embodiment 4 FIG.
18 to 20 are views showing a manufacturing process of the super junction semiconductor device having the configuration shown in FIG. The same components as those in the third embodiment are denoted by the same reference numerals. Unless otherwise specified, dimensions and impurity concentrations of respective components such as a semiconductor, and a depth and an opening width of a trench are the same as those in the third embodiment.
[0053]
First, an n-type epitaxial growth layer 32 is grown on the n-type low resistance layer 31. Next, an oxide film 33 is grown on the surface of the n-type epitaxial growth layer 32, and an opening 34 is formed by photolithography (FIG. 18A). Next, a trench 35 having a depth of, for example, about 45 μm is formed by etching (FIG. 18B).
[0054]
Next, a first p-type epitaxial growth layer 36 made of boron-doped silicon is grown along the side walls and the bottom of the trench 35 (FIG. 18C). Subsequently, a second p-type epitaxial growth layer 37 having a large boron doping amount is grown inside the first p-type epitaxial growth layer 36 to fill the trench 35 (FIG. 19A). Thereafter, the oxide film 33 is removed (FIG. 19B), and the exposed surface is polished by CMP to a thickness of, for example, about 5 μm (FIG. 19C), as shown in FIG.
[0055]
Next, cleaning and the like are performed, for example, heat treatment is performed at 1150 ° C. for 120 minutes. In the fourth embodiment, trench 35 is shallower by 2 μm than in the third embodiment. For this reason, the region that becomes the p-type semiconductor region 210 of the parallel pn junction layer 2 is only slightly shortened by the diffusion from the low resistance layer 31 that occurs during this heat treatment. That is, the region serving as the p-type semiconductor region 210 is hardly shortened. Thereafter, a MOSFET structure is formed on the surface on the side polished by CMP, and a super-junction semiconductor device having the configuration shown in FIG. 4 is obtained.
[0056]
Embodiment 5 FIG.
21 to 23 are views showing a manufacturing process of the super junction semiconductor device having the configuration shown in FIG. The same components as those in the third embodiment are denoted by the same reference numerals. Unless otherwise specified, dimensions and impurity concentrations of respective components such as a semiconductor, and a depth and an opening width of a trench are the same as those in the third embodiment.
[0057]
First, an n-type epitaxial growth layer 32 is grown on the n-type low resistance layer 31. Next, an oxide film 33 is grown on the surface of the n-type epitaxial growth layer 32, and an opening 34 is formed by photolithography (FIG. 21A). In the fifth embodiment, the opening width of opening 34 is, for example, 8.5 μm. Then, a trench 35 having a depth of, for example, about 45 μm and a trench side wall making an angle of, for example, about 87 ° with the surface of the n-type epitaxial growth layer 32 is formed by etching (FIG. 21B).
[0058]
Here, the opening width of the opening 34 of the oxide film 33 is wider than that in the third embodiment because the side wall of the trench 35 is inclined so that the width of the bottom of the trench is smaller than the opening end of the trench 35. This is because the width becomes smaller than the width. Although not particularly limited, in the fifth embodiment, the width of the trench bottom is 5.5 μm. Also, in the fifth embodiment, the trench having an opening width of 7 μm is arranged at a distance between trenches of 7 μm. However, in the fifth embodiment, the trench opening width is set to 8.5 μm. The distance between them is 5.5 μm.
[0059]
Therefore, the width of the p-type epitaxial growth layer 36 buried in the trench 35 at the bottom of the trench is equal to the width of the n-type epitaxial growth layer 32 on the surface of the n-type epitaxial growth layer 32. In other words, the shape of the trench 35 and the region other than the trench 35 are the same, and the charge balance can be ensured by forming the p-type epitaxial growth layer 36 at the same concentration as the region other than the trench 35. In the fifth embodiment, since the second p-type epitaxial growth layer 37 having a high impurity concentration is grown in a later step, such dimensions are set.
[0060]
Next, the inside of the trench 35 is filled with a p-type epitaxial growth layer. At this time, since the side wall of the trench 35 is inclined, the epitaxial growth layer is filled from the bottom of the trench. Therefore, the first p-type epitaxial growth layer 36 having a low impurity concentration is grown to an appropriate thickness, for example, a thickness of about 3.8 μm (FIGS. 21C and 22A). Thereafter, the supply amount of the gas serving as the dopant is increased, and the second p-type epitaxial growth layer 37 having a high impurity concentration is grown to a thickness of, for example, about 1 μm to fill the trench 35 (FIG. 22B). At this time, the depth of the second p-type epitaxial growth layer 37 is about 25 μm. By doing so, the p-type semiconductor region 210 having a desired profile of the parallel pn junction layer 2 can be formed.
[0061]
Thereafter, the oxide film 33 is removed (FIG. 22C), and the exposed surface is polished by CMP (FIG. 23A). Then, cleaning and the like are performed (FIG. 23B), and a MOSFET structure is formed on the surface polished by the CMP, thereby obtaining a super junction semiconductor device having a configuration shown in FIG. After the cleaning, heat treatment may be performed, and then the surface MOSFET structure may be manufactured.
[0062]
Embodiment 6 FIG.
24 to 26 are views showing another manufacturing process of the super junction semiconductor device having the configuration shown in FIG. The same components as those in the third embodiment are denoted by the same reference numerals. Unless otherwise specified, dimensions and impurity concentrations of respective components such as a semiconductor, and a depth and an opening width of a trench are the same as those in the third embodiment.
[0063]
First, an n-type epitaxial growth layer 32 is grown on the n-type low resistance layer 31. Next, an oxide film 33 is grown on the surface of the n-type epitaxial growth layer 32, and an opening 34 is formed by photolithography (FIG. 24A). Next, a trench 35 is formed by etching to reach the n-type low resistance layer 31 (FIG. 24B). Note that the trench 35 does not have to reach the n-type low-resistance layer 31.
[0064]
Next, a first p-type epitaxial growth layer 36 made of boron-doped silicon is grown in the trench 35, and the trench 35 is filled with the first p-type epitaxial growth layer 36. (FIG. 24 (c)). Next, the oxide film 33 is removed, an oxidation process is performed again, and an oxide film 43 is newly grown on the exposed surface to a thickness of, for example, about 1.5 μm. Then, an opening 44 having a width of about 3 μm is formed in the central portion of the oxide film 43 on the first p-type epitaxial growth layer 36 by photolithography (FIG. 25A).
[0065]
Next, a second trench 45 having a depth of, for example, about 25 μm is formed in the center of the first p-type epitaxial growth layer 36 by etching (FIG. 25B). Then, a second p-type epitaxial growth layer 37 made of boron-doped silicon is grown in the second trench 45, and the second trench 45 is filled with the second p-type epitaxial growth layer 37 (FIG. 25C). ).
[0066]
In the sixth embodiment, the impurity concentration of second p-type epitaxial growth layer 37 is, for example, about 3.61 × 10 ^Fifteen cm ^-3 It is. This is higher than the impurity concentration of the second p-type epitaxial growth layer 37 in the third to fifth embodiments. However, in the sixth embodiment, since the second p-type epitaxial growth layer 37 is formed shallow, the total impurity amount of the first and second p-type epitaxial growth layers 36 and 37 is large even if the impurity concentration is high. It does not increase. Therefore, the withstand voltage does not significantly decrease.
[0067]
Thereafter, the oxide film 43 is removed (FIG. 26A), and the exposed surface is polished by CMP. Next, cleaning and the like are performed, and a heat treatment is performed (FIG. 26B). In addition, you may make it utilize the heat history at the time of forming a surface MOSFET structure as heat processing. Then, a MOSFET structure is formed on the surface on the side polished by the CMP, and a super-junction semiconductor device having the configuration shown in FIG. 6 is obtained.
[0068]
Embodiment 7 FIG.
27 to 29 are views showing a manufacturing process of the super junction semiconductor device having the configuration shown in FIG. The same components as those in the third embodiment are denoted by the same reference numerals. Unless otherwise specified, dimensions and impurity concentrations of respective components such as a semiconductor, and a depth and an opening width of a trench are the same as those in the third embodiment.
[0069]
First, a first n-type epitaxial growth layer 32 is grown on the n-type low resistance layer 31. Next, an oxide film 53 is grown on the surface of the first n-type epitaxial growth layer 32, and an opening 54 having a width of, for example, about 3 μm is formed by photolithography (FIG. 27A). Next, a trench 55 having a depth of, for example, about 45 μm is formed by etching (FIG. 27B). Here, the trench 55 reaches the n-type low-resistance layer 31, but does not have to reach the n-type low-resistance layer 31.
[0070]
Then, the impurity concentration is set to, for example, about 3.31 × 10 ^Fifteen cm ^-3 Is filled with the second n-type epitaxial growth layer 67 (FIG. 27C). The second n-type epitaxial growth layer 67 becomes a central portion 221 of the n-type semiconductor region 220 of the parallel pn junction layer 2 where the impurity concentration is relatively high. The first n-type epitaxial growth layer 32 is a side 222 of the n-type semiconductor region 220 of the parallel pn junction layer 2 having a relatively low impurity concentration.
[0071]
Next, the oxide film 53 is removed, an oxidation process is performed again, and a new oxide film 33 is grown on the exposed surface. Then, an opening 34 having a width of about 7 μm is formed in the central portion of the oxide film 33 on the first n-type epitaxial growth layer 32 by photolithography (FIG. 28A). Next, a second trench having a depth of, for example, about 45 μm is formed in the center of the first n-type epitaxial growth layer 32 by etching.
[0072]
Next, the inside of the second trench is filled with a first p-type epitaxial growth layer 36 by epitaxial growth. After removing the oxide film 33, an oxidation process is performed again to newly grow an oxide film 43 having a thickness of, for example, 3 μm on the exposed surface. Then, an opening 44 having a width of about 3 μm is formed in the central portion of the oxide film 43 on the first p-type epitaxial growth layer 36 by a photolithography technique.
[0073]
Next, a third trench 45 having a depth of, for example, about 45 μm is formed in the center of the first p-type epitaxial growth layer 36 by etching (FIG. 28B). In the third trench 45, the impurity concentration is, for example, 3.61 × 10 ^Fifteen cm ^-3 The second p-type epitaxial growth layer 37 is grown to a degree, and the third trench 45 is filled with the second p-type epitaxial growth layer 37 (FIG. 28C).
[0074]
Thereafter, the oxide film 43 is removed (FIG. 29A), and the exposed surface is polished by CMP. Next, cleaning and the like are performed, and diffusion by heat treatment is performed (FIG. 29B). Then, the structure of the MOSFET is formed on the surface on the side polished by the CMP, and the super junction semiconductor element having the configuration shown in FIG. 7 is obtained. Note that the step of forming the third trench 45 is omitted, and the concentration of the dopant gas is changed after the growth of the first p-type epitaxial growth layer 36 as in the third embodiment, so that the second p-type epitaxial growth layer 36 is continuously formed. The type epitaxial growth layer 37 may be grown. Further, after forming the first p-type epitaxial growth layer 36 and the second p-type epitaxial growth layer 37, the second n-type epitaxial growth layer 67 may be formed.
[0075]
Embodiment 8 FIG.
30 to 32 are views showing a manufacturing process of the super junction semiconductor device having the configuration shown in FIG. The same components as those in the third embodiment are denoted by the same reference numerals. Unless otherwise specified, dimensions and impurity concentrations of respective components such as a semiconductor, and a depth and an opening width of a trench are the same as those in the third embodiment.
[0076]
First, a first n-type epitaxial growth layer 32 is grown on the n-type low resistance layer 31. Next, an oxide film 53 is grown on the surface of the first n-type epitaxial growth layer 32, and an opening 54 having a width of, for example, about 3 μm is formed by photolithography. Next, a trench 55 having a depth of, for example, about 45 μm is formed by etching (FIG. 30A). Note that the trench 55 does not have to reach the n-type low-resistance layer 31.
[0077]
Then, the impurity concentration is set to, for example, about 3.31 × 10 ^Fifteen cm ^-3 Is filled with the second n-type epitaxial growth layer 67. As in the seventh embodiment, the first n-type epitaxial growth layer 32 and the second n-type epitaxial growth layer 67 are each on the side of the n-type semiconductor region 220 of the parallel pn junction layer 2 having a relatively low impurity concentration. The portion 222 and the central portion 221 having a relatively high impurity concentration are formed.
[0078]
Next, the oxide film 53 is removed, an oxidation process is performed again, and an oxide film 63 having a thickness of about 1.5 μm is newly grown on the exposed surface. Then, an opening 64 having a width of about 7 μm is formed by a photolithography technique, leaving a central portion of the oxide film 63 on the first n-type epitaxial growth layer 32. Then, a second trench 65 having a depth of, for example, about 25 μm is formed in the portion of the second n-type epitaxial growth layer 67 and the first n-type epitaxial growth layer 32 on both sides thereof by etching (FIG. 30 ( b)).
[0079]
Next, the inside of the second trench 65 is filled with a third n-type epitaxial growth layer 32 'by epitaxial growth (FIG. 30 (c)). The impurity concentration of the third n-type epitaxial growth layer 32 ′ is desirably about the same as that of the first n-type epitaxial growth layer 32. Then, in the n-type semiconductor region 220 of the parallel pn junction layer 2, a region having a high impurity concentration can be provided on the n-type low-resistance layer 31 side in the center. Therefore, the impurity concentration of third n-type epitaxial growth layer 32 ′ is, for example, about 3.01 × 10 ^Fifteen cm ^-3 It is.
[0080]
Next, the oxide film 63 is removed, and an oxidation process is performed again to newly grow an oxide film 33 having a thickness of about 3 μm on the exposed surface. Then, an opening 34 having a width of about 7 μm is formed in the central portion of the oxide film 33 on the first n-type epitaxial growth layer 32 by photolithography. Next, a third trench 35 is formed in the center of the first n-type epitaxial growth layer 32 by etching to reach the n-type low resistance layer 31 (the third trench 35 does not have to reach) (FIG. 31A). )).
[0081]
Next, the inside of the third trench 35 is filled with a first p-type epitaxial growth layer 36 by epitaxial growth. The oxide film 33 is removed, and a new oxide film 43 having an opening 44 having a width of about 3 μm is newly grown at the center on the first p-type epitaxial growth layer 36. Next, a second trench 45 having a depth of, for example, about 25 μm is formed in the center of the first p-type epitaxial growth layer 36 by etching (FIG. 31B). Then, the impurity concentration in the second trench 45 is, for example, about 3.61 × 10 ^Fifteen cm ^-3 (FIG. 31 (c)).
[0082]
Thereafter, the oxide film 43 is removed (FIG. 32A), and the exposed surface is polished by CMP. Next, cleaning and the like are performed, and heat treatment is performed (FIG. 32B). In addition, you may make it utilize the heat history at the time of forming a surface MOSFET structure as heat processing. Then, the structure of the MOSFET is formed on the surface on the side polished by the CMP, and the super junction semiconductor element having the configuration shown in FIG. 12 is obtained.
[0083]
After forming the first p-type epitaxial growth layer 36 and the second p-type epitaxial growth layer 37, the second n-type epitaxial growth layer 67 and the third n-type epitaxial growth layer 32 'may be formed. . Further, if the impurity concentration of the second p-type epitaxial growth layer 37 is made the same as that of the second n-type epitaxial growth layer 67, a super junction semiconductor device having the configuration shown in FIG. 13 can be obtained.
[0084]
Since the present invention relates to the super-junction structure constituting the breakdown voltage region, the structure of the source and the drain and the manufacturing process thereof are arbitrary. Therefore, the present invention is not limited to MOSFETs, but also applies to IGBTs, bipolar transistors, GTO thyristors, diodes, and the like. Further, the dimensions and impurity concentration values of the respective semiconductor regions described above are merely examples, and the present invention is not limited to these.
[0085]
【The invention's effect】
According to the present invention, when an avalanche occurs in the parallel pn junction layer, the impurity concentration in the central portion through which holes and electrons flow in the p-type semiconductor region and the n-type semiconductor region is high. Since the impurity concentration in the central portion of the semiconductor device is high, a charge balance at the time of occurrence of avalanche is ensured. Therefore, the negative resistance is improved, and the avalanche resistance is improved.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view showing a configuration of a super junction semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an impurity concentration distribution along AA ′ in FIG. 1;
3 is a diagram showing a current-voltage waveform in a large current region when the concentration at the center of a p-type semiconductor region is changed in the superjunction semiconductor device having the configuration shown in FIG.
FIG. 4 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. 1;
FIG. 5 is a diagram showing an impurity concentration distribution in BB ′ and CC ′ in FIG. 4;
FIG. 6 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. 4;
FIG. 7 is a longitudinal sectional view illustrating a configuration of a super junction semiconductor device according to a second embodiment of the present invention;
FIG. 8 is a diagram showing an impurity concentration distribution along DD ′ in FIG. 7;
9 is a diagram showing a current-voltage waveform in a large current region when the concentration at the center of a p-type semiconductor region is changed in the superjunction semiconductor device having the configuration shown in FIG. 7;
10 is a diagram showing a current-voltage waveform in a large current region when the concentration at the center of a p-type semiconductor region is changed in the superjunction semiconductor device having the configuration shown in FIG. 7;
11 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. 7;
12 is a longitudinal sectional view showing a configuration of a modified example of the super junction semiconductor element having the configuration shown in FIG. 11;
13 is a longitudinal sectional view showing a configuration of a modification of the super junction semiconductor element having the configuration shown in FIG. 11;
FIG. 14 is a diagram showing an impurity concentration distribution along EE ′ in FIG. 13;
FIG. 15 is a diagram illustrating a part of the manufacturing process of the super-junction semiconductor device having the configuration illustrated in FIG. 1;
16 is a view illustrating a continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 1;
17 is a view illustrating a continuation of the manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 1;
18 is a view illustrating a part of the manufacturing process of the super-junction semiconductor device having the configuration illustrated in FIG. 4;
19 is a view illustrating a continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 4;
20 is a view illustrating a continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 4;
21 is a view illustrating a part of the manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
FIG. 22 is a view illustrating a continuation of the manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
FIG. 23 is a view illustrating a continuation of the manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
24 is a view illustrating a part of another manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
FIG. 25 is a view illustrating a continuation of another manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
26 is a view illustrating a continuation of another manufacturing process of the super junction semiconductor element having the configuration illustrated in FIG. 6;
FIG. 27 is a diagram illustrating a part of the manufacturing process of the super-junction semiconductor device having the configuration illustrated in FIG. 7;
28 is a view illustrating the continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 7;
29 is a view illustrating the continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 7;
30 is a view illustrating a part of the manufacturing process of the super-junction semiconductor element having the configuration illustrated in FIG. 12;
FIG. 31 is a view illustrating the continuation of the manufacturing process for the super junction semiconductor element having the configuration illustrated in FIG. 12;
32 is a view illustrating the continuation of the manufacturing process for the super-junction semiconductor element having the configuration illustrated in FIG. 12;
[Explanation of symbols]
1 Low resistance layer (n ⁺⁺ Drain layer)
2 Parallel pn junction layer
210 First conductivity type semiconductor region (p-type semiconductor region)
211 Central part of first conductivity type semiconductor region
212 Side portion of first conductivity type semiconductor region
213 End of first conductivity type semiconductor region
220 Second conductivity type semiconductor region (n-type semiconductor region)
221 Central part of semiconductor region of second conductivity type
222 Side portion of second conductivity type semiconductor region
223 End of second conductivity type semiconductor region

Claims (15)

A low-resistance layer between the first main surface and the second main surface of the semiconductor substrate, extending in the vertical direction from the first main surface side to the second main surface side, and in the horizontal direction; And a parallel pn junction layer comprising a first conductivity type semiconductor region and a second conductivity type semiconductor region alternately and repeatedly joined, and a current flows in an on state and is depleted in an off state. In the element
Concerning the impurity concentration in the lateral direction in the first conductivity type semiconductor region, the concentration at the center portion is relatively high, and the concentration at the side portion close to the junction surface with the second conductivity type semiconductor region is relatively low. A semiconductor element characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a lateral impurity concentration in the second conductivity type semiconductor region is substantially uniform. The horizontal width of the central portion of the first conductive type semiconductor region in the horizontal direction is not more than half of the horizontal width of the first conductive type semiconductor region. Semiconductor element. Concerning the impurity concentration in the vertical direction in the first conductivity type semiconductor region, the concentration at the end on the second main surface side is the same as that of the side portion of the first conductivity type semiconductor region, where the impurity concentration is relatively low. 4. The semiconductor device according to claim 1, wherein the concentration is substantially the same. The vertical thickness of the end of the first conductive type semiconductor region on the second main surface side where the impurity concentration is relatively low is such that the impurity concentration of the first conductive type semiconductor region is relatively low. 5. The semiconductor device according to claim 4, wherein the width of the region is substantially the same as the width of the region. Concerning the impurity concentration in the lateral direction in the second conductivity type semiconductor region, the concentration at the center portion is relatively high, and the concentration at the side portion near the junction surface with the first conductivity type semiconductor region is relatively low. The semiconductor device according to claim 1, wherein: 7. The semiconductor device according to claim 6, wherein a lateral width of the central portion of the second conductivity type semiconductor region is equal to or less than a half of a lateral width of the second conductivity type semiconductor region. . Concerning the impurity concentration in the vertical direction in the second conductivity type semiconductor region, the concentration at the end on the first main surface side is the same as that of the side portion of the second conductivity type semiconductor region, where the impurity concentration is relatively low. 8. The semiconductor device according to claim 6, wherein the concentration is substantially the same. The vertical thickness of the end of the second conductive type semiconductor region on the first principal surface side where the impurity concentration is relatively low is such that the impurity concentration of the second conductive type semiconductor region is relatively low. 9. The semiconductor device according to claim 8, wherein the width of the region is substantially the same as the width of the region. Concerning the impurity concentration in the vertical direction in the first conductivity type semiconductor region, the concentration at the end on the second main surface side is the same as that of the side portion of the first conductivity type semiconductor region, where the impurity concentration is relatively low. 10. The semiconductor device according to claim 6, wherein the concentration is substantially the same. The vertical thickness of the end of the first conductive type semiconductor region on the second main surface side where the impurity concentration is relatively low is such that the impurity concentration of the first conductive type semiconductor region is relatively low. The semiconductor device according to claim 10, wherein the width of the region is substantially the same as the width of the region. The vertical thickness of the end of the first conductive type semiconductor region on the second main surface side where the impurity concentration is relatively low is such that the impurity concentration of the second conductive type semiconductor region is relatively low. 12. The semiconductor device according to claim 11, wherein the thickness of the first main surface side end portion is smaller than a vertical thickness. 13. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor region and the second conductivity type semiconductor region are arranged in a stripe shape. 14. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor region is formed of a p-type semiconductor, and the second conductivity type semiconductor region is formed of an n-type semiconductor. The impurity concentration of the central portion of the first conductivity type semiconductor region having a relatively high impurity concentration is higher than the impurity concentration of the central portion in the lateral direction of the second conductivity type semiconductor region. 15. The semiconductor device according to 14.

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