CN104659086A

CN104659086A - Power semiconductor device and manufacturing method thereof

Info

Publication number: CN104659086A
Application number: CN201310594909.XA
Authority: CN
Inventors: 肖胜安; 雷海波
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-11-21
Filing date: 2013-11-21
Publication date: 2015-05-27
Anticipated expiration: 2033-11-21
Also published as: CN104659086B

Abstract

The invention discloses a power semiconductor device. A drift region is formed by combining a superjunction drift region and a single drift region, so that the device can achieve parallel connection of a superjunction device and a single drift region device; the superjunction drift region consists of a plurality of alternately arranged N-type thin layers and P-type thin layers; and the single drift region consists of an N-type doped first N-type layer. The superjunction drift region can optimize specific on resistance of the device, so that low specific on resistance can be obtained; and the reverse recovery characteristic of the device in a shutoff process can be softened, the reverse recovery characteristic and the impact resistance of the device are improved, and recovery current impact is reduced by utilizing the characteristic of reverse recovery characteristic softening of the single drift region in the shutoff process of the device. The invention further discloses a manufacturing method of the power semiconductor device.

Description

Power semiconductor and manufacture method thereof

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of power semiconductor; The invention still further relates to a kind of manufacture method of power semiconductor.

Background technology

Super junction MOSFET adopts new structure of voltage-sustaining layer, the a series of P type semiconductor thin layer that is alternately arranged and N type semiconductor thin layer is utilized to come just described P type semiconductor thin layer and N type semiconductor thin layer to be exhausted at the lower voltage in the off state, realize electric charge mutually to compensate, thus make P type semiconductor thin layer and N type semiconductor thin layer can realize high puncture voltage under high-dopant concentration, thus obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions power MOSFET theoretical limit.In US Patent No. 5216275, the above P type semiconductor thin layer be alternately arranged is connected with N+ substrate with N type semiconductor thin layer; In US Patent No. 6630698B1, middle P type semiconductor thin layer and N type semiconductor thin layer and N+ substrate can have the interval being greater than 0.

In prior art, the formation one of P type semiconductor thin layer and N type semiconductor thin layer then carries out photoetching and injection by epitaxial growth, repeatedly this process obtains P type semiconductor thin layer and the N type semiconductor thin layer of the thickness needed repeatedly, this technique is in the MOSFET of more than 600V, generally need repetition more than 5 times, production cost and the production cycle long.Another kind be by a kind of type of a secondary growth need the extension of thickness after, carry out the etching of groove, insert the silicon of opposite types afterwards in the trench; Although this method difficulty is large, there is simplification of flowsheet, improve the effect of stability; After adopting groove structure, namely in the P type semiconductor thin layer be alternately arranged due to P/N thin layer and N type semiconductor thin layer, P type semiconductor thin layer and the doping content of N type semiconductor thin layer on longitudinal direction are easy to control, and in the thin layer not having repeatedly epitaxy technique to cause, P type semiconductor thin layer and N type semiconductor thin layer or the doping content of one of them change in the vertical thus bring additional longitudinal electric field, ensure that the leakage current characteristic that device can obtain and high puncture voltage.

In super junction technique, owing to have employed P/N thin layer alternately, in the body of power semiconductor, diode and diode such as 50 volts of Vds under lower reversed bias voltage of being formed between P type semiconductor thin layer and N type semiconductor thin layer will exhaust P type semiconductor thin layer and N type semiconductor thin layer fall completely, this makes this diode have very hard reverse recovery characteristic, this hard reverse recovery characteristic causes the restoring current of device sharply to change, in Reverse recovery, fluctuation is violent, cause the magnetotelluric noise (EMI NOISE) in circuit, impact is brought on the work of other device in circuit, in this, power semiconductor is not as conventional MOSFET element, the drift region of conventional MOSFET element does not have P/N laminate structure, but whole drift region is all N-doping, because exhausting of the MOSFET element N-drift region of routine expands along with the increase of voltage (Vds) always, reverse recovery characteristic is softer.

In process choice, repeatedly epitaxial growth and photoetching, injection technology have complexity, the manufacturing cycle is long and cost is high problem, in trench fill process, to need before trench process deposition thickness on the substrate of high-concentration dopant to reach the epitaxial loayer of some tens of pm, too increase the cost of technique.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of power semiconductor, and manufacturing cost can be made to minimize, simultaneously can also the conduction resistance of optimised devices and the softness coefficient (SOFTNESS) of the Reverse recovery of device in turn off process.For this reason, the present invention also provides a kind of manufacture method of power semiconductor.

For solving the problems of the technologies described above, power semiconductor provided by the invention is formed in N-type silicon substrate, and the zone line of described power semiconductor is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; Drift region in described current flowing district comprises super junction drift region and single drift region, and described super junction drift region is made up of multiple N-type thin layer of being alternately arranged and P type thin layer, and the first N-type layer adulterated by N-type in described single drift region forms; P trap is formed at the top of described drift region.

Described silicon substrate is formed with multiple groove, be silicon substrate thin layer between each adjacent described groove in described super junction drift region, each described N-type thin layer is by form by adulterating to the side of described silicon substrate thin layer or by described silicon substrate thin layer, each described N-type thin layer adds that the first N-type silicon epitaxy layer being formed at described silicon substrate thin layer both sides forms; Each described P type thin layer is made up of the second P-type silicon epitaxial loayer be filled in described groove.

The resistivity of described N-type thin layer is change in the horizontal and comprises the first high-resistivity portions and the first low resistivity portion, and described first low resistivity portion is the part of the side doping that the both sides of described silicon substrate thin layer were carried out or described first low resistivity portion is the described first N-type silicon epitaxy layer being formed at described silicon substrate thin layer both sides; Described first high-resistivity portions is made up of the described silicon substrate thin layer be positioned in the middle of described first low resistivity portion; Described first low resistivity portion and contiguous described P type thin layer contact; Charge balance is realized by described first low resistivity portion and its contiguous described P type thin layer.

The width of described first N-type layer is greater than the width of described N-type thin layer, and the width of described first N-type layer is by two adjacent ditch slot definitions, described first N-type layer comprises the second high-resistivity portions and the second low resistivity portion, described second high-resistivity portions is the mid portion of described first N-type layer, described second low resistivity portion is arranged in the both sides of described second high-resistivity portions and contacts with the described P type thin layer of the described groove being formed at described first N-type layer both sides, the process conditions of described second low resistivity portion are identical with described first low resistivity portion.

The charge unbalance of described first N-type layer and its contiguous described P type thin layer, under connecting the condition of reversed bias voltage between described first N-type layer and its contiguous described P type thin layer, described second low resistivity portion can by the complete having lateral depletion of described P type thin layer be close to, described second high-resistivity portions can not by the complete having lateral depletion of described P type thin layer, described second high-resistivity portions do not formed the PN junction longitudinally exhausted between the part of described P type thin layer having lateral depletion and described P trap; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap to described second high-resistivity portions exhausts increases.

Further improvement is, described power semiconductor is MOSFET element, is formed with the N-type region be made up of backside particulate injection region bottom described drift region, and the bottom of described N-type region and back metal form ohmic contact.

Further improvement is, described power semiconductor is MOSFET element, be formed bottom described drift region and form N-type buffering area and N-type region by backside particulate injection region, the top of described N-type buffering area contacts with bottom described drift region, the top of described N-type region contacts with the bottom of described N-type buffering area, the bottom of described N-type region and back metal form ohmic contact; The doping content of described N-type region is greater than the doping content of described N-type buffering area.

Further improvement is, described power semiconductor is IGBT device, be formed bottom described drift region and form N-type region and p type island region by backside particulate injection region, the top of described N-type region contacts with bottom described drift region, the top of described p type island region contacts with the bottom of described N-type region, the bottom of described p type island region and back metal form ohmic contact.

Further improvement is, described power semiconductor is trench gate mosfet device, or described power semiconductor is flat-grid MOSFET component.

Further improvement is, described power semiconductor is trench gate IGBT device, or described power semiconductor is planar gate IGBT device.

Further improvement is, the thickness of described N-type region is 0.5 micron ~ 5 microns.

Further improvement is, described single drift region comprises the above first N-type layer, each described first N-type layer is distributed in the zones of different in described current flowing district, the regional location of each described first N-type layer is respectively by the described ditch slot definition of each described first N-type layer both sides, and the regional location place of each described first N-type layer is formed with the cellular construction of more than one described power semiconductor.

Further improvement is, each regional location of described first N-type layer and the region of described terminal protection structure do not adjoin.

Further improvement is, the region of the regional location of each described first N-type layer and the grid metal electrode figure of described power semiconductor does not adjoin.

For solving the problems of the technologies described above, the described power semiconductor in the manufacture method of power semiconductor provided by the invention is MOSFET element, comprises the steps:

Step one, described surface of silicon deposit first silicon dioxide layer and the second silicon nitride layer successively adulterated in N-type; Lithographic etch process is utilized to form groove figure mask to described second silicon nitride layer and described first silicon dioxide layer successively.

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple described groove; The forming region of described super junction drift region and described single drift region is defined by described groove.

Step 3, carry out front and be deposited on the bottom surface of described groove and side forms described first N-type silicon epitaxy layer; Described first low resistivity portion and described second low resistivity portion is formed respectively by described first N-type silicon epitaxy layer.

Step 4, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.

Step 5, form the grid structure of described MOSFET element, described grid structure comprises gate dielectric layer and polysilicon gate; Form described P trap; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively.

Step 6, carry out thinning from the back side to described silicon substrate.

Step 7, carry out back side N-type ion implantation form N-type region bottom described drift region.

Step 8, the ion of described N-type region to be activated.

Step 9, carry out back face metalization and form drain electrode, the bottom of described N-type region and back metal form ohmic contact.

Step one, N-type doping described silicon substrate on form described P trap.

Step 2, at described surface of silicon successively deposit first silicon dioxide layer and the second silicon nitride layer; Lithographic etch process is utilized to form groove figure mask to described second silicon nitride layer and described first silicon dioxide layer successively.

Step 3, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple described groove; The forming region of described super junction drift region and described single drift region is defined by described groove.

Step 4, carry out front and be deposited on the bottom surface of described groove and side forms described first N-type silicon epitaxy layer; Described first low resistivity portion and described second low resistivity portion is formed respectively by described first N-type silicon epitaxy layer.

Step 5, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.

Step 6, form the grid structure of described MOSFET element, described grid structure comprises gate dielectric layer and polysilicon gate; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively.

Step 7, carry out thinning from the back side to described silicon substrate.

Step 8, carry out back side N-type ion implantation form N-type region bottom described drift region.

Step 9, the ion of described N-type region to be activated.

Step 10, carry out back face metalization and form drain electrode, the bottom of described N-type region and back metal form ohmic contact.

The described silicon substrate of step 3, the bottom surface of carrying out groove described in phosphorus diffusion couple and side carries out adulterating and distinguishes described first low resistivity portion and described second low resistivity portion.

Step 4, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described groove fills up by described second P-type silicon epitaxial loayer completely; The silicon of described groove top surface and silica are all removed.

Step 6, carry out thinning from the back side to described silicon substrate.

Step 8, the ion of described N-type region to be activated.

Step one, N-type doping described silicon substrate on form described P trap.

The described silicon substrate of step 4, the bottom surface of carrying out groove described in phosphorus diffusion couple and side carries out adulterating and distinguishes described first low resistivity portion and described second low resistivity portion.

Step 5, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described groove fills up by described second P-type silicon epitaxial loayer completely; The silicon of described groove top surface and silica are all removed.

Step 7, carry out thinning from the back side to described silicon substrate.

Step 9, the ion of described N-type region to be activated.

For solving the problems of the technologies described above, the described power semiconductor in the manufacture method of power semiconductor provided by the invention is IGBT device, comprises the steps:

Step 5, form the grid structure of described IGBT device, described grid structure comprises gate dielectric layer and polysilicon gate; Form described P trap; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively.

Step 6, carry out thinning from the back side to described silicon substrate.

Step 7, carry out back side N-type ion implantation form N-type region bottom described drift region; Carry out back side P type ion implantation and form p type island region bottom described N-type region.

Step 8, the ion of described N-type region and described p type island region to be activated.

Step 9, carry out back face metalization and form drain electrode, the bottom of described p type island region and back metal form ohmic contact.

Step one, N-type doping described silicon substrate on form described P trap.

Step 6, form the grid structure of described IGBT device, described grid structure comprises gate dielectric layer and polysilicon gate; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively.

Step 7, carry out thinning from the back side to described silicon substrate.

Step 8, carry out back side N-type ion implantation form N-type region bottom described drift region; Carry out back side P type ion implantation and form p type island region bottom described N-type region.

Step 9, the ion of described N-type region and described p type island region to be activated.

Step 10, carry out back face metalization and form drain electrode, the bottom of described p type island region and back metal form ohmic contact.

Step 6, carry out thinning from the back side to described silicon substrate.

Step one, N-type doping described silicon substrate on form described P trap.

Step 7, carry out thinning from the back side to described silicon substrate.

The present invention has following beneficial effect:

1, the drift region of device of the present invention is set to by super junction drift region and single drift region fabricated structure, make device of the present invention can realize the parallel connection of super-junction device and single drift region device, utilize super junction drift region can optimised devices conduction resistance thus low conduction resistance can be obtained; Utilize the characteristic that reverse recovery characteristic is softer in device turn off process of single drift region, the reverse recovery characteristic deliquescing of device in turn off process, the reverse recovery characteristic improving device and shock-resistant ability can be made, reduce restoring current impact.So the present invention can better optimize low conduction resistance and the SOFTNESS of device in turn off process, the optimum balance of conduction resistance and resistance to rush of current can be realized.

2, the groove of the P/N thin layer of power semiconductor of the present invention is formed directly on silicon substrate, does not need on a silicon substrate to form epitaxial loayer, so the present invention can make minimizing of the manufacturing cost of device.

3, power semiconductor of the present invention is by adopting thinner silicon substrate film, forms very thin N-type region simultaneously, can reduce the conduction resistance of device and reduce device thermal resistance in the bottom of P/N thin layer, improves reliability.

4, the low resistivity portion of N-type thin layer of the present invention can adopt and carry out diffusing, doping formation in a silicon substrate, the low resistivity portion being made up of N-type thin layer N-type epitaxy layer can be substituted wholly or in part, thus further can reduce technology difficulty, reduce process costs.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is existing power semiconductor vertical view one;

Fig. 2 is existing power semiconductor vertical view two;

Fig. 3 is the vertical view in the current flowing district of the embodiment of the present invention one power semiconductor;

Fig. 4 A is the profile of the embodiment of the present invention one power semiconductor along the E1F1 line of Fig. 3;

Fig. 4 B is the profile of the embodiment of the present invention one power semiconductor along the E2F2 line of Fig. 3;

Fig. 5 A-Fig. 8 is the device profile map in each step of manufacture method of the embodiment of the present invention one power semiconductor;

Fig. 9 A is the profile of the embodiment of the present invention two power semiconductor along the E1F1 line of Fig. 3;

Fig. 9 B is the profile of the embodiment of the present invention two power semiconductor along the E2F2 line of Fig. 3;

Figure 10 is the vertical view in the current flowing district of the embodiment of the present invention three power semiconductor;

Figure 11 is the profile of the embodiment of the present invention three power semiconductor along the E2F2 line of Figure 10;

Figure 12 is the profile of the embodiment of the present invention four power semiconductor along the E2F2 line of Figure 10;

Figure 13-Figure 15 is the device profile map in each step of manufacture method of the embodiment of the present invention five power semiconductor;

Figure 16 is the genesis analysis figure of the impurity concentration of the N-type region of the embodiment of the present invention one power semiconductor;

Figure 17 be the embodiment of the present invention seven power semiconductor P/N thin layer bottom to the genesis analysis figure of impurity concentration at the silicon substrate back side;

Figure 18 is the schematic diagram of Reverse recovery curve;

Figure 19 is the Reverse recovery curve of the embodiment of the present invention one power semiconductor.

Embodiment

As shown in Figure 1, be the vertical view one of existing power semiconductor.On vertical view, the embodiment of the present invention can be divided into 1st district, 2nd district and 3rd district.1st district is the zone line of power semiconductor is current flowing district, described current flowing district comprises the territory, p type island region 25 and N-type region territory that are alternately arranged, and namely territory, described p type island region 25 is also formed at the P type thin layer in described current flowing district, namely described N-type region territory is also formed at N-type thin layer in described current flowing district; Can arrive drain electrode by source electrode through raceway groove by N-type region territory at described current flowing district electric current, and territory, described p type island region 25 bears voltage under reverse blocking state together with formation depletion region, described N-type region territory.2nd district and 3rd district are the terminal protection structure region of described power semiconductor; when break-over of device, described terminal protection structure does not provide electric current, reverse-biased for this voltage of voltage born from the surface in 1 periphery, district unit and territory, p type island region, periphery 25 to device outer-most end surface substrate be lateral voltage and from 1 periphery, district cell surface to this voltage of voltage of substrate be longitudinal voliage.Having in 2nd district at least one P type ring 24, Fig. 1 is a P type ring 24, and the general P type backgate with 1st district of this P type ring 24 and P trap link together; There is the field plate dielectric film with certain inclination angle in 2nd district, also having in 2nd district for slowing down surface field polycrystalline field plate jumpy sheet and Metal field plate, and P type post 23; In 2nd district, also described Metal field plate can not be set.3rd district bear district by P type post 23 and the voltage that the N-type post be made up of N-type silicon epitaxy layer is alternately formed, it there is deielectric-coating, namely described P type post 23 is also formed at the P type thin layer in described terminal protection structure, namely described N-type post is also formed at N-type thin layer in described terminal protection structure; There is Metal field plate in 3rd district, in 3rd district, also described Metal field plate can not be set; P type ring 24 can be had in 3rd district also can not have, have the P type ring at this place during P type ring 24 to be not connected with the P type backgate in current flowing district (suspension) that be connected; Have channel cutoff ring 21 in the outermost end in 3rd district, described channel cutoff ring 21 adds medium formed thereon again by N+ injection region or N+ injection region or medium adds that metal is formed; Additional little P type post 22 can be had at four angles place, in order to better to realize charge balance at described P type post 23.As seen from Figure 1, the cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all strip structure; Described terminal protection structure is surrounded on the periphery in described current flowing district and described P type ring 24, described P type post 23 and described channel cutoff ring 21 are all tetragonal circulus, also can have the circulus of circular arc in tetragonal corner.

As shown in Figure 2, it is the vertical view two of existing power semiconductor, structure difference is as shown in Figure 1, cellular construction in described current flowing district and territory, described p type island region 25 and N-type region territory are all tetragonal structure, namely by territory, tetragonal described p type island region 25 and N-type region territory in the two-dimensional direction proper alignment form the cell array in described current flowing district.Territory, described p type island region 25 and N-type region territory also can be hexagon, octagon and other shape, and the arrangement mode in territory, described p type island region 25 and N-type region territory also can at X, and Y-direction carries out certain dislocation; As long as ensure that whole arrangement is by certain rule, carry out repeating just passable.

The additional little P type post 22 of corner in Fig. 1 and Fig. 2, can design according to the optimized requirement of local charge balance, if the width of described P type post 23 is a, distance between described P type post 23 and described P type post 23 is also a, and so described little P type post 22 can adopt the length of side to be the square P nibs of 0.3 ~ 0.5a.

In existing MOSFET element, MOSFET element unit is all formed above the N-type thin layer in current flowing district, the N-type thin layer in current flowing district, P type thin layer and MOSFET element unit repeat completely, the device being such as 600V and BVds-600V to a puncture voltage is example: the N+ silicon substrate of device is uniform, resistivity is 0.001-0.003 ohmcm, on N+ substrate, deposition thickness is 45 microns, and resistivity is the N-type silicon epitaxial layers of the Uniform Doped of 1 ohmcm ~ 5 ohmcm or the N-type silicon epitaxial layers of longitudinally impurity concentration change; Form groove afterwards, fill P type silicon epitaxial layers in the trench, P type silicon epitaxial layers can be longitudinally Uniform Doped, also can be longitudinally change doping, the P type thin layer leaving N-type thin layer and extension filling after such etching groove just constitutes the P-N thin layer replaced of power semiconductor by P type thin layer and N-type thin layer; In current flowing district, except the region close to device terminal, may because Terminal Design and technique cause outside some differences, all device cells are consistent, and in the horizontal, the structure of P-N thin layer repeats completely.

As shown in Figure 3, be the vertical view in current flowing district of the embodiment of the present invention one power semiconductor; As shown in Figure 4 A, be the profile of the embodiment of the present invention one power semiconductor along the E1F1 line of Fig. 3; As shown in Figure 4 B, be the profile of the embodiment of the present invention one power semiconductor along the E2F2 line of Fig. 3.The embodiment of the present invention one power semiconductor is MOSFET element, is formed in N-type silicon substrate 1, and the zone line of described power semiconductor is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; Drift region in described current flowing district comprises super junction drift region and single drift region, and described super junction drift region is made up of multiple N-type thin layer of being alternately arranged and P type thin layer 4, and the first N-type layer adulterated by N-type in described single drift region forms; P trap 7 is formed at the top of described drift region.As can be seen from Figure 3, described P type thin layer 4 corresponds to the thin layer between B0B1, B2B3, B4B5, B6B7 etc., described N-type thin layer corresponds to the thin layer between B1B2, B3B4, B5B6, B7B8 etc., can find out that described P type thin layer 4 and described N-type thin layer are all strip structure and are alternately arranged.First N-type layer of described single drift region is arranged in square frame g1g2g3g4, and in the embodiment of the present invention one, described single drift region is surrounded by described super junction drift region.

Described silicon substrate 1 adopts the N-type doped substrate of higher electric resistivity.

Described silicon substrate 1 is formed with multiple groove, be silicon substrate thin layer between each adjacent described groove in described super junction drift region, by described silicon substrate thin layer, each described N-type thin layer adds that the first N-type silicon epitaxy layer being formed at described silicon substrate thin layer both sides forms; Each described P type thin layer 4 is made up of the second P-type silicon epitaxial loayer be filled in described groove.

The resistivity of described N-type thin layer is change in the horizontal and comprises the first high-resistivity portions 3 and the first low resistivity portion 3a, and described first low resistivity portion 3a is the described first N-type silicon epitaxy layer 3a being formed at described silicon substrate thin layer both sides; Described first high-resistivity portions 3 is made up of the described silicon substrate thin layer be positioned in the middle of described first low resistivity portion 3a; Described first low resistivity portion 3a and contiguous described P type thin layer 4 contact; Charge balance is realized by described first low resistivity portion 3a and its contiguous described P type thin layer.

The width of described first N-type layer is greater than the width of described N-type thin layer, and the width of described first N-type layer is by two adjacent ditch slot definitions, described first N-type layer comprises the second high-resistivity portions 3b and the second low resistivity portion 3a, described second high-resistivity portions 3b is the mid portion of described first N-type layer, described second low resistivity portion 3a is arranged in the both sides of described second high-resistivity portions 3b and contacts with the described P type thin layer 4 of the described groove being formed at described first N-type layer both sides, the process conditions of described second low resistivity portion 3a are identical with described first low resistivity portion 3a, also namely described second low resistivity portion 3a is also made up of the described first N-type silicon epitaxy layer 3a formed on the sidewalls of the trench.

The charge unbalance of described first N-type layer and its contiguous described P type thin layer 4, under connecting the condition of reversed bias voltage between described first N-type layer and its contiguous described P type thin layer 4, described second low resistivity portion 3a can by the complete having lateral depletion of described P type thin layer 4 be close to, described second high-resistivity portions 3b can not by the complete having lateral depletion of described P type thin layer 4, and described second high-resistivity portions 3b is not formed the PN junction longitudinally exhausted between the part of described P type thin layer 4 having lateral depletion and described P trap 7; When reversed bias voltage increases, the degree of depth that the longitudinal direction of described P trap 7 to described second high-resistivity portions 3b exhausts increases.Namely the described MOSFET element unit being positioned at described single drift region is all vertical DMOS field-effect transistor (VDMOS) structure; The described MOSFET element unit being positioned at described super junction drift region is all super junction MOSFET element.

Bottom described drift region, be formed with the N-type region 2 be made up of backside particulate injection region, bottom and the back metal 13 of described N-type region 2 form ohmic contact.

The embodiment of the present invention one MOSFET element is trench gate mosfet device, is all formed with a MOSFET element unit at each described N-type thin layer top of described super junction drift region; All be formed with more than one MOSFET element unit at the top of described single drift region, in Fig. 4 B, illustrate the MOSFET element unit being all formed with 2 at the top of described single drift region.Described MOSFET element cellular construction comprises:

The gate groove of P trap 7 is formed through at the top of each described N-type thin layer or described first N-type layer, be formed with gate dielectric layer 5 in the lower surface of described gate groove and side, be formed with the polysilicon gate 6 of filling described gate groove on gate dielectric layer 5 surface, described gate dielectric layer 5 is gate oxide.Described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel.The source region 8 be made up of N+ district is all formed at described P trap 7 top of the both sides of described gate groove.

Interlayer film 10 is formed in described silicon substrate 1 front; Contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Bottom the described contact hole 11 at top, described source region 8, be formed with the P trap draw-out area 9 be made up of P+ district, described P trap draw-out area 9 and described P trap 7 contact.

Be formed with front metal 12 in described silicon substrate 1 front, described front metal 12 draws source electrode and grid respectively.Be formed with back metal 13 at described silicon substrate 1 back side, described back metal 13 draws drain electrode respectively.

The further improvement of the embodiment of the present invention one has: described gash depth is 40 microns ~ 50 microns, the width of described groove is 6 microns, spacing in described super junction drift region between each adjacent described groove is 1 micron, spacing between the described groove of both sides, described single drift region is 8 microns, i.e. spacing between the g1g2 of Fig. 3, other place are all 1 micron.The thickness of described first N-type silicon epitaxy layer 3a is 1.5 microns, the thickness of described P type thin layer 4 is 3 microns, be in the described groove of 6 microns at each width, filled completely by two described first N-type silicon epitaxy layer 3a and described P type thin layer 4, described P type thin layer 4 be by two width be 1.5 microns described second P-type silicon epitaxial loayer in the trench between engage after formed.

The resistivity of described silicon substrate 1 is 20 ohmcm ~ 40 ohmcms.The resistivity of described first N-type silicon epitaxy layer 3a is 1 ohmcm, and impurity concentration is 5e15cm ^-3, described P type thin layer 4 resistivity be 2.78 ohmcms, impurity concentration is 5e15cm ^-3.

In the embodiment of the present invention one, the impurity of the described first N-type silicon epitaxy layer 3a in described super junction drift region also can diffuse in described first high-resistivity portions 3, the resistance of described first high-resistivity portions 3 can be reduced like this, thus further can lower the conduction resistance of device; The impurity spread from described first N-type silicon epitaxy layer 3a can spread all in described first high-resistivity portions 3, makes the resistivity of the whole transverse area of described first high-resistivity portions 3 all lower; Or, the impurity spread from described first N-type silicon epitaxy layer 3a does not spread all in the Zone Full of described first high-resistivity portions 3, the zone line of described first high-resistivity portions 3 also keeps higher resistivity, resistivity as higher in this be equal as described in the resistivity of silicon substrate 1, or be greater than described silicon substrate 1 resistivity 1/10th, or be greater than 10 times of resistivity of described first N-type silicon epitaxy layer 3a.When break-over of device, the current flowing district of device is provided by described N-type thin layer, when device is in cut-off state, N-type impurity in described first low resistivity portion 3a and described first high-resistivity portions 3 is all exhausted by the impurity in described P type thin layer 4, or at least, N-type impurity in described first low resistivity portion 3a is all exhausted by the impurity in described P type thin layer 4, the absolute value of the difference of the impurity sum in P type thin layer 4 described in the N-type impurity sum in 2 corresponding to each groove described first low resistivity portion 3a can not be greater than wherein any one and 10%.In the embodiment of the present invention one, when the epitaxial growth of described first N-type silicon epitaxy layer 3a, forming a thickness at channel bottom is the N-type layer of T1, part particularly below described P type thin layer 4, when device ends can not exhaust by p type impurity, the turn-off characteristic of device can be improved like this.

The direction along E2F2 in figure 3, the described single drift region of the embodiment of the present invention one is included in current flowing district, described first N-type layer of described single drift region adds the first N-type silicon epitaxy layer 3a described in both sides by the silicon between a wider N-type thin layer and g1g2 and forms, in described first N-type layer etching groove complete after the lateral dimension of silicon and the distance of lateral dimension also namely between g1g2 of described second high-resistivity portions 3b be greater than the lateral dimension of silicon that the unit around it stays after etching and described first high-resistivity portions 3 as the distance between C1D1.Described first N-type silicon epitaxy layer 3a around wherein said second high-resistivity portions 3b and the N-type impurity in described second low resistivity portion 3a can be exhausted by the impurity in horizontal P type thin layer 4, but the N-type impurity in described second high-resistivity portions 3b necessarily has part can not think that in horizontal P type thin layer 4, p type impurity exhausted, namely in described second high-resistivity portions 3b region, always have part high resistance area do not have depleted fall, this do not have depleted fall part with the cellular construction of the described MOSFET on it forms routine VDMOS.

In the embodiment of the present invention one, the part that the P type thin layer 4 be not received in second high-resistivity portions 3b described in when ending exhausts, a P-N junction is formed with the P trap 7 of device, along with the increase of device Vds, depletion region in described second high-resistivity portions 3b expands gradually, this different with the described first low resistivity portion 3a in described super junction drift region with P type thin layer 4 in low voltage as just completely exhausted under 50V, due to this characteristic in described second high-resistivity portions 3b district, improve reverse recovery characteristic and the switching characteristic of device, improve the resistance to rush of current ability (bearing higher di/dt) of device.

In the embodiment of the present invention one, described N-type region 2 is formed by the ion implantation of a high dose, and described N-type region 2 can form ohmic contact with back metal 13.The implanted dopant of described N-type region 2 is arsenic, and Implantation Energy is 5KEV ~ 100KEV, and implantation dosage is at E15CM ^-2magnitude level, carry out formation low contact resistance with the back side.The impurity of described N-type region 2 needs to activate, as laser annealing, and furnace anneal, or the combination of laser annealing and furnace anneal activates; The thickness of described N-type region 2 is 0.5 micron ~ 5 microns, this thickness is that the thickness of thinning back side by controlling described silicon substrate 1 obtains, in double arrowed line EDC in Fig. 4 A, border E, D are respectively the back side of described N-type region 2 and upper bounds, border C are in described N-type thin layer.

In the embodiment of the present invention one, also can bottom described N-type region 2 and described drift region between add a N-type buffering area, the top of described N-type buffering area contacts with bottom described drift region, the top of described N-type region contacts with the bottom of described N-type buffering area, the bottom of described N-type region 2 and back metal form ohmic contact; The doping content of described N-type region 2 is greater than the doping content of described N-type buffering area.Need employing twice injection to be formed like this, one is the high energy ion implantation forming described N-type buffering area, and Implantation Energy 1MEV ~ 5MEV, implantation dosage is at E12CM ^-2~ E13CM ^-2magnitude, implanted dopant is phosphorus, and puncture voltage and the switch performance of device can be improved in described N-type buffering area; One for forming the lower injection of the energy of described N-type region 2, implanted dopant is arsenic, and Implantation Energy is 5KEV ~ 100KEV, and implantation dosage is at E15CM ^-2magnitude level, carry out formation low contact resistance with the back side.As shown in figure 16, be the genesis analysis figure of impurity concentration of N-type region of the embodiment of the present invention one power semiconductor.

As shown in figure 18, be the schematic diagram of Reverse recovery curve; In figure, ta is the time increasing to maximum reverse current at device electric current in turn off process from 0, di/dt in this time period determines primarily of the parameter of external circuit, tb is reduced to from maximum reverse current the time that electric current is 0 in recovery process, the di/dt of this time period determines primarily of the characteristic of diode in body, softness coefficient is S=tb/ta, (or hard recovery characteristics) device of low softness coefficient can cause di/dt very high in recovery process, cause the voltage overshoot that device is high, the electromagnetic interference of component failure, system such as to exceed standard at the problem.Shown in Figure 19, it is the Reverse recovery curve of the power semiconductor of the embodiment of the present invention one, further comprises two correlation curves, wherein curve 17 is the Reverse recovery curve of the body diode of the power semiconductor of the present invention one, curve 18 is reverse recovery characteristics of the body diode of the existing super-junction device not comprising single drift region in the embodiment of the present invention, curve 19 is reverse recovery characteristics of the body diode of the MOSFET element adopting conventional single drift region structure, can find out that the softness coefficient of the Reverse recovery of the device of the embodiment of the present invention one is larger than the softness coefficient of the MOSFET element of conventional single drift region structure, the reverse recovery characteristic of the body diode of existing super-junction device is improved, but the reverse recovery characteristic of the MOSFET element lower than the conventional single drift region structure of employing.As from the foregoing, the embodiment of the present invention one is while super junction P-N thin layer is as drift region, and the single drift region of normal high resistive rate due to parallel connection, the recovery characteristics of device becomes soft, improve the ability of bearing di/dt simultaneously.

As shown in Fig. 5 A to Fig. 7, it is the device profile map in each step of manufacture method of the embodiment of the present invention one power semiconductor; The manufacture method of the embodiment of the present invention one power semiconductor, for the preparation of the embodiment of the present invention one power semiconductor as shown in Figure 4 A and 4 B shown in FIG., comprises the steps:

Step one, is as shown in Figure 5A the section of structure along the E1F1 line of Fig. 3 in this step; As shown in Figure 5 B, be section of structure along the E2F2 line of Fig. 3 in this step; At described silicon substrate 1 surface deposit first silicon dioxide layer 31 and second silicon nitride layer 32 successively of N-type doping; Lithographic etch process is utilized to form groove figure mask to described second silicon nitride layer 32 and described first silicon dioxide layer 31 successively.

Step 2, is as shown in Figure 5A the section of structure along the E1F1 line of Fig. 3 in this step; As shown in Figure 5 B, be section of structure along the E2F2 line of Fig. 3 in this step; Multiple described groove is formed for mask carries out etching to described silicon substrate 1 with described groove figure mask; The forming region of described super junction drift region and described single drift region is defined by described groove.

Step 3, is as shown in Figure 6A the section of structure along the E1F1 line of Fig. 3 in this step; As shown in Figure 6B, be section of structure along the E2F2 line of Fig. 3 in this step; Carry out front and be deposited on the bottom surface of described groove and side forms described first N-type silicon epitaxy layer 3a; Described first low resistivity portion 3a and described second low resistivity portion 3a is formed respectively by described first N-type silicon epitaxy layer 3a.

Step 4, is as shown in Figure 6A the section of structure along the E1F1 line of Fig. 3 in this step; As shown in Figure 6B, be section of structure along the E2F2 line of Fig. 3 in this step; Carry out the described second P-type silicon epitaxial loayer 4 of middle formation that front is deposited on described groove, described second P-type silicon epitaxial loayer 4 contacts with described first N-type silicon epitaxy layer 3a and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed.

Step 5, is as shown in Figure 7 the section of structure along the E1F1 line of Fig. 3 in this step; Section of structure along the E2F2 line of Fig. 3 omits.

Form the grid structure of described MOSFET element, described grid structure comprises gate dielectric layer and polysilicon gate.The forming step of described grid structure comprises: adopt lithographic etch process to form gate groove at the top of the top of the described N-type thin layer of described super junction drift region and described single drift region; Deposit gate dielectric layer 5 and polysilicon gate 6, be preferably successively, and described gate dielectric layer 5 is gate oxide.Described gate dielectric layer 5 covers the lower surface of described gate groove and side and outside, described polysilicon gate 6 is formed at described gate dielectric layer 5 surface and is filled completely by described gate groove, remove described gate dielectric layer 5 and the described polysilicon gate 6 of described gate groove outside, be made up of the grid structure of described super junction trench gate mosfet device the described gate dielectric layer 5 and described polysilicon gate 6 that are filled in described gate groove inside.

Described P trap 7 is formed at the top of described drift region; The degree of depth of described gate groove is greater than the degree of depth of described P trap 7, described polysilicon gate 6 cover described P trap 7 from the side and described P trap 7 side that covers by described polysilicon gate 6 for the formation of longitudinal channel.

Carry out N+ ion implantation and form source region 8; The source region 8 be made up of N+ district is all formed at described P trap 7 top of the both sides of described gate groove.

Interlayer film 10 is formed in described silicon substrate 1 front defining described source region 8; Adopt lithographic etch process to form contact hole 11, described contact hole 11 also contacts with described source region 8 or described polysilicon gate 6 through described interlayer film 10; Carry out P+ ion implantation and form P trap draw-out area 9, described P trap draw-out area 9 is positioned at bottom the described contact hole 11 that contacts with described source region 8, and described P trap draw-out area 9 and described P trap 7 contact.

Deposit front metal 12 also carries out chemical wet etching to described front metal 12 and forms source electrode and grid respectively;

Step 6, as shown in Figure 8, carry out thinning from the back side to described silicon substrate 1.

Step 7, as shown in Figure 8, carry out back side N-type ion implantation and form N-type region 2 bottom described drift region; The implanted dopant of described N-type region 2 is arsenic, and Implantation Energy is 5KEV ~ 100KEV, and implantation dosage is at E15CM ^-2magnitude level, carry out formation low contact resistance with the back side.

When being also formed with N-type buffering area between described drift region and described N-type region 2, need employing twice injection to be formed, one is the high energy ion implantation forming described N-type buffering area, and Implantation Energy 1MEV ~ 5MEV, implantation dosage is at E12CM ^-2~ E13CM ^-2magnitude, implanted dopant is phosphorus, and puncture voltage and the switch performance of device can be improved in described N-type buffering area; One for forming the lower injection of the energy of described N-type region 2, implanted dopant is arsenic, and Implantation Energy is 5KEV ~ 100KEV, and implantation dosage is at E15CM ^-2magnitude level, carry out formation low contact resistance with the back side.

Step 8, as shown in Figure 8, the ion of described N-type region 2 or described N-type buffering area to be activated, adopt a laser annealing or a furnace anneal, or the combination of a laser annealing and a furnace anneal activates.

Step 9, as shown in Figure 4 A and 4 B shown in FIG., carries out back face metalization and forms drain electrode 13, and namely the bottom of described N-type region 2 and back metal drain 13 formation ohmic contact.

The embodiment of the present invention two manufacture method is for the preparation of the embodiment of the present invention one power semiconductor as shown in Figure 4 A and 4 B shown in FIG., the difference part of the embodiment of the present invention two method and the embodiment of the present invention one method is: before deposit first silicon dioxide layer 31 technique of described for the formation in the step 5 in the embodiment of the present invention one method P trap 7 being placed on step one and the second silicon nitride layer 32 technique, the numbering of subsequent step adds one respectively; Such energy reduces because the thermal process pushing away trap technique needs in described P trap 7 forming process is on the impact of Impurity Diffusion in P-N thin layer, improves the conduction resistance of device.

As shown in Figure 9 A, be the profile of the embodiment of the present invention two power semiconductor along the E1F1 line of Fig. 3; As shown in Figure 9 B, be the profile of the embodiment of the present invention two power semiconductor along the E2F2 line of Fig. 3; The difference part of the embodiment of the present invention two power semiconductor and the embodiment of the present invention one power semiconductor is: the embodiment of the present invention two power semiconductor is flat-grid MOSFET component, trench gate structure by the embodiment of the present invention one is transformed to planar gate and namely obtains the embodiment of the present invention two power semiconductor, described P trap 9 is spacer structure, in described super junction drift region, described P trap 9 is arranged in the top of each described P type thin layer 4 and extends to the described N-type thin layer of described P type thin layer 4 both sides; In described single drift region, described P trap 9 is positioned at the top of the described high-resistivity portions 3b of part; The planar gate of each described MOSFET cellular construction is made up of the gate dielectric layer 6 and polysilicon gate 6 being formed at described silicon substrate 1 surface successively, described planar gate from top, described P trap 9 is covered and the surface portion of described P trap 9 that covers by described planar gate for the formation of raceway groove, source region 8 and described planar gate autoregistration.

Trench gate structure in the grid structure of the described MOSFET element of formation in the step 5 in the embodiment of the present invention one method is changed to formation planar gate, then can obtain the embodiment of the present invention two power semiconductor; Trench gate structure in the grid structure of the described MOSFET element of formation in the step 6 in the embodiment of the present invention two method is changed to formation planar gate, then can obtain the embodiment of the present invention two power semiconductor.

As shown in Figure 10, be the vertical view in current flowing district of the embodiment of the present invention three power semiconductor, the profile of the embodiment of the present invention three power semiconductor along the E2F2 line of Figure 10 as described in Figure 11, the difference part of the embodiment of the present invention three power semiconductor and the embodiment of the present invention one power semiconductor is: the width of the single drift region of the embodiment of the present invention three device is larger than the width of the single drift region of the embodiment of the present invention one device, known as shown in Figure 10, the maximum of the width of described single drift region can be identical with the width of described super junction drift region, namely described single drift region Breadth Maximum by described super junction drift region outermost two grooves between spacing determine, the width of described single drift region is larger, the cellular construction of MOSFET element in parallel in described single drift region is more.

The profile of the embodiment of the present invention four power semiconductor along the E2F2 line of Figure 10 as described in Figure 12; The difference part of the embodiment of the present invention four power semiconductor and the embodiment of the present invention three power semiconductor is: the embodiment of the present invention four power semiconductor is flat-grid MOSFET component, and the planar gate of the embodiment of the present invention four power semiconductor is identical with the planar gate of the embodiment of the present invention two power semiconductor.

The difference part of the embodiment of the present invention five power semiconductor and the embodiment of the present invention one power semiconductor is: do not form described first N-type silicon epitaxy layer in described groove both sides in the embodiment of the present invention five device, each described N-type thin layer forms by by carrying out doping to the side of described silicon substrate thin layer, and described groove is filled completely by described second P-type silicon epitaxial loayer 4 and formed described P type thin layer 4.The described first low resistivity portion 3a of described N-type thin layer is the part of the side doping that the both sides of described silicon substrate thin layer were carried out.The process conditions of the described second low resistivity portion 3a of described first N-type layer are identical with described first low resistivity portion 3a, and the part of the side doping also undertaken by the both sides of described silicon substrate thin layer forms.In the embodiment of the present invention five, the width of groove is also different with the embodiment of the present invention one with the setting of spacing, in the embodiment of the present invention five by: described gash depth is 40 microns ~ 50 microns, the width of described groove is 3 microns, spacing in described super junction drift region between each adjacent described groove is 4 microns, and the spacing in described super junction drift region between each adjacent described groove corresponds to the spacing between B1B2, B3B4, B5B6 or B7B8 in Fig. 3; Spacing between the described groove of both sides, described single drift region is 10 microns, and the spacing between the described groove of both sides, described single drift region is all 4 microns corresponding to the spacing between the b3b6 in Fig. 3, other place.The thickness of described first low resistivity portion 3a is 1.5 microns, the thickness of described P type thin layer 4 is 3 microns, be in the described groove of 3 microns at each width, filled completely by a described P type thin layer 4, described P type thin layer 4 be by two width be 1.5 microns described second P-type silicon epitaxial loayer in the trench between engage after formed.

As shown in FIG. 13 to 15, be device profile map in each step of the embodiment of the present invention three manufacture method; The embodiment of the present invention three manufacture method is for the manufacture of the embodiment of the present invention five power semiconductor, and the difference part of the embodiment of the present invention three method and the embodiment of the present invention one method is:

The width of the groove that the step 2 of the embodiment of the present invention three method is formed, spacing are carried out according to the requirement of the embodiment of the present invention five power semiconductor; Namely the width of described groove is 3 microns, spacing in described super junction drift region between each adjacent described groove is 4 microns, and the spacing in described super junction drift region between each adjacent described groove corresponds to the spacing between B1B2, B3B4, B5B6 or B7B8 in Fig. 3; Spacing between the described groove of both sides, described single drift region is 10 microns, and the spacing between the described groove of both sides, described single drift region is all 4 microns corresponding to the spacing between the b3b6 in Fig. 3, other place.

That the described silicon substrate 1 of the bottom surface and side of carrying out groove described in phosphorus diffusion couple carries out adulterating and distinguishes described first low resistivity portion 3a and described second low resistivity portion 3a in the step 3 of the embodiment of the present invention three method, 1.5 microns are about, so the width of described first low resistivity portion 3a and described second low resistivity portion 3a is also all respectively 1.5 microns in the degree of depth when phosphorus diffusion on avris wall of described groove.

Other step of the embodiment of the present invention three method is identical with the embodiment of the present invention one method.

The difference part of the embodiment of the present invention six power semiconductor and the embodiment of the present invention five power semiconductor is: the embodiment of the present invention six power semiconductor is flat-grid MOSFET component, and the planar gate of the embodiment of the present invention six power semiconductor is identical with the planar gate of the embodiment of the present invention two power semiconductor.

Trench gate structure in the grid structure of the described MOSFET element of formation in the step 5 in the embodiment of the present invention three method is changed to formation planar gate, then can obtain the embodiment of the present invention six power semiconductor.

The difference part of the embodiment of the present invention seven power semiconductor and the embodiment of the present invention one power semiconductor is: the embodiment of the present invention seven device is trench gate IGBT device, also be formed by the p type island region of backside particulate injection region between the described N-type region 2 and described back metal 13 of the embodiment of the present invention seven device, the top of described N-type region contacts with bottom described drift region, the top of described p type island region contacts with the bottom of described N-type region, the bottom of described p type island region and back metal form ohmic contact.As shown in figure 17, be the embodiment of the present invention seven power semiconductor P/N thin layer bottom to the genesis analysis figure of impurity concentration at the silicon substrate back side, compare Figure 16 and Figure 17 known, the embodiment of the present invention seven power semiconductor is a many described p type island region.

The embodiment of the present invention four manufacture method is for the manufacture of the embodiment of the present invention seven power semiconductor, and the difference part of the embodiment of the present invention four method and the embodiment of the present invention one method is:

Carry out in the step 7 of the embodiment of the present invention four method after back side N-type ion implantation forms N-type region 2 bottom described drift region, also comprising and carrying out the processing step that back side P type ion implantation forms p type island region bottom described N-type region.

The difference part of the embodiment of the present invention eight power semiconductor and the embodiment of the present invention seven power semiconductor is: the embodiment of the present invention eight power semiconductor is planar gate IGBT device, and the planar gate of the embodiment of the present invention eight power semiconductor is identical with the planar gate of the embodiment of the present invention two power semiconductor.

Trench gate structure in the grid structure of the described IGBT device of formation in the step 5 in the embodiment of the present invention four method is changed to formation planar gate, then can obtain the embodiment of the present invention eight power semiconductor.

Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a power semiconductor, power semiconductor is formed in N-type silicon substrate, and the zone line of described power semiconductor is current flowing district, and terminal protection structure is surrounded on the periphery in described current flowing district; It is characterized in that: the drift region in described current flowing district comprises super junction drift region and single drift region, described super junction drift region is made up of multiple N-type thin layer of being alternately arranged and P type thin layer, and the first N-type layer adulterated by N-type in described single drift region forms; P trap is formed at the top of described drift region;

Described silicon substrate is formed with multiple groove, be silicon substrate thin layer between each adjacent described groove in described super junction drift region, each described N-type thin layer is by form by adulterating to the side of described silicon substrate thin layer or by described silicon substrate thin layer, each described N-type thin layer adds that the first N-type silicon epitaxy layer being formed at described silicon substrate thin layer both sides forms; Each described P type thin layer is made up of the second P-type silicon epitaxial loayer be filled in described groove;

The resistivity of described N-type thin layer is change in the horizontal and comprises the first high-resistivity portions and the first low resistivity portion, and described first low resistivity portion is the part of the side doping that the both sides of described silicon substrate thin layer were carried out or described first low resistivity portion is the described first N-type silicon epitaxy layer being formed at described silicon substrate thin layer both sides; Described first high-resistivity portions is made up of the described silicon substrate thin layer be positioned in the middle of described first low resistivity portion; Described first low resistivity portion and contiguous described P type thin layer contact; Charge balance is realized by described first low resistivity portion and its contiguous described P type thin layer;

The width of described first N-type layer is greater than the width of described N-type thin layer, and the width of described first N-type layer is by two adjacent ditch slot definitions, described first N-type layer comprises the second high-resistivity portions and the second low resistivity portion, described second high-resistivity portions is the mid portion of described first N-type layer, described second low resistivity portion is arranged in the both sides of described second high-resistivity portions and contacts with the described P type thin layer of the described groove being formed at described first N-type layer both sides, the process conditions of described second low resistivity portion are identical with described first low resistivity portion,

2. power semiconductor as claimed in claim 1, it is characterized in that: described power semiconductor is MOSFET element, bottom described drift region, be formed with the N-type region be made up of backside particulate injection region, the bottom of described N-type region and back metal form ohmic contact.

3. power semiconductor as claimed in claim 1, it is characterized in that: described power semiconductor is MOSFET element, be formed bottom described drift region and form N-type buffering area and N-type region by backside particulate injection region, the top of described N-type buffering area contacts with bottom described drift region, the top of described N-type region contacts with the bottom of described N-type buffering area, the bottom of described N-type region and back metal form ohmic contact; The doping content of described N-type region is greater than the doping content of described N-type buffering area.

4. power semiconductor as claimed in claim 1, it is characterized in that: described power semiconductor is IGBT device, be formed bottom described drift region and form N-type region and p type island region by backside particulate injection region, the top of described N-type region contacts with bottom described drift region, the top of described p type island region contacts with the bottom of described N-type region, the bottom of described p type island region and back metal form ohmic contact.

5. power semiconductor as claimed in claim 2 or claim 3, it is characterized in that: described power semiconductor is trench gate mosfet device, or described power semiconductor is flat-grid MOSFET component.

6. power semiconductor as claimed in claim 4, it is characterized in that: described power semiconductor is trench gate IGBT device, or described power semiconductor is planar gate IGBT device.

7. the power semiconductor as described in Claims 2 or 3 or 4, is characterized in that: the thickness of described N-type region is 0.5 micron ~ 5 microns.

8. power semiconductor as claimed in claim 1 or 2 or 3 or 4, it is characterized in that: described single drift region comprises the above first N-type layer, each described first N-type layer is distributed in the zones of different in described current flowing district, the regional location of each described first N-type layer is respectively by the described ditch slot definition of each described first N-type layer both sides, and the regional location place of each described first N-type layer is formed with the cellular construction of more than one described power semiconductor.

9. power semiconductor as claimed in claim 1 or 2 or 3 or 4, is characterized in that: each regional location of described first N-type layer and the region of described terminal protection structure do not adjoin.

10. power semiconductor as claimed in claim 1 or 2 or 3 or 4, is characterized in that: the region of the regional location of each described first N-type layer and the grid metal electrode figure of described power semiconductor does not adjoin.

The method of 11. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is MOSFET element, it is characterized in that, comprises the steps:

Step one, described surface of silicon deposit first silicon dioxide layer and the second silicon nitride layer successively adulterated in N-type; Lithographic etch process is utilized to form groove figure mask to described second silicon nitride layer and described first silicon dioxide layer successively;

Step 2, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple described groove; The forming region of described super junction drift region and described single drift region is defined by described groove;

Step 3, carry out front and be deposited on the bottom surface of described groove and side forms described first N-type silicon epitaxy layer; Described first low resistivity portion and described second low resistivity portion is formed respectively by described first N-type silicon epitaxy layer;

Step 4, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

Step 5, form the grid structure of described MOSFET element, described grid structure comprises gate dielectric layer and polysilicon gate; Form described P trap; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively;

Step 6, carry out thinning from the back side to described silicon substrate;

Step 7, carry out back side N-type ion implantation form N-type region bottom described drift region;

Step 8, the ion of described N-type region to be activated;

The method of 12. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is MOSFET element, it is characterized in that, comprises the steps:

Step one, N-type doping described silicon substrate on form described P trap;

Step 2, at described surface of silicon successively deposit first silicon dioxide layer and the second silicon nitride layer; Lithographic etch process is utilized to form groove figure mask to described second silicon nitride layer and described first silicon dioxide layer successively;

Step 3, with described groove figure mask for mask to described silicon substrate carry out etching formed multiple described groove; The forming region of described super junction drift region and described single drift region is defined by described groove;

Step 4, carry out front and be deposited on the bottom surface of described groove and side forms described first N-type silicon epitaxy layer; Described first low resistivity portion and described second low resistivity portion is formed respectively by described first N-type silicon epitaxy layer;

Step 5, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described second P-type silicon epitaxial loayer contacts with described first N-type silicon epitaxy layer and is filled up completely by described groove; The silicon of described groove top surface and silica are all removed;

Step 6, form the grid structure of described MOSFET element, described grid structure comprises gate dielectric layer and polysilicon gate; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively;

Step 7, carry out thinning from the back side to described silicon substrate;

Step 8, carry out back side N-type ion implantation form N-type region bottom described drift region;

Step 9, the ion of described N-type region to be activated;

The method of 13. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is MOSFET element, it is characterized in that, comprises the steps:

The described silicon substrate of step 3, the bottom surface of carrying out groove described in phosphorus diffusion couple and side carries out adulterating and distinguishes described first low resistivity portion and described second low resistivity portion;

Step 4, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described groove fills up by described second P-type silicon epitaxial loayer completely; The silicon of described groove top surface and silica are all removed;

Step 6, carry out thinning from the back side to described silicon substrate;

Step 8, the ion of described N-type region to be activated;

The method of 14. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is MOSFET element, it is characterized in that, comprises the steps:

Step one, N-type doping described silicon substrate on form described P trap;

The described silicon substrate of step 4, the bottom surface of carrying out groove described in phosphorus diffusion couple and side carries out adulterating and distinguishes described first low resistivity portion and described second low resistivity portion;

Step 5, carry out the described second P-type silicon epitaxial loayer of middle formation that front is deposited on described groove, described groove fills up by described second P-type silicon epitaxial loayer completely; The silicon of described groove top surface and silica are all removed;

Step 7, carry out thinning from the back side to described silicon substrate;

Step 9, the ion of described N-type region to be activated;

The method of 15. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is IGBT device, it is characterized in that, comprises the steps:

Step 5, form the grid structure of described IGBT device, described grid structure comprises gate dielectric layer and polysilicon gate; Form described P trap; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively;

Step 6, carry out thinning from the back side to described silicon substrate;

Step 7, carry out back side N-type ion implantation form N-type region bottom described drift region; Carry out back side P type ion implantation and form p type island region bottom described N-type region;

Step 8, the ion of described N-type region and described p type island region to be activated;

The method of 16. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is IGBT device, it is characterized in that, comprises the steps:

Step one, N-type doping described silicon substrate on form described P trap;

Step 6, form the grid structure of described IGBT device, described grid structure comprises gate dielectric layer and polysilicon gate; Carry out N+ ion implantation and form source region; Interlayer film is formed in the described silicon substrate front defining described source region; Adopt lithographic etch process to form contact hole, described contact hole also contacts with described source region or described polysilicon gate through described interlayer film; Carry out P+ ion implantation and form P trap draw-out area, described P trap draw-out area is positioned at bottom the described contact hole that contacts with described source region, and described P trap draw-out area and described P trap contact; Deposit front metal also carries out chemical wet etching to described front metal and forms source electrode and grid respectively;

Step 7, carry out thinning from the back side to described silicon substrate;

Step 8, carry out back side N-type ion implantation form N-type region bottom described drift region; Carry out back side P type ion implantation and form p type island region bottom described N-type region;

Step 9, the ion of described N-type region and described p type island region to be activated;

The method of 17. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is IGBT device, it is characterized in that, comprises the steps:

Step 6, carry out thinning from the back side to described silicon substrate;

The method of 18. 1 kinds of manufacture power semiconductors as claimed in claim 1, described power semiconductor is IGBT device, it is characterized in that, comprises the steps:

Step one, N-type doping described silicon substrate on form described P trap;

Step 7, carry out thinning from the back side to described silicon substrate;