JP4764974B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4764974B2
JP4764974B2 JP2001033408A JP2001033408A JP4764974B2 JP 4764974 B2 JP4764974 B2 JP 4764974B2 JP 2001033408 A JP2001033408 A JP 2001033408A JP 2001033408 A JP2001033408 A JP 2001033408A JP 4764974 B2 JP4764974 B2 JP 4764974B2
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parallel
vertical
substrate
conductivity type
drift
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JP2001298191A (en
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進 岩本
龍彦 藤平
勝典 上野
泰彦 大西
高広 佐藤
達司 永岡
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to DE10205345A priority patent/DE10205345B9/en
Priority to US10/073,671 priority patent/US6674126B2/en
Priority to US10/678,941 priority patent/US6903418B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）、ＩＧＢＴ（伝導度変調型ＭＯＳＦＥＴ）、バイポーラトンラジスタ等の能動素子やダイオード等の受動素子に適用可能で高耐圧化と大電流容量化が両立する縦形パワー半導体装置に関する。
【０００２】
一般に半導体装置は、基板の片面のみに電極部を持つ横形素子と、基板の両面に電極部を持つ縦形素子とに大別できる。縦形素子は、オン時にドリフト電流が流れる方向と、オフ時に逆バイアス電圧による空乏層が延びる方向とが共に基板の厚み方向（縦方向）である。例えば、図１３は通常のプレーナ型のｎチャネル縦形ＭＯＳＦＥＴの断面図である。この縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ＋ドレイン層１１の上に形成された高抵抗のｎ−ドレイン・ドリフト層１２と、このドリフト層１２の表面層に選択的に形成されたチャネル拡散層としてのｐベース領域（ｐウェル）１３と、そのｐベース領域１３内の表面側に選択的に形成された高不純物濃度のｎ＋ソース領域１４及びオーミックコンタクトを確保するための高不純物濃度のｐ＋コンタクト領域１９と、ｐベース領域１３のうちｎ＋ソース領域１４とドリフト層１２とに挟まれた表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、ｎ＋ソース領域１４及びｐ＋コンタクト領域１９の双方表面に導電接触するソース電極層１７とを有している。
【０００３】
このような縦形素子において、高抵抗のｎ−ドレイン・ドリフト層１２の部分は、ＭＯＳＦＥＴがオン状態のときは縦方向にドリフト電流を流す領域として働き、オフ状態のときはｐベース領域１３とのｐｎ接合から空乏層が深さ方向へ拡張して空乏化し耐圧を高める働きをする。この高抵抗のｎ−ドレイン・ドリフト層１２の厚さ（電流経路長）を薄くすることは、オン状態ではドリフト抵抗が低くなるのでＭＯＳＦＥＴの実質的なオン抵抗（ドレイン−ソース抵抗）を下げる効果に繋がるものの、オフ状態ではｐベース領域１３とｎ−ドレイン・ドリフト層１２との間のｐｎ接合から拡張するドレイン−ベース間空乏層の拡張幅が狭くなるため、空乏電界強度がシリコンの最大（臨界）電界強度に速く達するので、ドレイン−ソース電圧が素子耐圧の設計値に達する前に、ブレークダウンが生じ、耐圧（ドレイン−ソース電圧）が低下してしまう。逆に、ｎ−ドレイン・ドリフト層１２を厚く形成すると、高耐圧化を図ることができるが、必然的にオン抵抗が大きくなり、オン損失が増す。即ち、オン抵抗（電流容量）と耐圧との間にはトレードオフ関係がある。この関係は、ドリフト層を持つＩＧＢＴ，バイポーラトランジスタ，ダイオード等の半導体素子においても同様に成立することが知られている。
【０００４】
この問題に対する解決法として、縦形ドリフト部として不純物濃度を高めたｎ型の領域とｐ型の領域とを交互に繰り返して多重接合した並列ｐｎ構造である半導体装置が、ＥＰ００５３８５４、ＵＳＰ５２１６２７５、ＵＳＰ５４３８２１５、特開平９−２６６３１１、特開平１０−２２３８９６などにおいて知られている。
【０００５】
図１４は、ＵＳＰ５２１６２７５に開示された縦形ＭＯＳＦＥＴの一例を示す断面図である。図１３の半導体装置との構造上の違いは、ドレイン・ドリフト部２２が一様・単一のｎ−導電型層（不純物拡散層）ではなく、縦形層状のｎ型のドリフト電路領域２２ａと縦形層状のｐ型の仕切領域２２ｂとを交互に繰り返して多重接合した並列ｐｎ構造となっているところである。ｐベース領域１３のウェル底にｐ型の仕切領域２２ｂが接続し、相隣接するｐベース領域１３，１３のウェル端部の間にｎ型のドリフト電路領域２２ａが接続している。ドレイン・ドリフト部２２の並列ｐｎ構造の不純物濃度が高くても、オフ状態では並列ｐｎ構造の縦方向に配向する各ｐｎ接合から空乏層がその横方向双方に拡張し、ドリフト部２２全体が早期に空乏化するため、高耐圧化を図ることができる。なお、このような並列ｐｎ構造のドレイン部２２を備える半導体素子を、以下に超接合半導体素子と称することとする。
【０００６】
【発明が解決しようとする課題】
▲１▼ 上記のような超接合半導体素子にあっては、表層部分に形成された複数のｐベース領域１３（素子活性領域）の真下にある並列ｐｎ構造のドレイン・ドリフト部２２では耐圧確保が図れるものの、ドレイン・ドリフト部２２の周りの耐圧構造部では最外のｐベース領域１３のｐｎ接合からの空乏層が外方向や基板深部へは拡がり難く、空乏電界強度がシリコンの臨界電界強度に速く達するので、耐圧構造部で耐圧が低下してしまう。
【０００７】
ここに、最外のｐベース領域１３の耐圧構造部における耐圧も確保するために、耐圧構造部の表面側に公知の空乏電界制御手段としてのガードリングを形成することや、絶縁膜上に公知のフィールドプレートを適用することが考えられる。ところが、並列ｐｎ構造のドリフト部２２の形成によって従前に比しドリフト部２２では高耐圧化が期待できるのに、その耐圧構造部の耐圧確保のために従前通りのガードリングやフィールドプレートを併せて空乏電界強度の修正を外的付加により最適構造に設計するのはますます困難が伴い、半導体素子毎の信頼性が乏しく、またガードリングから離れた深部では空乏化せず電界強度の制御が不能であるため、ドリフト部２２での高耐圧化に追い付かず、全体として素子のバランスの良い高耐圧化が難しくなり、超接合半導体素子の機能を十分に引き出すことができない。また、その構造を実現するためのマスク形成、不純物導入及び拡散、あるいは金属被着及びそのパターニングというような追加工程が必要である。
【０００８】
▲２▼ 他方、パワー半導体装置においては、チャンネル幅を長くして電流容量を高めるために、ｐベース領域１３及びゲート電極層１６は平面的に環状又はストライプ状のセルとして長く引き延ばされており、配線抵抗を下げるために、ソース電極層１７はセル毎のｐベース領域１３上の接続孔又は接続溝を介してｎ＋ソース領域１４及びｐ＋コンタクト領域１９に接続し、各ゲート電極層１６を層間絶縁膜を介して覆う平面的連続層として形成されている。その平面的連続層の周囲端部は一般に電界集中を緩和するためのフィールドプレートとしてドリフト部２２よりも外側へ張り出ている（図示せず）。また、各セル毎のゲート電極層１６はゲート取り出し電極（ボンディングパッド）に接続し、このゲート取り出し電極はソース電極層１７である平面的連続層の一辺途中部，コーナー部又は央部を欠損した部分の絶縁膜上に位置し、少なくとも一部がソース電極層１７のフィールドプレート部分に近接又は囲まれている（図示せず）。
【０００９】
ドリフト部２２が並列ｐｎ構造となった超接合半導体素子では、遮断瞬時にキャリアの残留する状態で逆バイアス電圧が生じた際に起こるダイナミック・アバランシェ・ブレイクダウン（動的なだれ降伏）は、ドリフト部２２では低逆バイアス電圧（５０Ｖ程度）でも空乏層が急速に拡張するため、比較的に発生し難く、ダイナミック・アバランシェ・ブレイクダウンがドリフト部２２の主面側のいずれの部位で万一発生しても、セル毎の分散的配置のソース電極層１７のコンタクト部がその発生部位に必ず近接しているので、発生した過剰なホールはそのコンタクト部を介してソース電源に速やかに引き抜かれる。
【００１０】
しかしながら、ゲート取り出し電極の直下部分やソース電極層１７のフィールドプレートの直下部分ではドリフト部から外れた位置にあって局部的にｎ型領域となっているため、遮断瞬時には空乏層の拡張がドリフト部よりも遅れ、キャリアが残留し易く、ダイナミック・アバランシェ・ブレイクダウンを発生し易い。その上、ダイナミック・アバランシェ・ブレイクダウンがゲート取り出し電極の直下部分やソース電極層１７のフィールドプレートの直下部分で発生した場合、発生した過剰なホールはゲート取り出し電極と絶縁膜との界面に一旦蓄積した後、ソース電極層１７のうちゲート取り出し電極を囲むフィールドプレート部分に向けて一斉放電するため、発熱等により素子破壊を招くので、ゲート取り出し電極層の直下部分では、どうしてもドリフト部よりもダイナミック・アバランシェ・ブレイクダウン耐量が低くなるか、耐圧不安定性を招く。
【００１１】
そこで、上記問題点に鑑み、本発明の第１の課題は、基板表面にガードリングやフィールドプレートを形成せずとも、ドリフト部の耐圧よりもその外周部の耐圧を大きくできる半導体装置を提供することにある。
【００１２】
また、本発明の第２の課題は、ゲート取り出し電極層等のオン・オフ制御用の電極層の直下部分やフィールドプレートの直下部分でのダイナミック・アバランシェ・ブレイクダウンを抑制し、安定した耐圧の確保が可能であると共に、高いダイナミック・アバランシェ・ブレイクダウン耐量を得ることが可能な半導体装置を提供することにある。
【００１３】
【課題を解決するための手段】
本発明は以下の手段を講じたものである。まず、本発明に係る半導体装置は、基板の第１主面側に形成された活性部に導電接続する第１の電極層と、基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、活性部と低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、第１主面に絶縁膜を介して形成され、第１電極層に少なくとも一部が近接して成るオン・オフ制御用の第３電極層とを有するものであるが、超接合半導体素子として、縦形ドリフト部が基板の厚み方向に配向する縦形第１導電型領域と基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第１の並列ｐｎ構造となっている。本発明の第１の手段は、いわば３端子又はそれ以上の端子を持つ縦形能動半導体装置に適用できるものである。ここで、例えばＭＯＳＦＥＴの場合、ｎチャネル型のとき、活性部としては、ソース領域やャネル拡散領域層などを含み、第１の電極層はソース電極層、第２の電極層はドレイン電極層、外部接続用電極層としてゲート取り出し電極である。バイポーラトランジスタの場合、第２の電極層はエミッタ又はコレクタで、オン・オフ制御用の第３電極層である。
【００１４】
第１に、上記第１の課題を解決するため、本発明は、縦形ドリフト部の周りで第１主面と低抵抗層との間に介在し、オン状態では概ね非電路領域であってオフ状態では空乏化する耐圧構造部が、基板の厚み方向に配向する縦形第１導電型領域と基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造であことを特徴とする。
【００１５】
ドリフト部の周りの耐圧構造部に第２の並列ｐｎ構造が配置されているため、オフ状態では、多重のｐｎ接合面から空乏層が双方に拡張し、ドリフト部に限らず、そこから外方向や第２主面方向の深部まで空乏化するので、耐圧が大きくなる。また、第１主面側の活性部からドリフト部を介して第２主面側の第１導電型の低抵抗層に到達する直線状の電気力線の長さに比し、活性部の側部から耐圧構造部を介して第１導電型の低抵抗層にする曲線状の電気力線の方が長い分だけ、耐圧構造部の第２の並列ｐｎ構造とドリフト部が同一不純物濃度でも、耐圧構造部の第２の並列ｐｎ構造の空乏電界強度の方がドリフト部よりも低くなることから、耐圧構造部の耐圧はドリフト部の耐圧よりも大きい。従って、ドリフト部に第１の並列ｐｎ構造を採用した超接合半導体素子にあっても、その周りの耐圧構造部の耐圧が十分に保証されることになるため、ドリフト部の並列ｐｎ構造の最適化が容易で、超接合半導体素子の設計自由度が高まり、超接合半導体素子を実用化できる。
【００１６】
第２に、上記第２の課題を解決するために、本発明は、オン・オフ制御用の第３電極層の直下部分が、基板の厚み方向に配向する縦形第１導電型領域と基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第３の並列ｐｎ構造であり、第３の並列ｐｎ構造のｐｎ繰り返しピッチが第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭いことを特徴とする。オン・オフ制御用の第３電極層には第１の電極層の端部が近接している場合は、「第３電極層の直下部分」とは、第１の電極層の端部の直下部分も含むものである。
【００１７】
オン・オフ制御用の第３電極層は第１の電極層の一辺途中部，コーナー部又は央部を欠損した部分の絶縁膜上に位置し、少なくとも一部が第１の電極層に近接しているものであるが、第３電極層の直下部分も並列ｐｎ構造であって、そのｐｎ繰り返しピッチがドリフト部のｐｎ繰り返しピッチよりも狭くなっているため、第３電極層の直下部分ではドリフト部に比し単位面積当たりの空乏層が拡がり易く、素子耐圧が第３電極層の直下部分で決定されることはない。また、遮断瞬時には第３電極層の直下部分での空乏層の拡張がドリフト部よりも早まり、電界強度を緩和でき、キャリアがドリフト部側へ締め出されるため、第３電極層の直下部分ではダイナミック・アバランシェ・ブレイクダウンが発生し難くなる。従って、ダイナミック・アバランシェ・ブレイクダウンはドリフト部で発生し、第３電極層の直下部分でのダイナミック・アバランシェ・ブレイクダウンを抑制でき、安定した耐圧の確保が可能であると共に、高いダイナミック・アバランシェ・ブレイクダウン耐量を得ることができる。
【００１８】
ここで、第３電極層の直下部分の第３の並列ｐｎ構造の不純物濃度が第１の並列ｐｎ構造の不純物濃度よりも低い場合には、空乏層の拡張が一層拡がるため、なおさらダイナミック・アバランシェ・ブレイクダウンが発生し難くなる。勿論、耐圧構造部の第３の並列ｐｎ構造のｐｎ繰り返しピッチがドリフト部の第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも同等又は広い場合でも、相対的に第３の並列ｐｎ構造の不純物濃度を第１の並列ｐｎ構造の不純物濃度よりも低く設定することによっても、ダイナミック・アバランシェ・ブレイクダウンを発生し難くなる。
【００１９】
第２の並列ｐｎ構造のｐｎ繰り返しピッチは第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭くすることが望ましく、また、第２の並列ｐｎ構造の不純物濃度は第１の並列ｐｎ構造の不純物濃度よりも低くすることが望ましい。これは、耐圧がドリフト部の第１の並列ｐｎ構造で決定でき、また耐圧構造部でもダイナミック・アバランシェ・ブレイクダウンが起こり難くなるからである。
【００２０】
更に、第３の並列ｐｎ構造の第１主面側が第１電極層に導電接続する第２導電型ウェル領域で覆われて成る構成では、オフ時には第３の並列ｐｎ構造の各縦形第２導電型領域が確実に逆バイアスとなり、第２導電型領域のｐｎ接合から深さ方向にも空乏層が拡がり易く、第３電極層の直下部分では高耐圧であって、より一層ダイナミック・アバランシェ・ブレイクダウンが起こり難くなるため、アバランシェ耐量を向上できる。しかも、ダイナミック・アバランシェ・ブレイクダウンが第３電極層の直下部分で万一発生した場合、発生した過剰なホールは外部接続用電極層と絶縁膜との界面に蓄積することなく、キャリア引き抜き用として機能する第２導電型ウェル領域を介して第１電極層に引き抜かれるため、発熱等による素子破壊を招くことがない。
【００２１】
ここで、第３の並列ｐｎ構造の第１主面側を覆う第２導電型ウェル領域に着目すると、第２導電型ウェル領域が第３の並列ｐｎ構造の第１主面側の一部を覆う場合、第３の並列ｐｎ構造全体の空乏化が困難となるばかりか、第２導電型ウェル領域におけるウェル端部の曲面では電界集中が起こり易いので、第３の並列ｐｎ構造と第１の並列ｐｎ構造との境界に相当するｐｎ接合でダイナミック・アバランシェ・ブレイクダウンが発生し易くなる。
【００２２】
そこで、第３の並列ｐｎ構造は第２導電型領域のウェル両端部を除くウェル底に接続した構造を採用することが望ましい。斯かる場合、第３の並列ｐｎ構造全体を均等に空乏化することができる。第３電極層が第１の電極層の一辺途中部やコーナー部に位置するときは、第２導電型領域のウェル端部のいずれの部位がドリフト部の第１の並列ｐｎ構造の端部又は耐圧構造部の第２の並列ｐｎ構造の端部に接続し、また、第３電極層が第１の電極層の央部に位置するときは、第２導電型領域のウェル端部のいずれもの部位がドリフト部の第１の並列ｐｎ構造の端部に接続しているものであるから、第３の並列ｐｎ構造と第１の並列ｐｎ構造との境界に相当するｐｎ接合が第２導電型ウェル領域に接続し、ダイナミック・アバランシェ・ブレイクダウンの発生をドリフト部へ締め出すことができると共に、第３の並列ｐｎ構造と第２の並列ｐｎ構造との境界に相当するｐｎ接合も第２導電型ウェル領域に接続しているため、安定した耐圧が確保できる。特に、第１の並列ｐｎ構造における最端には縦形第２導電型領域を配置し、これが第２導電型ウェル領域のウェル端部側に接続していることが望ましい。隣接する第３の並列ｐｎ構造の最端の縦形第１導電型領域とのチャージバランスをとることができるからである。
【００２３】
第１の並列ｐｎ構造と前記第２の並列ｐｎ構造とが、平行に配置されていても、直交して配置されても構わない。また、第１の並列ｐｎ構造と第３の並列ｐｎ構造とが、平行に配置されていても、直交して配置されても構わない。第１、第２、及び第３の並列ｐｎ構造を構成する縦形第１導電型領域と縦形第２導電型領域は平面的にストライプ状とすることができるが、縦形第１導電型領域と縦形第２導電型領域が層状ではなく、少なくとも一方が柱状で、立体三方格子や立体四方格子等の立体的格子点に配置されていても良い。単位体積当たりのｐｎ接合面積の比率が増すため、耐圧が向上する。第１導電型領域と縦形第２導電型領域はそれぞれ一様不純物分布の連続拡散領域としても良いが、縦形第１導電型領域と縦形第２導電型領域のうち、少なくとも一方は基板の厚み方向に離散的に埋め込んだ複数の拡散単位領域が相互連結して成る会合構造とするのが望ましい。縦形の並列ｐｎ構造自体の形成が頗る容易となるからである。かかる場合、各拡散単位領域は中心部が最大濃度部となって外方向に濃度漸減する濃度分布を持つ。
【００２４】
上記第１の手段は、第３電極層がオン・オフ制御用の電極層であるため、３端子以上の縦形能動素子に適用するものであるが、第２の手段は、２端子の縦形受動素子にも適用できるものである。
【００２５】
即ち、上記第１の手段における第３電極層の有無に拘わらず、第２の手段は、第１の並列ｐｎ構造又は第２の並列ｐｎ構造のうち、少なくとも第１の電極層の周縁部の直下部分における並列ｐｎ構造のｐｎ繰り返しピッチが第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭くなっていることを特徴する。この第１の電極層の周縁部としては、一般にフィールドプレートとして機能しているものである。
【００２６】
斯かる手段によれば、第１の電極層の周縁部の直下部分での耐圧を向上できると共に、ダイナミック・アバランシェ・ブレイクダウン耐量を向上できる。その直下部分における並列ｐｎ構造の不純物濃度が第１の並列ｐｎ構造の不純物濃度よりも低くなっていることが望ましい。
【００２７】
また、その直下部分の並列ｐｎ構造の第１主面側は第１電極層に導電接続する第２導電型ウェル領域で覆われて成ることが望ましい。オフ時にはその直下部分を確実に逆バイアスに設定できるからであり、しかも、その直下部分でダイナミック・アバランシェ・ブレイクダウンが万一生じた場合にはキャリア引き抜き用として機能する第２導電型ウェル領域を介して第１電極層へキャリアを引き抜くことができ、素子破壊を防止できる。
【００２８】
そして、第１の並列ｐｎ構造のうち前記直下部分の並列ｐｎ構造に隣接する最端の縦形第２導電型領域は、第２導電型ウェル領域のウェル端部に接続していることが望ましい。直下部分の並列ｐｎ構造の最端の縦形第１導電型領域とその最端の縦形第２導電型領域とのｐｎ接合が第２導電型ウェル領域に接続しているため、ダイナミック・アバランシェ・ブレイクダウンが生じ難くなる。また、チャージバランスをとることができる。
【００２９】
【発明の実施の形態】
以下に本発明の実施例を添付図面に基づいて説明する。なお、以下でｎ又はｐを冠記した層や領域は、それぞれ電子又は正孔を多数キャリアとする層や領域を意味する。また、上付き文字＋は比較的高不純物濃度、上付き文字−は比較的低不純物濃度を意味する。
【００３０】
〔実施例１〕
図１は、本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図で、ＭＯＳＦＥＴの表面活性部や絶縁膜上のソース電極層及びゲート取り出し電極を省略してある。図２は、図１中の矩形範囲Ａ１−Ａ２−Ａ３−Ａ４を拡大して示す平面図である。図３は、図２中のＡ５−Ａ６線に沿って切断した状態を示す断面図である。
【００３１】
本例のｎチャネル縦形ＭＯＳＦＥＴは、裏側のドレイン電極１８が導電接触した低抵抗のｎ＋＋ドレイン層（ドレイン・コンタクト層）１１の上に形成された第１の並列ｐｎ構造のドレイン・ドリフト部１と、このドリフト部１の表面側に選択的に環状又はストライプ状のセルとして形成された不純物高濃度のｐベース領域（ｐウェル）１３と、そのｐベース領域１３内の表面側に選択的に形成された不純物高濃度のｎ＋ソース領域１４と、基板表面上にゲート絶縁膜１５を介して設けられたポリシリコン等のゲート電極層１６と、層間絶縁膜２０に開けたコンタクト孔を介してｐベース領域１３のｐ＋コンタクト領域１９及びｎ＋ソース領域１４の双方に導電接触するソース電極１７とを有している。ウェル状のｐベース領域１３の中にｎ＋ソース領域１４が浅く形成されており、２重拡散型ＭＯＳ部を構成している。ここで、この素子の表面活性部はｐベース領域１３及びソース領域１４に相当している。
【００３２】
このドレイン・ドリフト部１は、ｎ＋＋ドレイン層１１のサブストレートの上にｎ型のエピタキシャル成長層を幾層も積み増した厚い積層として形成されており、基板の厚み方向に層状縦形のｎ型ドリフト電路領域１ａと基板の厚み方向に層状縦形のｐ型仕切領域１ｂとを交互に繰り返して多重接合した構造である。本例では、ｎ型のドリフト電路領域１ａは、隣接するｐベース領域１３のウェル端部間に位置し、その上端が基板表面のチャネル領域１２ｅに達し、その下端がｎ＋＋ドレイン層１１に接している。また、ｐ型の仕切領域１ｂは、その上端がｐベース領域１３ａのウェル両端部を除くウェル底に接し、その下端がｎ＋＋ドレイン層１１に接している。本例は耐圧が６００Ｖクラスのものであり、ドリフト電路領域１ａとｐ型の仕切領域１ｂの層厚は共に８μｍで、深さは約４０μｍである。それぞれの不純物濃度は２．５×１０１５ｃｍ−３であるが、１×１０１５〜３×１０１５であれば良い。
【００３３】
図１に示すように、チップ平面に主体的に占めるドリフト部１の周りで、基板表面とｎ＋＋ドレイン層１１との間には、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部（素子外周部）２が形成されている。この耐圧構造部２は、基板の厚さ方向に配向する層状の縦形ｎ型領域２ａと、基板の厚さ方向に配向する層状の縦形ｐ型領域２ｂとを交互に繰り返して多重接合して成る第２の並列ｐｎ構造となっている。ドリフト部１の第１の並列ｐｎ構造と耐圧構造部２の第２の並列ｐｎ構造とは平行に配置されている。即ち、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造とは層面が相平行し、それらの境界部分では互いに逆導電型の領域となって、ｐｎ繰り返しが連続している。図２に示すように、耐圧構造部２の第２の並列ｐｎ構造におけるｐｎ繰り返し端面とドリフト部１の第２の並列ｐｎ構造におけるｐｎ繰り返し端面とが接続している。本例では、耐圧構造部２の第２の並列ｐｎ構造におけるｐｎ繰り返しピッチはドリフト部１の第１の並列ｐｎ構造におけるｐｎ繰り返しピッチよりも狭くなっている。また、耐圧構造部２の不純物濃度はドリフト部１の不純物濃度よりも低くなっている。縦形ｎ型領域２ａと縦形ｐ型領域２ｂの層厚は共に４μｍで、深さは約４０μｍである。それぞれの不純物濃度は２．５×１０１３ｃｍ−３であるが、２×１０１４ｃｍ−３以下であれば良い。なお、耐圧構造部２の表面上には、表面保護及び安定化のために、熱酸化膜又は燐シリカガラス（ＰＳＧ）から成る酸化膜（絶縁膜）２３が成膜されている。
【００３４】
耐圧構造部２の外側には、基板の厚み方向に配向し、比較的厚い層厚のｎ型チャネルストッパ領域２４が配置されている。このｎ型チャネルストッパ領域２４はｎ＋コンタクト領域２５を介してドレイン電圧と同電位の周縁電極２６に電気的に接続している。
【００３５】
ドリフト部１はチップ平面上で矩形領域を占め、その一辺中途部において、層間絶縁膜２０上にゲート取り出し電極３０が位置している。このゲート取り出し電極３０の周りにはソース電極層１７がフィールドプレート１７ａとして張り出している。ゲート取り出し電極３０の直下でドリフト部１の第１の並列ｐｎ構造と耐圧構造部２の第２の並列ｐｎ構造とに挟まれた直下部分は、第３の並列ｐｎ構造となっている。この第３の並列ｐｎ構造は、基板の厚さ方向に配向する層状の縦形ｎ型領域３ａと、基板の厚さ方向に配向する層状の縦形ｐ型領域３ｂとを交互に繰り返して多重接合して成る。ドリフト部１の第１の並列ｐｎ構造と直下部分３の第３の並列ｐｎ構造とは相平行して配置されている。即ち、ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相平行し、それらの境界部分では互いに逆導電型の領域となって、ｐｎ繰り返しが連続している。また、耐圧構造部２の第２の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相平行し、それらの境界部分では互いに逆導電型の領域となって、ｐｎ繰り返しが連続している。
【００３６】
本例では、直下部分３の第３の並列ｐｎ構造におけるｐｎ繰り返しピッチはドリフト部１の第１の並列ｐｎ構造におけるｐｎ繰り返しピッチよりも狭くなっており、耐圧構造部２の第２の並列ｐｎ構造におけるｐｎ繰り返しピッチと同じである。直下部分３の第３の並列ｐｎ構造の不純物濃度はドリフト部１の不純物濃度よりも低くなっており、耐圧構造部２の第２の並列ｐｎ構造の不純物濃度と同じである。ｎ型領域３ａとｐ型領域３ｂの層厚は共に４μｍで、深さは約４０μｍである。それぞれの不純物濃度は２．５×１０１３ｃｍ−３であるが、２×１０１４ｃｍ−３以下であれば良い。
【００３７】
直下部分３の第３の並列ｐｎ構造の表面側はｐ型ウェル領域４０で覆われており、ｐ型ウェル領域４０はその中に形成したｐ＋コンタクト領域４１を介してコンタクト領域に電気的に接続している。直下部分３の第３の並列ｐｎ構造はｐ型ウェル領域４０のウェル端を除くウェル底に接続している。ドリフト部１の最端の縦形仕切領域１ｂはｐ型ウェル領域４０の内側ウェル端寄りでウェル底に接続し、隣接する直下部分３のｎ型領域３ａとのｐｎ接合Ｊはｐ型領域４０のウェル底に接続している。耐圧構造部２の最端のｐ型領域２ｂはｐ型ウェル領域４０に外側ウェル端寄りで接続している。
【００３８】
なお、上記の並列ｐｎ構造は、縦形ｐ型領域と縦形ｎ型領域のうち、少なくとも一方は基板の厚み方向に離散的に埋め込んだ複数の拡散単位領域が相互連結して成る会合構造とするのが望ましい。並列ｐｎ構造自体の形成が頗る容易となるからである。かかる場合、各拡散単位領域は中心部が最大濃度部となって外方向に濃度漸減する濃度分布を持つものである。
【００３９】
次に本例の動作について説明する。ゲート電極層１６に所定の正の電位を印加すると、ｎチャネル型ＭＯＳＦＥＴはオン状態となり、ゲート電極層１６直下のｐベース領域１３の表面に誘起される反転層を介して、ソース領域１４からチャネル領域１２ｅに電子が注入され、その注入された電子がドリフト電路領域１ａを通ってｎ＋＋ドレイン層１１に達し、ドレイン電極１８とソース電極１７との間が導通する。
【００４０】
ゲート電極層１６への正の電位を取り去ると、ＭＯＳＦＥＴはオフ状態となり、ｐベース領域１３の表面に誘起される反転層が消滅し、ドレイン電極１８とソース電極１７との間が遮断する。更に、このオフ状態の際、逆バイアス電圧（ソース・ドレイン間電圧）が大きいと、ｐベース領域１３とチャネル領域１２ｅとの間のｐｎ接合からそれぞれｐベース領域１３とチャネル領域１２ｅに空乏層が拡張して空乏化すると共に、ドリフト部１の各仕切領域１ｂはｐベース領域１３を介してソース電極１７に電気的に接続し、ドリフト部１の各ドリフト電路領域１ａはｎ＋＋ドレイン層１１を介してドレイン電極１８に電気的に接続しているため、仕切領域１ｂとドリフト電路領域１ａとの間のｐｎ接合からの空乏層が仕切領域１ｂとドリフト電路領域１ａの双方に拡張するので、ドリフト部１の空乏化が早まる。従って、ドリフト部１の高耐圧化が十分確保されているので、ドリフト部１の不純物濃度を高く設定でき、大電流容量化も確保できる。
【００４１】
ここで、本例のドリフト部１の周りの耐圧構造部２には第２の並列ｐｎ構造が形成されている。この第２の並列ｐｎ構造の中で幾つかのｐ型領域２ｂは、ｐベース領域１３又はｐ型領域４０を介してソース電極１７に電気的に接続し、また各ｎ型領域２０ａはｎ＋＋ドレイン層１１を介してドレイン電極１８に電気的に接続しているため、耐圧構造部２のｐｎ接合から拡張した空乏層によって、基板厚み全長に亘り概ね空乏化される。このため、表面ガードリング構造やフィールドプレート構造のように耐圧構造部２の表面側を空乏化させるだけではなく、外周部や基板深部までも空乏化させることができるので、耐圧構造部２の電界強度を大幅緩和でき、高耐圧を確保できる。それ故、超接合半導体素子の高耐圧化を実現できる。
【００４２】
特に、本例では、耐圧構造部２の第２の並列ｐｎ構造は、ドリフト部１の第１の並列ｐｎ構造よりもｐｎ繰り返しピッチが狭く、しかも不純物量（不純物濃度）が低くなっているため、耐圧構造部２はドリフト部１よりも早く空乏化するため、耐圧信頼性が高い。耐圧構造部２のｐｎ繰り返し端面がドリフト部１のｐｎ繰り返し端面に接続しているため、耐圧構造部２の空乏化率は高い。従って、ドリフト部１に第１の並列ｐｎ構造を採用した超接合半導体素子にあっても、その周りの耐圧構造部２の耐圧が第２の並列ｐｎ構造によって十分に保証されることになるため、ドリフト部１の第１の並列ｐｎ構造の最適化が容易で、超接合半導体素子の設計自由度が高まり、超接合半導体素子を実用化できる。
【００４３】
本例はまた、ゲート取り出し電極３０の直下部分３の第３の並列ｐｎ構造がドリフト部１の第１の並列ｐｎ構造よりもｐｎ繰り返しピッチが狭く、しかも不純物濃度が低くなっているため、ゲート取り出し電極３０の直下部分３ではドリフト部１に比し単位面積当たりの空乏層が拡がり易く、素子耐圧が直下部分３で決定されることはない。特に、直下部分３の第３の並列ｐｎ構造がドリフト部１の第１の並列ｐｎ構造よりもｐｎ繰り返しピッチが狭いことから、直下部分３のいずれのｐ型領域３ｂもドリフト部１のｐ型仕切り領域１ｂの深さ方向に沿って接続しているため、電位浮遊状態にならず、直下部分３の空乏化を保証できる。換言すれば、ドリフト部１の第１の並列ｐｎ構造と直下部分３の第３の並列ｐｎ構造とが相平行である配置関係の場合には、ｐ型領域４０が存在しないときでも、ソース電位を直下部分３のいずれものｐ型領域３ｂに導電するためには、直下部分３の第３の並列ｐｎ構造のｐｎ繰り返しピッチをドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭くすることが望ましい。また、遮断時には直下部分３での空乏層の拡張がドリフト部１よりも早まり、電界強度を緩和でき、キャリアがドリフト部１側へ締め出されるため、直下部分３ではダイナミック・アバランシェ・ブレイクダウンが発生し難くなり、安定した耐圧の確保が可能であると共に、高いダイナミック・アバランシェ・ブレイクダウン耐量を得ることができる。
【００４４】
更に、第３の並列ｐｎ構造の表面側にはソース電極１７に電気的に接続するｐ型領域４０が存在するため、オフ時には第３の並列ｐｎ構造の各ｐ型領域２ｂが確実に逆バイアスとなり、ｐ型領域２ｂのｐｎ接合から深さ方向にも空乏層が拡がり易くなり、直下部分３では高耐圧であって、より一層ダイナミック・アバランシェ・ブレイクダウンが起こり難くなるため、アバランシェ耐量を向上できる。しかも、ダイナミック・アバランシェ・ブレイクダウンが直下部分３で万一発生した場合、発生した過剰なホールはｐ型領域４０を介してソース電極１７に引き抜かれるため、発熱等による素子破壊を招くことがない。
【００４５】
直下部分３の第３の並列ｐｎ構造はｐ型ウェル領域４０のウェル端を除くウェル底に接続しているため、第３の並列ｐｎ構造全体を均等に空乏化することができる。また、ドリフト部１の最端の縦形仕切領域１ｂはｐ型ウェル領域４０の内側ウェル端寄りでウェル底に接続し、隣接する直下部分３のｎ型領域３ａとのｐｎ接合Ｊはｐ型ウェル領域４０のウェル底に接続している。このため、内側ウェル端では電界集中が起こり易く、ダイナミック・アバランシェ・ブレイクダウンの発生を招き易いが、その発生をドリフト部１に締め出すことができると共に、隣接する第３の並列ｐｎ構造の最端のｎ型領域３ｂとのチャージバランスをとることができる。
【００４６】
なお、上記の並列ｐｎ構造１〜３のｎ型領域１ａ〜３ａ及びｐ型領域１ｂ〜３ｂは図２に示す如く平面的にストライプ状に形成されているが、図４に示す様に、地としてのｎ型領域１ａ′〜３ａ′の中にｐ型領域１ｂ′〜３ｂ′を平面的格子状に形成しても良い。ｐ型領域１ｂ′〜３ｂ′は基板の深さ方向に柱状である。各ｐ型領域１ｂ′〜３ｂ′は少なくとも一方は基板の厚み方向に離散的に埋め込んだ複数の拡散単位領域が相互連結して成る会合構造であり、各拡散単位領域は中心部が最大濃度部となって外方向に濃度漸減する濃度分布を持つものである。勿論、地としてのｐ型領域の中にｎ型領域を平面的格子状に形成しても良い。
【００４７】
なお、耐圧クラスを変更する場合、各並列ｐｎ構造の深さ方向の長さを耐圧クラスに応じた長さに変更すれば良い。例えば９００Ｖクラスの場合、６０μｍ程度であれば良い。更に、第２及び第３の並列ｐｎ構造は、そのピッチを狭くし、不純物濃度を低くしてあるが、ピッチが同じであっても濃度だけを低くすれば良い。第２及び第３の並列ｐｎ構造の不純物濃度は、第１の並列ｐｎ構造の不純物濃度の１／５〜１／１００程度が良い。
【００４８】
〔実施例２〕
図５は、本発明の実施例２に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図で、図２と同様に、図１中の矩形範囲Ａ１−Ａ２−Ａ３−Ａ４に相当している。
【００４９】
本例の実施例１との構造上の違いは、耐圧構造部２の第２の並列ｐｎ構造及び直下部分３の第３の並列ｐｎ構造がドリフト部１の第１の並列ｐｎ構造と直交して配置されているところである。即ち、ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造の層面とは相直交し、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造の層面とは相平行している。また、ドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチに比し、直下部分３と耐圧構造部２の並列ｐｎ構造のｐｎ繰り返しピッチの方が狭くなっており、約半分である。更に、ドリフト部１の不純物濃度に比し、直下部分３と耐圧構造部２の不純物濃度が低くなっている。図５中では、直下部分３の第３の並列ｐｎ構造の繰り返し端面とドリフト部１のｐ型仕切り領域１ｂｂとが接続している。このため、ドリフト部１の第１の並列ｐｎ構造と直下部分３の第３の並列ｐｎ構造とが相直交である配置関係の場合には、ｐ型ウェル領域４０が存在しないときでも、直下部分３とドリフト部１との境界の曲率線を考慮すれば、ｐ型領域４０が存在しないときでも、ソース電位を直下部分３のいずれものｐ型領域３ｂに導電することが可能であり、直下部分３におけるｐｎ繰り返しピッチの方をドリフト部１におけるｐｎ繰り返しピッチに比し狭くすることは必須ではない。
【００５０】
このような３つの並列ｐｎ構造の配列関係でも、実施例１と同様の作用効果を奏するものである。
【００５１】
〔実施例３〕
図６は、本発明の実施例３に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図で、ＭＯＳＦＥＴの表面活性化部や絶縁膜上のソース電極層及びゲート取り出し電極を省略してある。図７は、図６中の矩形範囲Ｂ１−Ｂ２−Ｂ３−Ｂ４を拡大して示す平面図である。図７中のＢ５−Ｂ６線に沿って切断した状態を示す断面図は、図３と同じである。
【００５２】
本例におけるゲート取り出し電極の直下部分３の第３の並列ｐｎ構造はドリフト部１の第１の並列ｐｎ構造のコーナー部に位置している。ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相平行し、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造の層面とは相平行している。また、ドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチに比し、直下部分３と耐圧構造部２の並列ｐｎ構造のｐｎ繰り返しピッチの方が狭くなっており、約半分である。更に、ドリフト部１の不純物濃度に比し、直下部分３と耐圧構造部２の不純物濃度が低くなっている。特に、直下部分３の第３の並列ｐｎ構造がドリフト部１の第１の並列ｐｎ構造よりもｐｎ繰り返しピッチが狭いことから、ｐ型ウェル領域４０が存在しないときでも、直下部分３のいずれのｐ型領域３ｂもドリフト部１のｐ型仕切り領域１ｂの深さ方向に沿って接続しているため、電位浮遊状態にならず、直下部分３の空乏化を保証できる。
【００５３】
このように、ゲート取り出し電極の直下部分３がドリフト部１のコーナー部に位置している場合でも、実施例１と同様な作用効果を奏するものである。
【００５４】
〔実施例４〕
図８は、本発明の実施例４に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図で、図７と同様に、図６中の矩形範囲Ｂ１−Ｂ２−Ｂ３−Ｂ４に相当している。
【００５５】
本例もまた、実施例３と同様に、ゲート取り出し電極の直下部分３の第３の並列ｐｎ構造はドリフト部１の第１の並列ｐｎ構造のコーナー部に位置しているが、ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相直交し、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造の層面とは相直交している。また、ドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチに比し、直下部分３と耐圧構造部２の並列ｐｎ構造のｐｎ繰り返しピッチの方が狭くなっており、約半分である。更に、ドリフト部１の不純物濃度に比し、直下部分３と耐圧構造部２の不純物濃度が低くなっている。
【００５６】
このように、ゲート取り出し電極の直下部分３がドリフト部１のコーナー部に位置している場合でも、実施例１と同様な作用効果を奏するものである。コーナー部では電界集中をできる限り避けるために、ドリフト部１と直下部分３との境界線は曲線を以って接続しているため、直下部分３における第３の並列ｐｎ構造のｐｎ繰り返し端面が一のｐ型仕切り領域に接続し難い。その曲線の曲率にもよるが、むしろ、直下部分３におけるｐｎ繰り返しピッチの方をドリフト部１におけるｐｎ繰り返しピッチに比し広くすると、ｐ型ウェル領域４０が存在しないときでも、ソース電位を直下部分３のいずれものｐ型領域３ｂに導電することが可能となる。
【００５７】
〔実施例５〕
図９は、本発明の実施例５に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図で、ＭＯＳＦＥＴの表面活性化部や絶縁膜上のソース電極層及びゲート取り出し電極を省略してある。図１０は、図９中の矩形範囲Ｃ１−Ｃ２−Ｃ３−Ｃ４を拡大して示す平面図である。図１１は、図１０中のＣ５−Ｃ６線に沿って切断した状態を示す断面図である。
【００５８】
本例におけるゲート取り出し電極３０の直下部分３の第３の並列ｐｎ構造はドリフト部１の第１の並列ｐｎ構造の中央部に位置している。ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相平行し、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造の層面とは相平行している。また、ドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチに比し、直下部分３と耐圧構造部２の並列ｐｎ構造のｐｎ繰り返しピッチの方が狭くなっており、約半分である。更に、ドリフト部１の不純物濃度に比し、直下部分３と耐圧構造部２の不純物濃度が低くなっている。直下部分３の第３の並列ｐｎ構造がドリフト部１の第１の並列ｐｎ構造よりもｐｎ繰り返しピッチが狭いことから、ｐ型ウェル領域４０が存在しないときでも、直下部分３のいずれのｐ型領域３ｂもドリフト部１のｐ型仕切り領域１ｂの深さ方向に沿って接続しているため、電位浮遊状態にならず、直下部分３の空乏化を保証できる。
【００５９】
本例では、ゲート取り出し電極３０がソース電極層１７の外周フィールドプレート１７ａはなく、内周フィールドプレート１７ｂに囲まれた領域に位置しているため、直下部分３の第３の並列ｐｎ構造がｐ型領域４０で覆われている外、外周フィールドプレート１７ａの直下部分における第２の並列ｐｎ構造がｐ型ウェル領域５０で覆われ、ｐ型ウェル領域５０の中にソース電極と導電接続するｐ＋コンタクト領域５１が形成されている。外周フィールドプレート１７ａの直下部分での空乏化を早め、ダイナミック・アバランシェ・ブレイクダウン耐量を確保できる。また、第１の並列ｐｎ構造の最端の仕切り領域１ｂがｐ型ウェル領域５０のウェル底に接続していので、隣接する第２の並列ｐｎ構造の最端のｎ型領域２ａとのチャージバランスをとることができる。
【００６０】
〔実施例６〕
図１２は、本発明の実施例４に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図である。図１０と同様に、図９中の矩形範囲Ｃ１−Ｃ２−Ｃ３−Ｃ４に相当している。
【００６１】
本例もまた、実施例５と同様に、ゲート取り出し電極の直下部分３の第３の並列ｐｎ構造はドリフト部１の第１の並列ｐｎ構造の中央部に位置しているが、ドリフト部１の第１の並列ｐｎ構造の層面と直下部分３の第３の並列ｐｎ構造との層面とは相直交し、ドリフト部１の第１の並列ｐｎ構造の層面と耐圧構造部２の第２の並列ｐｎ構造の層面とは相直交している。また、ドリフト部１の第１の並列ｐｎ構造のｐｎ繰り返しピッチに比し、直下部分３と耐圧構造部２の並列ｐｎ構造のｐｎ繰り返しピッチの方が狭くなっており、約半分である。更に、ドリフト部１の不純物濃度に比し、直下部分３と耐圧構造部２の不純物濃度が低くなっている。
【００６２】
直下部分３における第３の並列ｐｎ構造のｐｎ繰り返し端面が一のｐ型仕切り領域に接続しているため、ｐ型ウェル領域４０が存在しないときでも、ソース電位を直下部分３のいずれものｐ型領域３ｂに導電することが可能となる。そして、ゲート取り出し電極の直下部分３がドリフト部１のコーナー部に位置している場合でも、実施例５と同様な作用効果を奏するものである。
【００６３】
なお、上記各実施例では２重拡散型の縦形ＭＯＳＦＥＴについて説明したが、本発明はＩＧＢＴ（伝導度変調型ＭＯＳＦＥＴ）、バイポーラトランジスタなどの３端子以上の縦形能動素子は勿論のこと、２端子の受動素子に適用できるものである。
【００６４】
【発明の効果】
以上説明したように、本発明は、ドリフト部の周りの耐圧構造部を並列ｐｎ構造とすると共に、第３電極層の直下部分や第１の電極層の周縁部の直下部分もまた並列ｐｎ構造としながら、その直下部分のｐｎ繰り返しピッチをドリフト部のそれに比して狭くするか、或いはその直下部分の不純物濃度をドリフト部のそれに比して低くした点に特徴を有するものであるから、次のような効果を奏する。
【００６５】
（１） ドリフト部の周りに並列ｐｎ構造が配置されているため、オフ状態では、多重のｐｎ接合面から空乏層が拡張し、活性部の近傍に限らず、外方向や第２主面側まで空乏化するので、耐圧構造部の耐圧はドリフト部の耐圧よりも大きい。従って、ドリフト部に縦形の並列ｐｎ構造を採用した超接合半導体素子においても、耐圧構造部の耐圧が十分に保証されていることになるため、ドリフト部の並列ｐｎ構造の最適化が容易で、超接合半導体素子の設計自由度が高まり、超接合半導体素子を実用化できる。耐圧構造部の並列ｐｎ構造がドリフト部の並列ｐｎ構造よりも不純物量の少ない場合、又は耐圧構造部の並列ｐｎ構造がドリフト部の並列ｐｎ構造よりもｐｎ繰り返しピッチの狭い場合、耐圧構造部の耐圧をドリフト部の耐圧よりも確実に大きくでき、信頼性が向上する。
【００６６】
（２） 第３電極層の直下部分又は第１の電極層の周縁部の直下部分も並列ｐｎ構造であって、そのｐｎ繰り返しピッチがドリフト部のｐｎ繰り返しピッチよりも狭くなっているため、直下部分ではドリフト部に比し単位面積当たりの空乏層が拡がり易く、直下部分で決定されることはない。また、遮断瞬時には直下部分での空乏層の拡張がドリフト部よりも早まり、電界強度を緩和でき、キャリアがドリフト部側へ締め出されるため、直下部分ではダイナミック・アバランシェ・ブレイクダウンが発生し難くなる。従って、ダイナミック・アバランシェ・ブレイクダウンはドリフト部で発生し、直下部分でのダイナミック・アバランシェ・ブレイクダウンを抑制でき、安定した耐圧の確保が可能であると共に、高いダイナミック・アバランシェ・ブレイクダウン耐量を得ることができる。直下部分の不純物濃度がドリフト部のそれに比して低い場合も同様の効果を得ることができる。
【００６７】
（３） 直下部分の第１主面側が第１電極層に導電接続する第２導電型ウェル領域で覆われて成る構成では、オフ時には第３の並列ｐｎ構造の各縦形第２導電型領域が確実に逆バイアスとなり、第２導電型領域のｐｎ接合から深さ方向にも空乏層が拡がり易く、第３電極層の直下部分では高耐圧であって、より一層ダイナミック・アバランシェ・ブレイクダウンが起こり難くなるため、アバランシェ耐量を向上できる。しかも、ダイナミック・アバランシェ・ブレイクダウンが第３電極層の直下部分で万一発生した場合、キャリア引き抜き用として機能する第２導電型ウェル領域を介して第１電極層に引き抜かれるため、発熱等による素子破壊を招くことがない。
【図面の簡単な説明】
【図１】本発明の実施例１に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図２】図１中の矩形範囲Ａ１−Ａ２−Ａ３−Ａ４を拡大して示す平面図である。
【図３】図２中のＡ５−Ａ６線に沿って切断した状態を示す断面図である。
【図４】実施例１における並列ｐｎ構造の変形例を示す平面図である。
【図５】本発明の実施例２に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図である。
【図６】本発明の実施例３に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図７】図６中の矩形範囲Ｂ１−Ｂ２−Ｂ３−Ｂ４を拡大して示す平面図である。
【図８】本発明の実施例４に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図である。
【図９】本発明の実施例５に係る縦形ＭＯＳＦＥＴ素子のチップを示す概略平面図である。
【図１０】図９中の矩形範囲Ｃ１−Ｃ２−Ｃ３−Ｃ４を拡大して示す平面図である。
【図１１】図１０中のＣ５−Ｃ６線に沿って切断した状態を示す断面図である。
【図１２】本発明の実施例６に係る縦形ＭＯＳＦＥＴにおけるチップの左上範囲を拡大して示す平面図である。
【図１３】従来の単一導電型のドリフト層を持つ縦形ＭＯＳＦＥＴを示す部分断面図である。
【図１４】従来の並列ｐｎ構造のドリフト層を持つ縦形ＭＯＳＦＥＴを示す部分断面図である。
【符号の説明】
１…ドレイン・ドリフト部
１ａ，１ａ′…ｎ型ドリフト電路領域
１ｂ，１ｂ′…ｐ型仕切領域
２…耐圧構造部
２ａ，２ａ′，３ａ，３ａ′…縦形ｎ型領域
２ｂ，２ｂ′，３ｂ，３ｂ′…縦形ｐ型領域
３…ゲート取り出し電極の直下部分
１１…ｎ＋ドレイン層
１２ｅ…チャネル領域
１３…高不純物濃度のｐベース領域（ｐウェル）
１４…ｎ＋ソース領域
１５…ゲート絶縁膜
１６…ゲート電極層
１７…ソース電極
１７ａ，１７ｂ…フィールドプレート
１８…ドレイン電極
１９，２１，５１…ｐ＋コンタクト領域
２０…層間絶縁膜
２４…ｎ型チャネルストッパ領域
２５…ｎ＋コンタクト領域
２６…周縁電極
３０…ゲート取り出し電極
４０，５０…ｐ型ウェル領域
Ｊ…ｐｎ接合[0001]
BACKGROUND OF THE INVENTION
The present invention can be applied to active elements such as MOSFETs (insulated gate field effect transistors), IGBTs (conductivity modulation MOSFETs) and bipolar transistors, and passive elements such as diodes. The present invention relates to a compatible vertical power semiconductor device.
[0002]
In general, semiconductor devices can be broadly classified into horizontal elements having electrode portions only on one side of the substrate and vertical elements having electrode portions on both sides of the substrate. In the vertical element, the direction in which the drift current flows when turned on and the direction in which the depletion layer is extended by the reverse bias voltage when turned off are both in the thickness direction (vertical direction) of the substrate. For example, FIG. 13 is a cross-sectional view of a normal planar type n-channel vertical MOSFET. This vertical MOSFET has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact. + High resistance n formed on the drain layer 11 − The drain / drift layer 12, a p base region (p well) 13 as a channel diffusion layer selectively formed in the surface layer of the drift layer 12, and selectively formed on the surface side in the p base region 13 High impurity concentration n + High impurity concentration p for securing source region 14 and ohmic contact + N of contact region 19 and p base region 13 + A gate electrode layer 16 such as polysilicon provided on a surface sandwiched between the source region 14 and the drift layer 12 via a gate insulating film 15; + Source region 14 and p + A source electrode layer 17 is provided in conductive contact with both surfaces of the contact region 19.
[0003]
In such a vertical element, high resistance n − The drain / drift layer 12 functions as a region in which drift current flows in the vertical direction when the MOSFET is in the on state, and the depletion layer extends in the depth direction from the pn junction with the p base region 13 in the off state. It works to increase the pressure resistance. N of this high resistance − Reducing the thickness (current path length) of the drain / drift layer 12 leads to an effect of lowering the substantial on-resistance (drain-source resistance) of the MOSFET because the drift resistance is lowered in the on-state. Then, p base region 13 and n − Since the extension width of the drain-base depletion layer extending from the pn junction with the drain / drift layer 12 is narrowed, the depletion electric field intensity quickly reaches the maximum (critical) electric field intensity of silicon, so that the drain-source voltage is Before reaching the design value of the element breakdown voltage, breakdown occurs, and the breakdown voltage (drain-source voltage) decreases. Conversely, n − When the drain / drift layer 12 is formed thick, a high breakdown voltage can be achieved, but an on-resistance is inevitably increased and an on-loss is increased. That is, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage. It is known that this relationship holds true for semiconductor elements such as IGBTs, bipolar transistors, and diodes having a drift layer as well.
[0004]
As a solution to this problem, a semiconductor device having a parallel pn structure in which an n-type region and a p-type region having a high impurity concentration are alternately and repeatedly joined as a vertical drift portion is disclosed in EP0053854, USP5216275, USP5438215, It is known in Kaihei 9-266611, JP-A-10-223896, and the like.
[0005]
FIG. 14 is a cross-sectional view showing an example of a vertical MOSFET disclosed in US Pat. No. 5,216,275. The difference in structure from the semiconductor device of FIG. 13 is that the drain / drift portion 22 is uniform / single n − It is not a conductive type layer (impurity diffusion layer), but has a parallel pn structure in which a vertical layer-like n-type drift electric circuit region 22a and a vertical layer-like p-type partition region 22b are alternately and repeatedly joined. A p-type partition region 22 b is connected to the well bottom of the p base region 13, and an n-type drift circuit region 22 a is connected between the well ends of the adjacent p base regions 13 and 13. Even if the impurity concentration of the parallel pn structure of the drain / drift portion 22 is high, the depletion layer extends in both the lateral directions from each pn junction oriented in the vertical direction of the parallel pn structure in the off state, and the entire drift portion 22 is early. Therefore, a high breakdown voltage can be achieved. Hereinafter, a semiconductor element including such a drain portion 22 having a parallel pn structure will be referred to as a super junction semiconductor element.
[0006]
[Problems to be solved by the invention]
(1) In the superjunction semiconductor device as described above, withstand voltage can be secured in the drain / drift portion 22 having a parallel pn structure directly below the plurality of p base regions 13 (device active regions) formed in the surface layer portion. However, in the breakdown voltage structure around the drain / drift portion 22, the depletion layer from the pn junction of the outermost p base region 13 does not easily extend outward or deep in the substrate, and the depletion electric field strength becomes the critical electric field strength of silicon. Since it reaches quickly, the breakdown voltage decreases at the breakdown voltage structure.
[0007]
Here, in order to ensure the breakdown voltage in the breakdown voltage structure portion of the outermost p base region 13, a guard ring as a known depletion electric field control means is formed on the surface side of the breakdown voltage structure portion, or on the insulating film. It is conceivable to apply the following field plate. However, although the drift portion 22 can be expected to have a higher breakdown voltage than before due to the formation of the drift portion 22 of the parallel pn structure, the conventional guard ring and field plate are also used for securing the breakdown voltage of the breakdown voltage structure portion. It is increasingly difficult to design an optimum structure by externally adding a depletion field strength correction. The reliability of each semiconductor element is poor, and the field strength cannot be controlled without being depleted in the deep part away from the guard ring. Therefore, it is difficult to keep up with the high breakdown voltage in the drift portion 22 and it is difficult to increase the breakdown voltage with a good balance of the elements as a whole, and the function of the super junction semiconductor element cannot be fully exploited. Further, additional steps such as mask formation, impurity introduction and diffusion, or metal deposition and patterning for realizing the structure are necessary.
[0008]
(2) On the other hand, in the power semiconductor device, the p base region 13 and the gate electrode layer 16 are elongated as a ring or stripe cell in plan view in order to increase the channel width and increase the current capacity. In order to reduce the wiring resistance, the source electrode layer 17 is n through a connection hole or a connection groove on the p base region 13 for each cell. + Source region 14 and p + It is connected to the contact region 19 and is formed as a planar continuous layer covering each gate electrode layer 16 via an interlayer insulating film. The peripheral edge of the planar continuous layer generally projects outward from the drift portion 22 as a field plate for relaxing electric field concentration (not shown). In addition, the gate electrode layer 16 for each cell is connected to a gate extraction electrode (bonding pad), and this gate extraction electrode lacks a middle portion, a corner portion, or a central portion of one side of the planar continuous layer that is the source electrode layer 17. It is located on a portion of the insulating film, and at least a part thereof is close to or surrounded by the field plate portion of the source electrode layer 17 (not shown).
[0009]
In a superjunction semiconductor device in which the drift portion 22 has a parallel pn structure, dynamic avalanche breakdown (dynamic avalanche breakdown) that occurs when a reverse bias voltage is generated in a state where carriers remain at the moment of interruption is 22, the depletion layer rapidly expands even at a low reverse bias voltage (about 50 V), so that it is relatively difficult to occur, and a dynamic avalanche breakdown should occur in any part on the main surface side of the drift portion 22. However, since the contact portions of the source electrode layer 17 in a distributed arrangement for each cell are always close to the generation site, the generated excess holes are quickly extracted to the source power supply through the contact portions.
[0010]
However, since the portion immediately below the gate extraction electrode and the portion immediately below the field plate of the source electrode layer 17 are located away from the drift portion and are locally n-type regions, the depletion layer expands at the moment of interruption. It is later than the drift part, carriers are likely to remain, and dynamic avalanche breakdown is likely to occur. In addition, when a dynamic avalanche breakdown occurs in a portion directly under the gate extraction electrode or a portion immediately under the field plate of the source electrode layer 17, the generated excess holes are temporarily accumulated at the interface between the gate extraction electrode and the insulating film. After that, since simultaneous discharge is performed toward the field plate portion surrounding the gate extraction electrode in the source electrode layer 17, the element is destroyed due to heat generation or the like. Therefore, in the portion immediately below the gate extraction electrode layer, it is inevitably more dynamic than the drift portion. The avalanche breakdown resistance is lowered, or the pressure breakdown is unstable.
[0011]
Accordingly, in view of the above problems, a first object of the present invention is to provide a semiconductor device that can increase the breakdown voltage of its outer peripheral portion more than that of the drift portion without forming a guard ring or a field plate on the substrate surface. There is.
[0012]
In addition, the second problem of the present invention is to suppress a dynamic avalanche breakdown at a portion directly under an on / off control electrode layer such as a gate lead-out electrode layer or a portion directly under a field plate, and to achieve a stable withstand voltage. An object of the present invention is to provide a semiconductor device that can be secured and can obtain a high dynamic avalanche breakdown capability.
[0013]
[Means for Solving the Problems]
The present invention takes the following measures. First, a semiconductor device according to the present invention includes a first electrode layer conductively connected to an active portion formed on a first main surface side of a substrate, and a first conductivity type formed on a second main surface side of the substrate. A second electrode layer that is conductively connected to the low resistance layer, a vertical drift portion that is interposed between the active portion and the low resistance layer, flows a drift current in the vertical direction in the on state, and is depleted in the off state; 1 having a third electrode layer for on / off control formed on an insulating film on one main surface and at least partially adjacent to the first electrode layer. The drift portion has a first parallel pn structure in which a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate are alternately and repeatedly joined. . The first means of the present invention can be applied to a vertical active semiconductor device having three terminals or more. Here, for example, in the case of a MOSFET in the case of an n-channel type, the active portion includes a source region, a channel diffusion region layer, and the like, the first electrode layer is a source electrode layer, the second electrode layer is a drain electrode layer, It is a gate extraction electrode as an external connection electrode layer. In the case of a bipolar transistor, the second electrode layer is an emitter or a collector and is a third electrode layer for on / off control.
[0014]
First, in order to solve the first problem, the present invention is interposed between the first main surface and the low-resistance layer around the vertical drift portion, and in the on-state, is generally a non-electric circuit region and is off. In the state, the breakdown voltage structure depleted is a second first conductive type region oriented in the thickness direction of the substrate and a second vertical conductivity type region oriented in the thickness direction of the substrate, which are alternately and repeatedly joined. It is a parallel pn structure.
[0015]
Since the second parallel pn structure is arranged in the breakdown voltage structure around the drift portion, in the off state, the depletion layer extends to both sides from the multiple pn junction surfaces, and not only the drift portion but also outward from there Further, since the depletion is performed up to the deep part in the second main surface direction, the breakdown voltage is increased. In addition, the active portion side is longer than the length of the straight line of electric force reaching the first conductive type low resistance layer on the second main surface side from the active portion on the first main surface side through the drift portion. Even if the second parallel pn structure of the breakdown voltage structure portion and the drift portion have the same impurity concentration, the curved line of electric force that makes the first conductive type low resistance layer through the breakdown voltage structure portion has a longer length. Since the depletion electric field strength of the second parallel pn structure of the breakdown voltage structure portion is lower than that of the drift portion, the breakdown voltage of the breakdown voltage structure portion is larger than the breakdown voltage of the drift portion. Therefore, even in the superjunction semiconductor element adopting the first parallel pn structure in the drift portion, the withstand voltage of the surrounding withstand voltage structure portion is sufficiently ensured. Therefore, the design flexibility of the superjunction semiconductor element is increased, and the superjunction semiconductor element can be put into practical use.
[0016]
Secondly, in order to solve the second problem, the present invention provides a vertical first conductivity type region in which a portion immediately below the third electrode layer for on / off control is oriented in the thickness direction of the substrate and the substrate. The third parallel pn structure is formed by alternately and repeatedly joining the vertical second conductivity type regions oriented in the thickness direction, and the pn repetition pitch of the third parallel pn structure is the pn repetition of the first parallel pn structure. It is characterized by being narrower than the pitch. When the end of the first electrode layer is close to the third electrode layer for on / off control, the “directly under the third electrode layer” is directly under the end of the first electrode layer. The part is also included.
[0017]
The third electrode layer for on / off control is located on the insulating film in a portion lacking the middle part, corner part or central part of one side of the first electrode layer, and at least part of the third electrode layer is close to the first electrode layer. However, since the portion immediately below the third electrode layer has a parallel pn structure and the pn repetition pitch is narrower than the pn repetition pitch of the drift portion, the portion immediately below the third electrode layer has a drift. The depletion layer per unit area is likely to expand as compared with the portion, and the device breakdown voltage is not determined immediately below the third electrode layer. In addition, since the depletion layer expands immediately below the third electrode layer earlier than the drift portion at the instant of interruption, the electric field strength can be relaxed and carriers are pushed out to the drift portion side. Dynamic avalanche breakdown is less likely to occur. Therefore, the dynamic avalanche breakdown occurs in the drift portion, the dynamic avalanche breakdown can be suppressed in the portion immediately below the third electrode layer, a stable breakdown voltage can be secured, and a high dynamic avalanche breakdown can be achieved. Breakdown tolerance can be obtained.
[0018]
Here, when the impurity concentration of the third parallel pn structure immediately below the third electrode layer is lower than the impurity concentration of the first parallel pn structure, the expansion of the depletion layer is further expanded, so that the dynamic avalanche is further increased.・ Breakdown is less likely to occur. Of course, even when the pn repetition pitch of the third parallel pn structure of the breakdown voltage structure portion is equal to or wider than the pn repetition pitch of the first parallel pn structure of the drift portion, the impurity concentration of the third parallel pn structure is relatively large. Is set lower than the impurity concentration of the first parallel pn structure, it is difficult to generate dynamic avalanche breakdown.
[0019]
The pn repetition pitch of the second parallel pn structure is preferably narrower than the pn repetition pitch of the first parallel pn structure, and the impurity concentration of the second parallel pn structure is the impurity concentration of the first parallel pn structure. It is desirable to make it lower. This is because the breakdown voltage can be determined by the first parallel pn structure of the drift portion, and dynamic avalanche breakdown is less likely to occur in the breakdown voltage structure portion.
[0020]
Further, in the configuration in which the first main surface side of the third parallel pn structure is covered with the second conductivity type well region conductively connected to the first electrode layer, each vertical second conductivity of the third parallel pn structure is turned off. The type region is surely reverse-biased, the depletion layer tends to spread in the depth direction from the pn junction of the second conductivity type region, and has a high breakdown voltage immediately below the third electrode layer, so that a more dynamic avalanche break The avalanche resistance can be improved because the down is less likely to occur. Moreover, if a dynamic avalanche breakdown occurs in the portion immediately below the third electrode layer, the excess holes generated do not accumulate at the interface between the external connection electrode layer and the insulating film, and are used for carrier extraction. Since the first electrode layer is pulled out via the functioning second conductivity type well region, element destruction due to heat generation or the like is not caused.
[0021]
Here, focusing on the second conductivity type well region covering the first main surface side of the third parallel pn structure, the second conductivity type well region covers a part of the first main surface side of the third parallel pn structure. When covering, not only is it difficult to deplete the entire third parallel pn structure, but electric field concentration is likely to occur on the curved surface of the well end in the second conductivity type well region. Dynamic avalanche breakdown is likely to occur at the pn junction corresponding to the boundary with the parallel pn structure.
[0022]
Therefore, it is desirable to adopt a structure in which the third parallel pn structure is connected to the well bottom except for both ends of the well of the second conductivity type region. In such a case, the entire third parallel pn structure can be depleted equally. When the third electrode layer is located in the middle or corner of one side of the first electrode layer, any portion of the well end portion of the second conductivity type region is the end portion of the first parallel pn structure of the drift portion or When connected to the end of the second parallel pn structure of the breakdown voltage structure and the third electrode layer is located at the center of the first electrode layer, any of the well ends of the second conductivity type region Since the part is connected to the end of the first parallel pn structure of the drift portion, the pn junction corresponding to the boundary between the third parallel pn structure and the first parallel pn structure is the second conductivity type. Connected to the well region, generation of dynamic avalanche breakdown can be shut out to the drift portion, and a pn junction corresponding to the boundary between the third parallel pn structure and the second parallel pn structure is also of the second conductivity type. Since it is connected to the well region, stable withstand voltage is ensured. It can be. In particular, it is desirable that a vertical second conductivity type region is disposed at the outermost end in the first parallel pn structure, and this is connected to the well end portion side of the second conductivity type well region. This is because it is possible to achieve charge balance with the outermost vertical first conductivity type region of the adjacent third parallel pn structure.
[0023]
The first parallel pn structure and the second parallel pn structure may be arranged in parallel or orthogonal to each other. Further, the first parallel pn structure and the third parallel pn structure may be arranged in parallel or orthogonal to each other. The vertical first conductivity type region and the vertical second conductivity type region constituting the first, second, and third parallel pn structures can be planarly striped, but the vertical first conductivity type region and the vertical shape The second conductivity type region may not be layered, but at least one may be columnar and may be arranged at a three-dimensional lattice point such as a three-dimensional lattice or a three-dimensional tetragonal lattice. Since the ratio of the pn junction area per unit volume is increased, the breakdown voltage is improved. The first conductivity type region and the vertical second conductivity type region may each be a continuous diffusion region having a uniform impurity distribution, but at least one of the vertical first conductivity type region and the vertical second conductivity type region is in the thickness direction of the substrate. It is desirable to have an associative structure in which a plurality of diffusion unit regions embedded discretely are interconnected. This is because it becomes easier to form the vertical parallel pn structure itself. In such a case, each diffusion unit region has a concentration distribution in which the concentration is gradually decreased outward with the central portion being the maximum concentration portion.
[0024]
The first means is applied to a vertical active element having three or more terminals because the third electrode layer is an on / off control electrode layer. The second means is a two-terminal vertical passive element. It can also be applied to elements.
[0025]
That is, regardless of the presence or absence of the third electrode layer in the first means, the second means includes at least the peripheral portion of the first electrode layer in the first parallel pn structure or the second parallel pn structure. The pn repetition pitch of the parallel pn structure in the portion immediately below is narrower than the pn repetition pitch of the first parallel pn structure. The peripheral portion of the first electrode layer generally functions as a field plate.
[0026]
According to such means, it is possible to improve the breakdown voltage at the portion immediately below the peripheral edge of the first electrode layer, and to improve the dynamic avalanche breakdown resistance. It is desirable that the impurity concentration of the parallel pn structure in the portion immediately below is lower than the impurity concentration of the first parallel pn structure.
[0027]
Further, it is desirable that the first main surface side of the parallel pn structure directly below the first pn structure is covered with a second conductivity type well region conductively connected to the first electrode layer. This is because the portion immediately below it can be reliably set to a reverse bias at the time of OFF, and in the event that a dynamic avalanche breakdown occurs in the portion immediately below, the second conductivity type well region that functions as a carrier extraction is provided. Thus, carriers can be extracted to the first electrode layer, and element destruction can be prevented.
[0028]
In the first parallel pn structure, it is desirable that the outermost vertical second conductivity type region adjacent to the parallel pn structure in the immediately lower portion is connected to the well end of the second conductivity type well region. Since the pn junction between the outermost vertical first conductivity type region and the outermost vertical second conductivity type region of the parallel pn structure directly below is connected to the second conductivity type well region, the dynamic avalanche break Down is less likely to occur. In addition, charge balance can be achieved.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following, layers and regions with n or p are used to mean layers or regions having electrons or holes as majority carriers. Superscript + means a relatively high impurity concentration and superscript-means a relatively low impurity concentration.
[0030]
[Example 1]
FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET element according to the first embodiment of the present invention, in which the surface active portion of the MOSFET, the source electrode layer on the insulating film, and the gate extraction electrode are omitted. FIG. 2 is an enlarged plan view showing the rectangular range A1-A2-A3-A4 in FIG. 3 is a cross-sectional view showing a state cut along line A5-A6 in FIG.
[0031]
The n-channel vertical MOSFET of this example has a low resistance n-type in which the drain electrode 18 on the back side is in conductive contact. ++ A drain / drift portion 1 having a first parallel pn structure formed on a drain layer (drain / contact layer) 11 and selectively formed as an annular or striped cell on the surface side of the drift portion 1 A high impurity concentration p base region (p well) 13 and an impurity high concentration n selectively formed on the surface side in the p base region 13 + The source region 14, the gate electrode layer 16 such as polysilicon provided on the substrate surface via the gate insulating film 15, and the p base region 13 via the contact hole opened in the interlayer insulating film 20 + Contact regions 19 and n + The source electrode 17 is in conductive contact with both of the source regions 14. N in the well-shaped p base region 13 + The source region 14 is formed shallow and constitutes a double diffusion type MOS portion. Here, the surface active portion of this element corresponds to the p base region 13 and the source region 14.
[0032]
The drain / drift unit 1 has n ++ The n-type epitaxial growth layer is formed on the substrate of the drain layer 11 as a thick stacked layer, and a layered vertical n-type drift circuit region 1a in the thickness direction of the substrate and a layered vertical shape in the thickness direction of the substrate. The p-type partition region 1b is alternately and repeatedly joined. In this example, the n-type drift circuit region 1a is located between the well end portions of the adjacent p base regions 13, the upper end thereof reaches the channel region 12e on the substrate surface, and the lower end thereof is n ++ It is in contact with the drain layer 11. The p-type partition region 1b has an upper end that is in contact with the well bottom except for both ends of the p base region 13a, and a lower end that is n. ++ It is in contact with the drain layer 11. In this example, the withstand voltage is 600V class, and both the drift electric circuit region 1a and the p-type partition region 1b have a thickness of 8 μm and a depth of about 40 μm. Each impurity concentration is 2.5 × 10 15 cm -3 But 1 × 10 15 ~ 3x10 15 If it is good.
[0033]
As shown in FIG. 1, the substrate surface and n around the drift portion 1 that occupies the chip plane mainly. ++ Between the drain layer 11 is formed a breakdown voltage structure portion (element outer peripheral portion) 2 that is a non-electric circuit region in the on state and is depleted in the off state. The breakdown voltage structure 2 is formed by alternately joining a layered vertical n-type region 2a oriented in the thickness direction of the substrate and a layered vertical p-type region 2b oriented in the thickness direction of the substrate alternately. It has a second parallel pn structure. The first parallel pn structure of the drift portion 1 and the second parallel pn structure of the breakdown voltage structure portion 2 are arranged in parallel. That is, the layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the second parallel pn structure of the breakdown voltage structure portion 2 are parallel to each other, and at the boundary portion thereof, regions of opposite conductivity type are obtained. The repetition is continuous. As shown in FIG. 2, the pn repeat end face in the second parallel pn structure of the breakdown voltage structure portion 2 and the pn repeat end face in the second parallel pn structure of the drift portion 1 are connected. In this example, the pn repetition pitch in the second parallel pn structure of the breakdown voltage structure portion 2 is narrower than the pn repetition pitch in the first parallel pn structure of the drift portion 1. Further, the impurity concentration of the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. The vertical n-type region 2a and the vertical p-type region 2b both have a layer thickness of 4 μm and a depth of about 40 μm. Each impurity concentration is 2.5 × 10 13 cm -3 But 2 × 10 14 cm -3 The following is acceptable. An oxide film (insulating film) 23 made of a thermal oxide film or phosphor silica glass (PSG) is formed on the surface of the pressure-resistant structure portion 2 for surface protection and stabilization.
[0034]
Outside the breakdown voltage structure 2, an n-type channel stopper region 24 having a relatively thick layer thickness is arranged in the substrate thickness direction. The n-type channel stopper region 24 is n + The contact region 25 is electrically connected to the peripheral electrode 26 having the same potential as the drain voltage.
[0035]
The drift portion 1 occupies a rectangular area on the chip plane, and the gate extraction electrode 30 is located on the interlayer insulating film 20 in the middle of one side. Around the gate extraction electrode 30, a source electrode layer 17 projects as a field plate 17a. The portion directly below the gate extraction electrode 30 and sandwiched between the first parallel pn structure of the drift portion 1 and the second parallel pn structure of the breakdown voltage structure portion 2 has a third parallel pn structure. In the third parallel pn structure, a layered vertical n-type region 3a oriented in the thickness direction of the substrate and a layered vertical p-type region 3b oriented in the thickness direction of the substrate are alternately and repeatedly joined. It consists of The first parallel pn structure of the drift portion 1 and the third parallel pn structure of the immediately lower portion 3 are arranged in parallel. That is, the layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the immediately lower portion 3 are in parallel with each other, and at the boundary portion thereof, regions of opposite conductivity type are obtained. The repetition is continuous. Further, the layer surface of the second parallel pn structure of the breakdown voltage structure portion 2 and the layer surface of the third parallel pn structure of the portion 3 immediately below are in parallel with each other, and the boundary portions thereof are regions of opposite conductivity type. The pn repetition is continuous.
[0036]
In this example, the pn repetition pitch in the third parallel pn structure of the immediately lower portion 3 is narrower than the pn repetition pitch in the first parallel pn structure of the drift portion 1, and the second parallel pn of the breakdown voltage structure portion 2. Same as the pn repeat pitch in the structure. The impurity concentration of the third parallel pn structure in the immediately lower portion 3 is lower than the impurity concentration of the drift portion 1 and is the same as the impurity concentration of the second parallel pn structure of the breakdown voltage structure portion 2. Both the n-type region 3a and the p-type region 3b have a layer thickness of 4 μm and a depth of about 40 μm. Each impurity concentration is 2.5 × 10 13 cm -3 But 2 × 10 14 cm -3 The following is acceptable.
[0037]
The surface side of the third parallel pn structure in the immediately lower portion 3 is covered with a p-type well region 40, and the p-type well region 40 is formed in the p-type well region 40. + The contact region 41 is electrically connected to the contact region. The third parallel pn structure in the immediately lower portion 3 is connected to the well bottom excluding the well end of the p-type well region 40. The vertical partition region 1b at the extreme end of the drift portion 1 is connected to the well bottom near the inner well end of the p-type well region 40, and the pn junction J with the n-type region 3a in the immediately lower portion 3 is the p-type region 40 Connected to the bottom of the well. The outermost p-type region 2b of the breakdown voltage structure 2 is connected to the p-type well region 40 near the outer well end.
[0038]
The parallel pn structure is an association structure in which at least one of the vertical p-type region and the vertical n-type region is formed by interconnecting a plurality of diffusion unit regions discretely embedded in the thickness direction of the substrate. Is desirable. This is because it becomes easier to form the parallel pn structure itself. In such a case, each diffusion unit region has a concentration distribution in which the concentration is gradually decreased outward with the central portion being the maximum concentration portion.
[0039]
Next, the operation of this example will be described. When a predetermined positive potential is applied to the gate electrode layer 16, the n-channel MOSFET is turned on, and the channel is formed from the source region 14 through the inversion layer induced on the surface of the p base region 13 immediately below the gate electrode layer 16. Electrons are injected into the region 12e, and the injected electrons pass through the drift circuit region 1a and n ++ The drain layer 11 is reached, and the drain electrode 18 and the source electrode 17 are electrically connected.
[0040]
When the positive potential to the gate electrode layer 16 is removed, the MOSFET is turned off, the inversion layer induced on the surface of the p base region 13 disappears, and the drain electrode 18 and the source electrode 17 are blocked. Further, when the reverse bias voltage (source-drain voltage) is large in the off state, a depletion layer is formed in the p base region 13 and the channel region 12e from the pn junction between the p base region 13 and the channel region 12e, respectively. While expanding and depleting, each partition region 1b of the drift portion 1 is electrically connected to the source electrode 17 via the p base region 13, and each drift electric circuit region 1a of the drift portion 1 is n ++ Since it is electrically connected to the drain electrode 18 via the drain layer 11, the depletion layer from the pn junction between the partition region 1b and the drift circuit region 1a extends to both the partition region 1b and the drift circuit region 1a. As a result, depletion of the drift portion 1 is accelerated. Therefore, since the high withstand voltage of the drift portion 1 is sufficiently secured, the impurity concentration of the drift portion 1 can be set high, and a large current capacity can be secured.
[0041]
Here, the second parallel pn structure is formed in the breakdown voltage structure portion 2 around the drift portion 1 of this example. In this second parallel pn structure, several p-type regions 2b are electrically connected to the source electrode 17 through the p base region 13 or the p-type region 40, and each n-type region 20a is n ++ Since it is electrically connected to the drain electrode 18 via the drain layer 11, the depletion layer extended from the pn junction of the breakdown voltage structure portion 2 is generally depleted over the entire thickness of the substrate. For this reason, not only can the surface side of the pressure-resistant structure portion 2 be depleted like the surface guard ring structure or the field plate structure, but also the outer peripheral portion and the substrate deep portion can be depleted. Strength can be greatly relaxed and high withstand voltage can be secured. Therefore, a high breakdown voltage of the super junction semiconductor element can be realized.
[0042]
In particular, in this example, the second parallel pn structure of the breakdown voltage structure portion 2 has a narrower pn repetition pitch and a lower impurity amount (impurity concentration) than the first parallel pn structure of the drift portion 1. The breakdown voltage structure portion 2 is depleted earlier than the drift portion 1, so that the breakdown voltage reliability is high. Since the pn repeating end face of the withstand voltage structure portion 2 is connected to the pn repeating end face of the drift portion 1, the depletion rate of the withstand voltage structure portion 2 is high. Therefore, even in the superjunction semiconductor element adopting the first parallel pn structure in the drift portion 1, the breakdown voltage of the surrounding breakdown voltage structure portion 2 is sufficiently guaranteed by the second parallel pn structure. The optimization of the first parallel pn structure of the drift portion 1 is easy, the degree of freedom in designing the superjunction semiconductor element is increased, and the superjunction semiconductor element can be put into practical use.
[0043]
In this example, the third parallel pn structure in the portion 3 immediately below the gate extraction electrode 30 has a narrower pn repetition pitch and a lower impurity concentration than the first parallel pn structure of the drift portion 1. Compared with the drift portion 1, the depletion layer per unit area is likely to expand in the portion 3 immediately below the extraction electrode 30, and the device breakdown voltage is not determined by the portion 3 directly below. In particular, since the third parallel pn structure of the immediately lower portion 3 has a pn repetition pitch narrower than that of the first parallel pn structure of the drift portion 1, any p-type region 3 b of the immediately lower portion 3 is p-type of the drift portion 1. Since the connection is made along the depth direction of the partition region 1b, the potential floating state is not caused, and depletion of the immediately lower portion 3 can be guaranteed. In other words, in the case where the first parallel pn structure of the drift portion 1 and the third parallel pn structure of the immediately lower portion 3 are in phase parallel to each other, even if the p-type region 40 does not exist, the source potential Is conductive to any p-type region 3b of the immediately lower portion 3, the pn repetition pitch of the third parallel pn structure of the immediately lower portion 3 is narrower than the pn repetition pitch of the first parallel pn structure of the drift portion 1. It is desirable to do. In addition, the expansion of the depletion layer in the immediately lower portion 3 is earlier than that of the drift portion 1 at the time of interruption, so that the electric field strength can be relaxed and carriers are locked out to the drift portion 1 side, so that a dynamic avalanche breakdown occurs in the immediately lower portion 3 Therefore, it is possible to secure a stable breakdown voltage and to obtain a high dynamic avalanche breakdown resistance.
[0044]
Further, since the p-type region 40 electrically connected to the source electrode 17 exists on the surface side of the third parallel pn structure, each p-type region 2b of the third parallel pn structure is reliably reverse-biased when turned off. As a result, the depletion layer easily expands in the depth direction from the pn junction of the p-type region 2b, and a high breakdown voltage is obtained in the portion 3 immediately below, so that a more dynamic avalanche breakdown is less likely to occur. it can. In addition, if a dynamic avalanche breakdown occurs in the portion 3 immediately below, the generated excess holes are extracted to the source electrode 17 through the p-type region 40, so that element destruction due to heat generation or the like is not caused. .
[0045]
Since the third parallel pn structure in the immediately lower portion 3 is connected to the well bottom except for the well end of the p-type well region 40, the entire third parallel pn structure can be depleted evenly. Further, the vertical partition region 1b at the extreme end of the drift portion 1 is connected to the well bottom near the inner well end of the p-type well region 40, and the pn junction J with the n-type region 3a in the immediately lower portion 3 is a p-type well. Connected to the well bottom of region 40. For this reason, electric field concentration is likely to occur at the inner well end, and dynamic avalanche breakdown is likely to occur. However, the occurrence can be locked out to the drift portion 1, and the end of the adjacent third parallel pn structure can be prevented. It is possible to balance the charge with the n-type region 3b.
[0046]
Note that the n-type regions 1a to 3a and the p-type regions 1b to 3b of the parallel pn structures 1 to 3 are formed in a planar stripe shape as shown in FIG. 2, but as shown in FIG. In the n-type regions 1a 'to 3a', p-type regions 1b 'to 3b' may be formed in a planar lattice shape. The p-type regions 1b ′ to 3b ′ are columnar in the depth direction of the substrate. Each of the p-type regions 1b 'to 3b' has an association structure in which a plurality of diffusion unit regions discretely embedded in the thickness direction of the substrate are interconnected, and each diffusion unit region has a maximum concentration portion at the center. And has a concentration distribution in which the concentration gradually decreases in the outward direction. Of course, the n-type region may be formed in a planar lattice pattern in the p-type region as the ground.
[0047]
In addition, when changing a pressure | voltage resistant class, what is necessary is just to change the length of the depth direction of each parallel pn structure to the length according to the pressure | voltage resistant class. For example, in the case of 900V class, it may be about 60 μm. Further, in the second and third parallel pn structures, the pitch is narrowed and the impurity concentration is lowered. However, even if the pitch is the same, only the concentration needs to be lowered. The impurity concentration of the second and third parallel pn structures is preferably about 1/5 to 1/100 of the impurity concentration of the first parallel pn structure.
[0048]
[Example 2]
FIG. 5 is an enlarged plan view showing the upper left range of the chip in the vertical MOSFET according to Embodiment 2 of the present invention, and corresponds to the rectangular range A1-A2-A3-A4 in FIG. ing.
[0049]
The structural difference between the first embodiment and the first embodiment is that the second parallel pn structure of the breakdown voltage structure portion 2 and the third parallel pn structure of the immediately lower portion 3 are orthogonal to the first parallel pn structure of the drift portion 1. Is being placed. That is, the layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the portion 3 directly below are orthogonal to each other, and the layer surface of the first parallel pn structure of the drift portion 1 and the breakdown voltage structure portion 2 Are parallel to the layer surface of the second parallel pn structure. Compared to the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the immediately lower portion 3 and the breakdown voltage structure portion 2 is narrower and is about half. Further, the impurity concentration of the immediately lower portion 3 and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. In FIG. 5, the repetitive end face of the third parallel pn structure in the immediately lower portion 3 is connected to the p-type partition region 1 bb of the drift portion 1. Therefore, in the case where the first parallel pn structure of the drift portion 1 and the third parallel pn structure of the immediately lower portion 3 are orthogonal to each other, even if the p-type well region 40 does not exist, the immediately lower portion 3 and the drift line 1, the source potential can be conducted to any p-type region 3b of the directly lower portion 3 even when the p-type region 40 is not present. It is not essential that the pn repetition pitch in 3 is narrower than the pn repetition pitch in the drift portion 1.
[0050]
Even with such an arrangement relationship of the three parallel pn structures, the same effects as those of the first embodiment can be obtained.
[0051]
Example 3
FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 3 of the present invention, in which the MOSFET surface activation part, the source electrode layer on the insulating film, and the gate extraction electrode are omitted. FIG. 7 is an enlarged plan view showing the rectangular range B1-B2-B3-B4 in FIG. A cross-sectional view showing a state cut along line B5-B6 in FIG. 7 is the same as FIG.
[0052]
The third parallel pn structure of the portion 3 immediately below the gate extraction electrode in this example is located at the corner portion of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the immediately lower portion 3 are in parallel with each other. The layer surface of the second parallel pn structure is parallel to the layer surface. Compared to the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the immediately lower portion 3 and the breakdown voltage structure portion 2 is narrower and is about half. Further, the impurity concentration of the immediately lower portion 3 and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. In particular, since the third parallel pn structure of the immediately lower portion 3 has a pn repetition pitch narrower than that of the first parallel pn structure of the drift portion 1, any of the immediately lower portions 3 can be obtained even when the p-type well region 40 is not present. Since the p-type region 3 b is also connected along the depth direction of the p-type partition region 1 b of the drift portion 1, the potential floating state is not achieved, and depletion of the directly lower portion 3 can be guaranteed.
[0053]
Thus, even when the portion 3 directly below the gate extraction electrode is located at the corner portion of the drift portion 1, the same effects as those of the first embodiment can be obtained.
[0054]
Example 4
FIG. 8 is an enlarged plan view showing the upper left range of the chip in the vertical MOSFET according to the fourth embodiment of the present invention, and corresponds to the rectangular range B1-B2-B3-B4 in FIG. 6 like FIG. ing.
[0055]
In this example, as in the third embodiment, the third parallel pn structure of the portion 3 immediately below the gate extraction electrode is located at the corner of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure and the layer surface of the third parallel pn structure of the portion 3 directly below are orthogonal to each other, and the layer surface of the first parallel pn structure of the drift portion 1 and the second surface of the breakdown voltage structure portion 2 It is orthogonal to the layer surface of the parallel pn structure. Compared to the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the immediately lower portion 3 and the breakdown voltage structure portion 2 is narrower and is about half. Further, the impurity concentration of the immediately lower portion 3 and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1.
[0056]
Thus, even when the portion 3 directly below the gate extraction electrode is located at the corner portion of the drift portion 1, the same effects as those of the first embodiment can be obtained. In order to avoid electric field concentration as much as possible in the corner portion, the boundary line between the drift portion 1 and the immediately lower portion 3 is connected by a curve, so that the pn repeating end face of the third parallel pn structure in the immediately lower portion 3 is It is difficult to connect to one p-type partition region. Rather, depending on the curvature of the curve, if the pn repetition pitch in the immediately lower portion 3 is made wider than the pn repetition pitch in the drift portion 1, the source potential is reduced to the immediately lower portion even when the p-type well region 40 is not present. 3 can be conducted to any p-type region 3b.
[0057]
Example 5
FIG. 9 is a schematic plan view showing the chip of the vertical MOSFET device according to the fifth embodiment of the present invention, in which the MOSFET surface activation portion, the source electrode layer on the insulating film, and the gate extraction electrode are omitted. FIG. 10 is an enlarged plan view showing the rectangular range C1-C2-C3-C4 in FIG. 11 is a cross-sectional view showing a state cut along line C5-C6 in FIG.
[0058]
The third parallel pn structure of the portion 3 immediately below the gate extraction electrode 30 in this example is located at the center of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the immediately lower portion 3 are in parallel with each other. The layer surface of the second parallel pn structure is parallel to the layer surface. Compared to the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the immediately lower portion 3 and the breakdown voltage structure portion 2 is narrower and is about half. Further, the impurity concentration of the immediately lower portion 3 and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. Since the pn repetition pitch of the third parallel pn structure of the immediately lower portion 3 is narrower than that of the first parallel pn structure of the drift portion 1, any p-type of the immediately lower portion 3 can be obtained even when the p-type well region 40 is not present. Since the region 3b is also connected along the depth direction of the p-type partition region 1b of the drift portion 1, it does not become a potential floating state, and depletion of the portion 3 immediately below can be guaranteed.
[0059]
In this example, since the gate extraction electrode 30 is located in a region surrounded by the inner peripheral field plate 17b and not the outer peripheral field plate 17a of the source electrode layer 17, the third parallel pn structure of the immediately lower portion 3 is p. In addition to being covered by the mold region 40, the second parallel pn structure in the portion immediately below the outer peripheral field plate 17a is covered by the p-type well region 50, and the p-type well region 50 is conductively connected to the source electrode. + A contact region 51 is formed. It is possible to accelerate the depletion in the portion directly below the outer peripheral field plate 17a, and to secure the dynamic avalanche breakdown capability. Further, since the outermost partition region 1b of the first parallel pn structure is connected to the well bottom of the p-type well region 50, the charge balance with the outermost n-type region 2a of the adjacent second parallel pn structure Can be taken.
[0060]
Example 6
FIG. 12 is an enlarged plan view showing the upper left range of the chip in the vertical MOSFET according to the fourth embodiment of the present invention. Similar to FIG. 10, this corresponds to the rectangular range C1-C2-C3-C4 in FIG.
[0061]
In this example, as in the fifth embodiment, the third parallel pn structure of the portion 3 immediately below the gate extraction electrode is located in the center of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure and the layer surface of the third parallel pn structure of the portion 3 directly below are orthogonal to each other, and the layer surface of the first parallel pn structure of the drift portion 1 and the second surface of the breakdown voltage structure portion 2 It is orthogonal to the layer surface of the parallel pn structure. Compared to the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the immediately lower portion 3 and the breakdown voltage structure portion 2 is narrower and is about half. Further, the impurity concentration of the immediately lower portion 3 and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1.
[0062]
Since the pn repeating end face of the third parallel pn structure in the immediately lower portion 3 is connected to one p-type partition region, even if the p-type well region 40 does not exist, the source potential of any p-type in the immediately lower portion 3 is changed. It becomes possible to conduct to the region 3b. Even when the portion 3 directly below the gate extraction electrode is located at the corner portion of the drift portion 1, the same effects as those of the fifth embodiment can be obtained.
[0063]
In each of the above embodiments, a double diffusion type vertical MOSFET has been described. However, the present invention is not limited to a vertical active element having three terminals or more such as an IGBT (conductivity modulation type MOSFET) or a bipolar transistor. It can be applied to passive elements.
[0064]
【The invention's effect】
As described above, according to the present invention, the breakdown voltage structure around the drift portion has the parallel pn structure, and the portion immediately below the third electrode layer and the portion directly below the peripheral edge of the first electrode layer also have the parallel pn structure. However, since the pn repetition pitch of the portion immediately below is narrower than that of the drift portion, or the impurity concentration of the portion immediately below is lower than that of the drift portion, There are effects like this.
[0065]
(1) Since the parallel pn structure is arranged around the drift part, in the off state, the depletion layer expands from the multiple pn junction surfaces, and is not limited to the vicinity of the active part, but the outward direction or the second main surface side Therefore, the breakdown voltage of the breakdown voltage structure portion is larger than the breakdown voltage of the drift portion. Accordingly, even in a superjunction semiconductor element that employs a vertical parallel pn structure in the drift portion, the withstand voltage of the withstand voltage structure portion is sufficiently ensured, so that the parallel pn structure of the drift portion can be easily optimized. The design flexibility of the superjunction semiconductor element is increased, and the superjunction semiconductor element can be put into practical use. When the parallel pn structure of the breakdown voltage structure portion has a smaller amount of impurities than the parallel pn structure of the drift portion, or when the parallel pn structure of the breakdown voltage structure portion has a smaller pn repetition pitch than the parallel pn structure of the drift portion, The withstand voltage can be surely made larger than the withstand voltage of the drift portion, and reliability is improved.
[0066]
(2) The portion immediately below the third electrode layer or the portion immediately below the peripheral edge of the first electrode layer also has a parallel pn structure, and the pn repetition pitch is narrower than the pn repetition pitch of the drift portion. In the portion, the depletion layer per unit area is likely to expand as compared with the drift portion, and is not determined in the portion immediately below. In addition, at the moment of interruption, the depletion layer expands immediately below the drift part earlier than the drift part, and the electric field strength can be relaxed. Carriers are locked out to the drift part side, so dynamic avalanche breakdown is unlikely to occur immediately below the part. Become. Therefore, the dynamic avalanche breakdown occurs in the drift part, and the dynamic avalanche breakdown can be suppressed in the portion immediately below, so that a stable breakdown voltage can be secured and a high dynamic avalanche breakdown resistance can be obtained. be able to. A similar effect can be obtained even when the impurity concentration in the portion immediately below is lower than that in the drift portion.
[0067]
(3) In the configuration in which the first main surface side of the immediately lower portion is covered with a second conductivity type well region that is conductively connected to the first electrode layer, each vertical second conductivity type region of the third parallel pn structure is turned off when off. The reverse bias is surely established, and the depletion layer is likely to extend in the depth direction from the pn junction of the second conductivity type region, and the high breakdown voltage is provided directly under the third electrode layer, so that further dynamic avalanche breakdown occurs. Since it becomes difficult, the avalanche resistance can be improved. In addition, if a dynamic avalanche breakdown occurs in the portion immediately below the third electrode layer, it is extracted to the first electrode layer through the second conductivity type well region that functions as a carrier extraction, and therefore, due to heat generation or the like. Does not cause device destruction.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET element according to Embodiment 1 of the present invention.
2 is an enlarged plan view showing a rectangular range A1-A2-A3-A4 in FIG.
3 is a cross-sectional view showing a state cut along the line A5-A6 in FIG. 2;
4 is a plan view showing a modification of the parallel pn structure in Embodiment 1. FIG.
FIG. 5 is an enlarged plan view showing an upper left range of a chip in a vertical MOSFET according to Embodiment 2 of the present invention.
FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET element according to Example 3 of the invention.
7 is an enlarged plan view showing a rectangular range B1-B2-B3-B4 in FIG. 6;
FIG. 8 is an enlarged plan view showing an upper left range of a chip in a vertical MOSFET according to a fourth embodiment of the invention.
FIG. 9 is a schematic plan view showing a chip of a vertical MOSFET element according to a fifth embodiment of the invention.
10 is an enlarged plan view showing a rectangular range C1-C2-C3-C4 in FIG. 9;
11 is a cross-sectional view showing a state cut along line C5-C6 in FIG.
FIG. 12 is an enlarged plan view showing an upper left range of a chip in a vertical MOSFET according to the sixth embodiment of the present invention.
FIG. 13 is a partial cross-sectional view showing a conventional vertical MOSFET having a single conductivity type drift layer.
FIG. 14 is a partial cross-sectional view showing a vertical MOSFET having a drift layer having a conventional parallel pn structure.
[Explanation of symbols]
1 ... Drain / drift section
1a, 1a '... n-type drift circuit region
1b, 1b '... p-type partition region
2 ... Pressure resistant structure
2a, 2a ', 3a, 3a' ... vertical n-type region
2b, 2b ', 3b, 3b' ... vertical p-type region
3 ... Directly under the gate extraction electrode
11 ... n + Drain layer
12e ... channel region
13 ... High impurity concentration p base region (p well)
14 ... n + Source area
15 ... Gate insulating film
16 ... Gate electrode layer
17 ... Source electrode
17a, 17b ... Field plate
18 ... Drain electrode
19, 21, 51 ... p + Contact area
20 ... Interlayer insulating film
24 ... n-type channel stopper region
25 ... n + Contact area
26 ... peripheral electrode
30 ... Gate extraction electrode
40, 50 ... p-type well region
J ... pn junction

Claims (21)

基板の第１主面側に形成された活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記第１主面に絶縁膜を介して形成されており、前記第１電極層に少なくとも一部が近接して成り、オン・オフ制御用の各第３電極層を共通接続して取り出すための取り出し電極とを有し、前記縦形ドリフト部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第１の並列ｐｎ構造となった半導体装置において、
前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造であり、
前記取り出し電極の直下部分が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第３の並列ｐｎ構造であり、前記第３の並列ｐｎ構造のｐｎ繰り返しピッチが前記第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭く、前記第３の並列ｐｎ構造の不純物濃度が前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。A first electrode layer that is conductively connected to the active portion formed on the first main surface side of the substrate, and a second electrode that is conductively connected to the low-resistance layer of the first conductivity type formed on the second main surface side of the substrate. An electrode layer, a vertical drift portion interposed between the active portion and the low-resistance layer, allowing a drift current to flow in the vertical direction in the on state and depleting in the off state, and an insulating film on the first main surface the are formed through, having at least partially Ri formed in close proximity, and the extraction electrode for extracting commonly connecting the third electrode layer for on-off control on the first electrode layer, A first parallel pn structure in which the vertical drift portion is formed by alternately and repeatedly joining a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. In the semiconductor device that became
A breakdown voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, which is a non- electric path region in the on state and is depleted in the off state, is a thickness direction of the substrate A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductive type region oriented in a vertical direction and a vertical second conductive type region oriented in the thickness direction of the substrate,
A third portion is formed by joining a portion immediately below the take-out electrode alternately and repeatedly with a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. parallel pn a structure, the third parallel pn repetition pitch of the pn structure the first parallel rather narrower than pn repetition pitch of the pn structure, the third parallel impurity concentration of said first parallel pn structure wherein a lower than the impurity concentration of the pn structure. 基板の第１主面側に形成された活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部と、前記１主面に絶縁膜を介して形成されており、前記第１電極層に少なくとも一部が囲まれて成り、オン・オフ制御用の各第３電極層を共通接続して取り出すための取り出し電極とを有し、前記縦形ドリフト部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第１の並列ｐｎ構造となった半導体装置において、
前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造であり、
前記取り出し電極の直下部分が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第３の並列ｐｎ構造であり、前記第３の並列ｐｎ構造の不純物濃度が前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。A first electrode layer that is conductively connected to the active portion formed on the first main surface side of the substrate, and a second electrode that is conductively connected to the low-resistance layer of the first conductivity type formed on the second main surface side of the substrate. A vertical drift portion that is interposed between the active portion and the low-resistance layer, allows a drift current to flow in the vertical direction in the on state and is depleted in the off state, and an insulating film on the one main surface. through are formed, the Ri formed by at least partially surrounded by the first electrode layer, and an extraction electrode for extracting commonly connecting the third electrode layer for on-off control, the A first parallel pn structure in which a vertical first conductivity type region having a vertical drift portion oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate are alternately and repeatedly joined; In the semiconductor device
A breakdown voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, which is a non- electric path region in the on state and is depleted in the off state, is a thickness direction of the substrate A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductive type region oriented in a vertical direction and a vertical second conductive type region oriented in the thickness direction of the substrate,
A third portion is formed by joining a portion immediately below the take-out electrode alternately and repeatedly with a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. parallel pn is a structure, wherein a impurity concentration of the third parallel pn structure is lower than the impurity concentration of said first parallel pn structure. 請求項１又は請求項２において、前記第２の並列ｐｎ構造のｐｎ繰り返しピッチは前記第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭いことを特徴とする半導体装置。According to claim 1 or claim 2, pn repetition pitch of said second parallel pn structure wherein a narrower than pn repetition pitch of said first parallel pn structure. 請求項１乃至請求項３のいずれか一項において、前記第２の並列ｐｎ構造の不純物濃度は前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。In any one of claims 1 to 3, the impurity concentration of said second parallel pn structure wherein a lower than the impurity concentration of said first parallel pn structure. 請求項１乃至請求項４のいずれか一項において、前記第３の並列ｐｎ構造の第１主面側が前記第１電極層に導電接続する第２導電型ウェル領域で覆われて成ることを特徴とする半導体装置。In any one of claims 1 to 4, characterized in that it comprises covered with the third second-conductivity-type well region in which the first main surface side of the parallel pn structure is conductively connected to the first electrode layer the semiconductor device according to. 請求項５において、前記第３の並列ｐｎ構造の第１主面側は前記第２導電型領域のウェル両端部を除くウェル底に接続していることを特徴とする半導体装置。In claim 5, the first main surface side of said third parallel pn structure wherein a connecting to the well bottom, except for wells both end portions of the second conductivity type region. 請求項１乃至請求項６のいずれか一項において、前記第１の並列ｐｎ構造と前記第２の並列ｐｎ構造とは層面が相平行して配置されていることを特徴とする半導体装置。In the claims 1 to any one of claims 6, wherein a said first parallel pn structure and the layer surface and the second parallel pn structure is arranged in parallel phases. 請求項１乃至請求項６のいずれか一項において、前記第１の並列ｐｎ構造と前記第２の並列ｐｎ構造とは層面が相直交して配置されていることを特徴とする半導体装置。In the claims 1 to any one of claims 6, wherein a said first parallel pn structure and the layer surface and the second parallel pn structure is arranged to phase quadrature. 請求項１乃至請求項６のいずれか一項において、前記第１の並列ｐｎ構造と前記第３の並列ｐｎ構造とは層面が相平行して配置されていることを特徴とする半導体装置。In the claims 1 to any one of claims 6, wherein a the layer surface are arranged in parallel phase and wherein the first parallel pn structure third parallel pn structure. 請求項１乃至請求項６のいずれか一項において、前記第１の並列ｐｎ構造と前記第３の並列ｐｎ構造とは層面が相直交して配置されていることを特徴とする半導体装置。In the claims 1 to any one of claims 6, wherein a the layer surface are arranged mutually orthogonal to said first parallel pn structure third parallel pn structure. 請求項１乃至請求項１０のいずれか一項において、前記第１、第２及び第３の並列ｐｎ構造を構成する縦形第１導電型領域と縦形第２導電型領域とは、平面的にストライプ状であることを特徴とする半導体装置。In any one of claims 1 to 10, wherein the first, second and third parallel pn structure constituting the vertical first conductivity type region and a vertical second conductivity type region is planarly stripes A semiconductor device characterized by having a shape. 基板の第１主面側に形成された活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部とを有し、前記縦形ドリフト部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型とを交互に繰り返して接合して成る第１の並列ｐｎ構造となった半導体装置において、
前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造であり、
前記第１の並列ｐｎ構造又は前記第２の並列ｐｎ構造のうち、前記各第１の電極層を共有接続してフィールドプレートに延長している部分の直下部分における並列ｐｎ構造のｐｎ繰り返しピッチが前記第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭く、前記直下部分における並列ｐｎ構造の不純物濃度が前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。A first electrode layer that is conductively connected to the active portion formed on the first main surface side of the substrate, and a second electrode that is conductively connected to the low-resistance layer of the first conductivity type formed on the second main surface side of the substrate. A vertical drift portion that is interposed between the active portion and the low-resistance layer, flows a drift current in the vertical direction in the on state, and depletes in the off state, and the vertical drift portion is In a semiconductor device having a first parallel pn structure in which a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type oriented in the thickness direction of the substrate are alternately and repeatedly joined. ,
A breakdown voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, which is a non- electric path region in the on state and is depleted in the off state, is a thickness direction of the substrate A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductive type region oriented in a vertical direction and a vertical second conductive type region oriented in the thickness direction of the substrate,
Among the first parallel pn structure or the second parallel pn structure, before Symbol pn repetition pitch of the parallel pn structure in the portion immediately below the portion that extends to the field plates share connect each first electrode layer There wherein a first narrower than pn repetition pitch of the parallel pn structure, the impurity concentration of the parallel pn structure in the portion immediately under that lower than the impurity concentration of said first parallel pn structure. 基板の第１主面側に形成された活性部に導電接続する第１の電極層と、前記基板の第２主面側に形成された第１導電型の低抵抗層に導電接続する第２の電極層と、前記活性部と前記低抵抗層との間に介在し、オン状態ではドリフト電流を縦方向に流すと共にオフ状態では空乏化する縦形ドリフト部とを有し、前記縦形ドリフト部が前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型とを交互に繰り返して接合して成る第１の並列ｐｎ構造となった半導体装置において、
前記縦形ドリフト部の周りで前記第１主面と前記低抵抗層との間に介在し、オン状態では非電路領域であってオフ状態では空乏化する耐圧構造部が、前記基板の厚み方向に配向する縦形第１導電型領域と前記基板の厚み方向に配向する縦形第２導電型領域とを交互に繰り返して接合して成る第２の並列ｐｎ構造であり、
前記第１の並列ｐｎ構造又は前記第２の並列ｐｎ構造のうち、前記各第１の電極層を共有接続してフィールドプレートに延長している部分の直下部分における並列ｐｎ構造の不純物濃度が前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。A first electrode layer that is conductively connected to the active portion formed on the first main surface side of the substrate, and a second electrode that is conductively connected to the low-resistance layer of the first conductivity type formed on the second main surface side of the substrate. A vertical drift portion that is interposed between the active portion and the low-resistance layer, flows a drift current in the vertical direction in the on state, and depletes in the off state, and the vertical drift portion is In a semiconductor device having a first parallel pn structure in which a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type oriented in the thickness direction of the substrate are alternately and repeatedly joined. ,
A breakdown voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, which is a non- electric path region in the on state and is depleted in the off state, is a thickness direction of the substrate A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductive type region oriented in a vertical direction and a vertical second conductive type region oriented in the thickness direction of the substrate,
Among the first parallel pn structure or the second parallel pn structure, the previous SL impurity concentration of the parallel pn structure in the portion immediately below the portion that extends to the field plates share connect each first electrode layer A semiconductor device, wherein the impurity concentration is lower than that of the first parallel pn structure. 請求項１２又は請求項１３において、前記第２の並列ｐｎ構造のｐｎ繰り返しピッチは前記第１の並列ｐｎ構造のｐｎ繰り返しピッチよりも狭いことを特徴とする半導体装置。According to claim 12 or claim 13, pn repetition pitch of said second parallel pn structure wherein a narrower than pn repetition pitch of said first parallel pn structure. 請求項１２乃至請求項１４のいずれか一項において、前記第２の並列ｐｎ構造の不純物濃度は前記第１の並列ｐｎ構造の不純物濃度よりも低いことを特徴とする半導体装置。According to any one of claims 12 to claim 14, the impurity concentration of said second parallel pn structure wherein a lower than the impurity concentration of said first parallel pn structure. 請求項１２乃至請求項１５のいずれか一項において、前記直下部分の並列ｐｎ構造の第１主面側が前記第１電極層に導電接続する第２導電型ウェル領域で覆われて成ることを特徴とする半導体装置。 16. The structure according to claim 12 , wherein the first main surface side of the parallel pn structure in the immediately lower portion is covered with a second conductivity type well region that is conductively connected to the first electrode layer. the semiconductor device according to. 請求項１６において、前記第１の並列ｐｎ構造のうち前記直下部分の並列ｐｎ構造に隣接する最端の縦形第２導電型領域は、前記第２導電型ウェル領域のウェル端部に接続していることを特徴とする半導体装置。17. The outermost vertical second conductivity type region adjacent to the parallel pn structure in the immediately lower portion of the first parallel pn structure is connected to a well end portion of the second conductivity type well region. wherein a it is. 請求項１２乃至請求項１７のいずれか一項において、前記第１の電極層の周縁部はフィールドプレートであることを特徴とする半導体装置。According to any one of claims 12 to claim 17, wherein a said peripheral edge portion of the first electrode layer is a field plate. 請求項１２乃至請求項１８のいずれか一項において、前記第１の並列ｐｎ構造と前記第２の並列ｐｎ構造とは層面が相平行して配置されていることを特徴とする半導体装置。According to any one of claims 12 to claim 18, wherein a said first parallel pn structure and the layer surface and the second parallel pn structure is arranged in parallel phases. 請求項１２乃至請求項１８のいずれか一項において、前記第１の並列ｐｎ構造と前記第２の並列ｐｎ構造とは層面が相直交して配置されていることを特徴とする半導体装置。According to any one of claims 12 to claim 18, wherein a said first parallel pn structure and the layer surface and the second parallel pn structure is arranged to phase quadrature. 請求項１２乃至請求項２０のいずれか一項において、前記第１及び第２の並列ｐｎ構造を構成する縦形第１導電型領域と縦形第２導電型領域とは、平面的にストライプ状であることを特徴とする半導体装置。21. The vertical first conductive type region and the vertical second conductive type region constituting the first and second parallel pn structures according to any one of claims 12 to 20 are striped in plan view. A semiconductor device.
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