JP2004119473A - Semiconductor device, its manufacturing method, circuit board, and electronic apparatus - Google Patents

Semiconductor device, its manufacturing method, circuit board, and electronic apparatus Download PDF

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JP2004119473A
JP2004119473A JP2002277454A JP2002277454A JP2004119473A JP 2004119473 A JP2004119473 A JP 2004119473A JP 2002277454 A JP2002277454 A JP 2002277454A JP 2002277454 A JP2002277454 A JP 2002277454A JP 2004119473 A JP2004119473 A JP 2004119473A
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Prior art keywords
semiconductor device
semiconductor
conductive layer
manufacturing
semiconductor chip
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JP2002277454A
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JP4081666B2 (en
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Takahiro Imai
今井 隆浩
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2002277454A priority Critical patent/JP4081666B2/en
Priority to US10/661,372 priority patent/US7005324B2/en
Publication of JP2004119473A publication Critical patent/JP2004119473A/en
Priority to US11/222,330 priority patent/US7180168B2/en
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Publication of JP4081666B2 publication Critical patent/JP4081666B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To enable a thin and highly integrated semiconductor device to be manufactured through simple manufacturing processes. <P>SOLUTION: A groove 30 is cut on the first surface 20 of a semiconductor substrate 10 where an integrated circuit 12 and electrodes 14 are formed. An insulating layer 40 is formed, at least, on the inner surface of the groove 30. A conductive layer 50 is formed on the insulating layer 40 on the inner surface of the groove 30. The second surface 22 of the semiconductor substrate 10 opposed to its first surface 20 is ground as far as the groove 30 is exposed, and the semiconductor substrate 10 is divided into a plurality of semiconductor chips 70 which are provided with the conductor layers 50 on their sides, respectively. The semiconductor chips 70 are stacked up. The conductive layer 50 of one of the semiconductor chips 70 and the conductive layer 50 of the other semiconductor chip 70 are electrically connected together. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。
【0002】
【発明の背景】
3次元的実装形態の半導体装置が開発されている。例えば、ワイヤによって上下の電気的な接続を図ることが知られているが、各半導体チップの電極にワイヤをボンディングしなければならず、多数の半導体チップを積層すると工程が複雑になってしまう。さらに、ワイヤボンディングの領域を露出させる必要があるので、半導体チップの外形及び電極の位置などが制限されてしまう。
【0003】
また、半導体チップに貫通穴を形成し、貫通穴の内面に絶縁層を形成し、その内側に貫通電極を形成することが知られている。その場合、小さな貫通穴の内面に絶縁層を形成することが難しく、その内側に導電電極を形成することも難しい。また、集積回路の設計を貫通穴を避けて行う必要があるので、設計上の制約が多くなってしまう。
【0004】
本発明の目的は、薄型かつ高集積の半導体装置を簡単な工程で製造することにある。
【0005】
【課題を解決するための手段】
(1)本発明に係る半導体装置の製造方法は、(a)集積回路及び電極が形成された半導体基板に第1の面から溝を形成すること、
(b)少なくとも前記溝の内面に絶縁層を形成すること、
(c)前記溝の内面で前記絶縁層上に導電層を形成すること、
(d)前記半導体基板を前記第1の面とは反対側の第2の面から前記溝が露出する厚さまで研磨して、前記半導体基板を、前記導電層が側面に露出してなる複数の前記半導体チップに分割すること、
(e)複数の前記半導体チップを積層すること、及び、
(f)複数の前記半導体チップのうち、いずれかの前記半導体チップの前記導電層と、他の前記半導体チップの前記導電層と、を電気的に接続することを含む。
【0006】
本発明によれば、半導体チップの側面に形成された導電層によって、複数の積層された半導体チップを電気的に接続する。導電層は、半導体基板の状態で一括して形成することができるので、製造工程が簡単である。また、導電層は他の半導体チップによって覆われることがないので、半導体チップの外形及び電極の位置に制限されることなく、設計自由度の高い半導体装置を製造することができる。
【0007】
(2)この半導体装置の製造方法において、
前記(b)工程で、前記絶縁層を、前記溝の内面から前記第1の面にかけて連続的に形成してもよい。
【0008】
これによって、絶縁層で半導体チップの角部を覆うことができる。したがって、半導体チップの角部を絶縁層で保護することができるので、チッピングの発生及び拡大を低減し、また、例えば第1の面に形成された集積回路の素子及び配線の剥離を防止することができる。
【0009】
(3)この半導体装置の製造方法において、
前記(c)工程で、前記導電層を前記溝の内面から前記第1の面にかけて連続的に形成してもよい。
【0010】
これによれば、導電層を配線となるように形成してもよい。
【0011】
(4)この半導体装置の製造方法において、
前記(c)工程で、前記導電層を前記電極に電気的に接続させてもよい。
【0012】
(5)この半導体装置の製造方法において、
前記(e)工程で、複数の前記半導体チップを、前記電極の形成された面が同一方向を向くように積層してもよい。
【0013】
(6)この半導体装置の製造方法において、
前記(e)工程で、複数の前記半導体チップを、いずれかの前記半導体チップの前記電極の形成された面が他の前記半導体チップの前記電極の形成された面とは反対方向を向くように積層してもよい。
【0014】
(7)この半導体装置の製造方法において、
前記(e)工程は、前記半導体チップ同士の間に絶縁部材を設けることを含んでもよい。
【0015】
これによって、半導体チップ同士が電気的にショートするのを防ぐことができる。
【0016】
(8)この半導体装置の製造方法において、
前記(e)工程で、前記絶縁部材を、前記半導体チップの側面よりも突出するように設けてもよい。
【0017】
これによれば、絶縁部材の突出部によって、例えば絶縁部材の両側に配置される導電層同士が電気的にショートするのを防ぐことができる。
【0018】
(9)この半導体装置の製造方法において、
前記(f)工程は、前記導電層同士を電気的に接続する第2の導電層を、少なくとも1つの前記半導体チップの側面に形成することを含んでもよい。
【0019】
これによれば、第2の導電層を半導体チップの側面に形成するので、半導体チップ同士の間を厚くすることなく、極めて薄い半導体装置を製造することができる。
【0020】
(10)この半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、前記半導体チップの高さ方向に延びるように形成することで、前記半導体チップの幅方向に一致してなる前記導電層同士を電気的に接続してもよい。
【0021】
(11)この半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、前記半導体チップの幅方向に延びる部分を有するように形成することで、前記半導体チップの幅方向にずれてなる前記導電層同士を電気的に接続してもよい。
【0022】
これによれば、さらに設計自由度の高い半導体装置を製造することができる。
【0023】
(12)この半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層の一部を前記絶縁部材の前記突出部に形成してもよい。
【0024】
これによれば、第2の導電層が他の部材と電気的にショートするのを防ぐことができる。
【0025】
(13)この半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、ろう材によって形成してもよい。
【0026】
(14)この半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、導電性材料の微粒子を含む溶媒を吐出することで形成してもよい。
【0027】
これによれば、溶媒を吐出させることで、例えば複数の第2の導電層を一括して形成することができる。
【0028】
(15)この半導体装置の製造方法において、
少なくとも前記(d)工程後に、
(g)複数の前記半導体チップを基板に搭載すること、及び、
(h)前記半導体チップを前記基板の配線パターンに電気的に接続することをさらに含んでもよい。
【0029】
(16)この半導体装置の製造方法において、
前記(e)及び(g)工程を終了した後に、前記(f)及び(h)工程を行ってもよい。
【0030】
これによれば、複数の半導体チップを積層し、かつ、それらを基板に搭載した後に、電気的な接続工程を行う。すなわち、組み立て工程と、電気的な接続工程とを1回ずつ行うことで半導体装置を製造することができるので、製造工程が極めて簡単になる。
【0031】
(17)この半導体装置の製造方法において、
前記(h)工程で、前記導電層を、ろう材によって前記配線パターンに電気的に接続してもよい。
【0032】
(18)この半導体装置の製造方法において、
前記(h)工程で、前記導電層を、導電性材料の微粒子を含む溶媒を吐出することで前記配線パターンに電気的に接続してもよい。
【0033】
これによれば、溶媒を吐出させることで、例えば複数の導電層を一括して配線パターンに電気的に接続することができる。
【0034】
(19)本発明に係る半導体装置は、上記方法によって製造されてなる。
【0035】
(20)本発明に係る半導体装置は、第1の面を有し、集積回路及び電極が形成されるとともに積層されてなる複数の半導体チップと、
前記半導体チップの前記第1の面からそれに連続する側面にかけて連続的に形成された絶縁層と、
前記半導体チップの側面で前記絶縁層上に形成された導電層と、
前記複数の半導体チップのうち、いずれかの半導体チップの前記導電層と、他の半導体チップの前記導電層と、を電気的に接続する第2の導電層と、
を含み、
前記半導体チップの側面の前記導電層から露出する部分は、前記絶縁層で覆われてなり、
前記第2の導電層は、少なくとも1つの半導体チップの側面に形成されてなる。
【0036】
本発明によれば、半導体チップの側面の導電層から露出する部分が絶縁層で覆われているので、導電層以外の部分での、外部との電気的な導通を遮断することができる。また、導電層は他の半導体チップによって覆われることがないので、半導体チップの外形及び電極の位置に制限されることなく、設計自由度の高い半導体装置を提供することができる。さらに、第2の導電層は半導体チップの側面に形成されるので、半導体チップ同士の間を厚くすることなく、極めて薄い半導体装置を提供することができる。
【0037】
(21)この半導体装置において、
前記導電層は、前記半導体チップの側面から前記第1の面にかけて連続的に形成されてもよい。
【0038】
これによれば、導電層は配線となるように形成されてもよい。
【0039】
(22)この半導体装置において、
前記導電層は、前記電極に電気的に接続されてもよい。
【0040】
(23)この半導体装置において、
前記複数の半導体チップは、前記電極の形成された面が同一方向を向くように積層されてもよい。
【0041】
(24)この半導体装置において、
前記複数の半導体チップは、いずれかの前記半導体チップの前記電極の形成された面が他の前記半導体チップの前記電極の形成された面とは反対方向を向くように積層されてもよい。
【0042】
(25)この半導体装置において、
前記半導体チップ同士の間に絶縁部材が設けられてもよい。
【0043】
これによって、半導体チップ同士が電気的にショートするのを防ぐことができる。
【0044】
(26)この半導体装置において、
前記絶縁部材は、前記半導体チップの側面よりも突出してもよい。
【0045】
これによれば、絶縁部材の突出部によって、例えば絶縁部材の両側に配置される導電層同士が電気的にショートするのを防ぐことができる。
【0046】
(27)この半導体装置において、
前記第2の導電層は、前記半導体チップの高さ方向に延びてなり、前記半導体チップの幅方向に一致してなる前記導電層同士を電気的に接続してもよい。
【0047】
(28)この半導体装置において、
前記第2の導電層は、前記半導体チップの幅方向に延びる部分を有し、前記半導体チップの幅方向にずれてなる前記導電層同士を電気的に接続してもよい。
【0048】
これによれば、さらに設計自由度の高い半導体装置を提供することができる。
【0049】
(29)この半導体装置において、
前記第2の導電層の一部は、前記絶縁部材の前記突出部に形成されてもよい。
【0050】
これによれば、第2の導電層が他の部材と電気的にショートするのを防ぐことができる。
【0051】
(30)この半導体装置において、
前記第2の導電層は、ろう材によって形成されてもよい。
【0052】
(31)この半導体装置において、
前記第2の導電層は、導電性材料の微粒子を含む溶媒によって形成されてもよい。
【0053】
(32)この半導体装置において、
配線パターンが形成された基板をさらに含み、
前記複数の半導体チップは、前記基板に搭載されるとともに、前記導電層を介して前記配線パターンに電気的に接続されてもよい。
【0054】
(33)この半導体装置において、
前記複数の半導体チップの外形の大きさは、ほぼ同じであってもよい。
【0055】
(34)この半導体装置において、
前記複数の半導体チップのうち、いずれかの前記半導体チップの外形の大きさは、他の前記半導体チップの外形の大きさとは異なっていてもよい。
【0056】
(35)本発明に係る回路基板には、上記半導体装置が実装されている。
【0057】
(36)本発明に係る電子機器は、上記半導体装置を有する。
【0058】
【発明の実施の形態】
以下、本発明の実施の形態を、図面を参照して説明する。図1〜図13は、本発明を適用した実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態では、半導体基板(例えばシリコン基板)10を使用する。半導体基板10は、半導体ウエハであってもよい。図1では、半導体ウエハの一部が示されている。半導体基板10の平面形状は限定されないが、例えば半導体ウエハの場合には円形であることが一般的である。
【0059】
半導体基板10には、複数の集積回路(例えばトランジスタやメモリを有する回路)12が形成されている。半導体基板10には、複数の電極(例えばパッド)14が形成されている。各電極14は、集積回路12に電気的に接続されている。各電極14は、集積回路12に重ならない領域(図1では集積回路の外側の領域)に形成されてもよい。各電極14は、アルミニウム系又は銅系の金属で形成されてもよい。電極14の表面の形状は特に限定されないが矩形であることが多い。半導体基板10が半導体ウエハである場合、複数の半導体チップとなる各領域に、2つ以上(1グループ)の電極14が形成される。図1に示す例では、電極14は、半導体チップとなる領域の4辺に沿って配列されているが、2辺に沿って配列されてもよいし、中央部に配列されてもよい。
【0060】
半導体基板10は、集積回路12が形成された側の第1の面20と、それとは反対の第2の面22と、を有する。複数の電極14は、第1の面20から外部に露出している。
【0061】
半導体基板10には、少なくとも1層の絶縁層(第2の絶縁層)16が形成されている。図2に示す例では、絶縁層16は、半導体基板10の第1の面20に形成されている。絶縁層16は、パッシベーション膜と呼ばれ、例えば、SiO、SiN、ポリイミド樹脂などで形成することができる。絶縁層16は、電極14の少なくとも一部を露出する開口部18を有する。絶縁層16は、電極14の表面を覆って形成した後、その一部をエッチングして電極14の一部を露出させてもよい。図2に示すように、絶縁層16は、電極14の中央部を開口して、外周端部を覆うように形成してもよい。
【0062】
図1及び図2に示される仮想ライン24は、半導体基板10を複数の領域(半導体チップとなる領域)に区画している。仮想ライン24は、集積回路12及び電極14を避けて形成されてもよい。各領域(半導体チップ)の外形は、矩形、円形又はその他の多角形であってもよいし、限定されるものではない。
【0063】
図3に示すように、半導体基板10に第1の面20から溝30を形成する。本実施の形態では、溝30は仮想ライン24に沿って形成する。すなわち、溝30は、半導体基板10を複数の半導体チップとなる領域に区画するように形成する。図3に示す例では、溝30は、集積回路12及び電極14を避けて形成している。溝30は、半導体基板10を、ブレードなどで切削することにより機械的に形成してもよいし、エッチングなどで化学的に形成してもよいし、レーザなどで光学的に形成してもよい。
【0064】
溝30は、第1の面20から傾斜してなるテーパ(例えば溝の開口方向に広がるテーパ)が付された壁面を有してもよいし、第1の面20から垂直に落ちる壁面を有してもよい。溝30は、底面が形成されて凹状になっていてもよいし、底面が形成されずにV状になっていてもよい。
【0065】
溝30は、半導体基板10を貫通しないように形成する。溝30は、完成品としての半導体チップの厚さよりも深くなるように形成する。また、溝30は、半導体基板10の内部に形成される集積回路12の素子及び配線よりも深くなるように形成する。なお、半導体基板10の溝30の内面には、半導体部分(例えばシリコン)が露出する。
【0066】
図4に示すように、半導体基板10に絶縁層40を形成する。絶縁層40の材料としては、酸化膜(例えばSiO)、窒化膜(例えばSiN)又は樹脂(例えばポリイミド樹脂)などが挙げられる。
【0067】
絶縁層40は、少なくとも溝30の内面に形成する。図4に示す例では、絶縁層40は、溝30の内壁面及び底面に形成しているが、溝30の内壁面のみに形成しても構わない。ただし、絶縁層40は、溝30を埋め込まないように形成する。すなわち、絶縁層40によって溝(又は凹部)を形成する。図4に示す例では、溝30の内面(図4では内壁面及び底面)の全部は、絶縁層40で覆われている。
【0068】
絶縁層40を溝30の内面から第1の面20にかけて連続的に形成してもよい。例えば、半導体基板10の第1の面20及び溝30の内面を覆って絶縁層40を形成し、必要な部分をエッチングして絶縁層40から露出させてもよい。図4に示す例では、絶縁層40の電極14を覆う一部をエッチングして、電極14を露出する開口部42を形成する。
【0069】
溝30の内面(詳しくは内壁面)と第1の面20との間の角部は、半導体チップの角部に相当するので、絶縁層40によって半導体チップの角部を覆うことができる(図12参照)。したがって、半導体チップの角部を絶縁層で保護することができるので、チッピングの発生及び拡大を低減し、また、第1の面20に形成された集積回路12の素子及び配線の剥離を防止することができる。
【0070】
なお、第1の面20に絶縁層(第2の絶縁層)16が形成されている場合、絶縁層40の一部(第1の面上の部分)を絶縁層(第2の絶縁層)16上に形成する。
【0071】
図5に示すように、半導体基板10に導電層50を形成する。導電層50は、銅(Cu)、クロム(Cr)、チタン(Ti)、ニッケル(Ni)、チタンタングステン(Ti−W)、金(Au)、アルミニウム(Al)、ニッケルバナジウム(NiV)、タングステン(W)のうちのいずれかを積層して、あるいはいずれかの一層で形成してもよい。導電層50の形成工程としては、フォトリソグラフィを適用した後にエッチングすることで形成してもよいし、スパッタリングなど形成してもよいし、無電解メッキによるアディティブ法を適用することで形成してもよい。あるいは、インクジェット方式を使用して導電層50を形成してもよい。これによれば、インクジェットプリンタ用に実用化された技術を応用することで、高速かつ導電層50の材料を無駄なく経済的に設けることが可能である。
【0072】
導電層50は、溝30の内面(詳しくは内壁面)で絶縁層40上に形成する。図5に示す例では、導電層50は、溝30の内壁面及び底面に形成しているが、溝30の内壁面のみに形成しても構わない。ただし、導電層50は、溝30を埋め込まないように形成する。すなわち、絶縁層50によって溝(又は凹部)を形成する。溝30の内面と導電層50との間には、絶縁層40が介在するので、両者の電気的な接続が遮断される。
【0073】
導電層50は、溝30の内面に深さ方向に沿って延びるように形成してもよい。あるいは、導電層50は、ランド状(円形又は矩形など)に形成してもよい。溝30の内面のうち導電層50から露出する部分は、絶縁層40が露出する。
【0074】
図6は、図5のVI−VI線断面図である。図6に示す例では、導電層50は、溝30の内側の方向に、絶縁層40の表面から突起するように形成されている。
【0075】
変形例として、図7に示すように、導電層54は、溝32の内面において、絶縁層44の表面と面一になるように形成されてもよい。その場合、導電層54は絶縁層44の内部に入り込む。他の変形例として、図8に示すように、導電層56は、溝34の内面において、絶縁層46の表面よりも窪むように形成されていてもよい。その場合も、導電層56は、絶縁層46の内部に入り込む。ただし、導電層56は、絶縁層46で覆わずに露出させる。
【0076】
これらの変形例によれば、導電層54,56と絶縁層44,46との密着力が大きくなるので、導電層54,56を絶縁層44,46から剥離しにくくすることができる。なお、必要に応じて、導電層の形成工程後に、再度、絶縁層の形成工程を行って、絶縁層における導電層の周囲の部分を厚く形成してもよい。
【0077】
図5に示すように、導電層50を溝30の内面から第1の面20にかけて連続的に形成してもよい。すなわち、導電層50は、溝30の内面から第1の面20の方向に延びるように配線として形成してもよい。
【0078】
図5に示すように、導電層50を電極14に電気的に接続させてもよい。導電層50は、第1の面20に延びてなり、複数の絶縁層16,40の開口部18,42内で電極14と電気的に接続する接続部52を有する。接続部52は、電極14を覆うように形成してもよい。
【0079】
変形例として、導電層50を電極14に電気的に接続しなくてもよい。すなわち、導電層50は、ダミー配線(集積回路と導通しない配線)として形成してもよい。
【0080】
これによれば、半導体チップの側面に導電層50を形成することができる。例えば、導電層50を電極14に電気的に接続させれば、半導体チップの側面に、集積回路12と電気的に接続した外部端子を容易に形成することができる。したがって、半導体チップ上の配線構造の自由度を向上させることができる。
【0081】
次に、半導体基板10の研磨工程を行い、複数の半導体チップ70に分割する。本実施の形態では、半導体基板10を、シート60によって保持した状態で研磨する。シート60は半導体基板10の保持部材である。
【0082】
図9に示すように、半導体基板10に、第1の面20からシート60を貼り付ける。シート60は、半導体基板10を第1の面20から保持する。シート60は、粘着材であってもよく、例えば、紫外線硬化型樹脂からなるUVテープであってもよい。UVテープによれば、紫外線の照射の有無によって、シート60の粘着力をコントロールできるので、半導体基板10の保持及び半導体チップ70の剥離に適している。
【0083】
図9に示す例では、シート60と半導体基板10との間に、樹脂などの充填材62が設けられ、シート60は充填材62を介して半導体基板10を保持している。充填材62は、少なくとも半導体基板10の溝30に充填され、図9に示すように、第1の面20にも設けられてもよい。充填材62は、シート60を貼り付ける前に、半導体基板10に第1の面20から塗布してもよく、あるいは、あらかじめシート60に設けておき、シート60を貼り付けることで溝30に設けてもよい。
【0084】
変形例として、充填材62なしで、半導体基板10にシート60を貼り付けてもよい。あるいは、シート60の一部が充填材62であってもよい。
【0085】
こうして、図10に示すように、半導体基板10を、第2の面22から研磨する。すなわち、半導体基板10の裏面をポリシングする。例えば、シート60が貼り付けられた半導体基板10をステージ(図示しない)に固定し、研磨用治具(図示しない)に備えられた砥石によって、半導体基板10を第2の面22から機械的に研磨する。本工程では、半導体基板10を溝30が露出する厚さまで研磨する。これによって、半導体基板10を複数の半導体チップ70に分割するとともに、各半導体チップ70を薄くすることができる。
【0086】
これによれば、半導体基板10に第1の面20からシート60を貼り付けているので、ばらばらに分割された複数の半導体チップ70を一括して保持することができる。したがって、分割後の複数の半導体チップ70の取り扱いを容易にすることができる。
【0087】
また、研磨工程のときに、溝30に充填材62が設けられているため、研磨工程で生じる粉状の異物が溝30に入り込むのを防ぐことができる。したがって、半導体チップ70の損傷及び異物の付着を防止して、半導体装置の信頼性を向上させることができる。
【0088】
図11に示すように、必要に応じて、複数の半導体チップ70の研磨面に絶縁層(第3の絶縁層)72を形成してもよい。複数の半導体チップ70がシート60に保持されていれば、複数の半導体チップ70の研磨面を一括して絶縁処理することができる。また、図11に示すように、複数の半導体チップ70の間に充填材62が設けられていれば、例えば、複数の半導体チップ70の研磨面を含む全面に絶縁層72を形成した後、絶縁層72における充填材62の部分をエッチングして除去すればよい。絶縁層72は、絶縁層40と同一の材料で形成されてもよい。絶縁層72を形成することで、半導体チップ70の研磨面における外部との電気的な導通を遮断することができる。また、半導体チップ70の半導体部分(例えばシリコン)の全面を、絶縁層16,40,72によって覆うことができるので、半導体チップ70の端子(例えば導電層50)以外の部分での、外部との電気的な導通を遮断することができる。
【0089】
その後、半導体チップ70をシート60から剥離する。半導体チップ70とシート60との間に充填材62が設けられている場合には、半導体チップ70を充填材62から剥離する。例えば、それぞれの半導体チップ70を、シート60を介して、ツール(図示しない)によってピックアップする。こうして、個片の半導体チップ70を取り出すことができる。
【0090】
以上の工程によれば、絶縁層40を半導体基板10の溝30の内面に形成する。半導体基板10の溝30の内面は、複数の半導体チップ70の側面に相当する。したがって、半導体基板10の状態で、複数の半導体チップ70の側面を一括して絶縁処理することができる。また、半導体基板10を研磨する前に絶縁層40を形成するので、半導体基板10の割れ及び損傷を回避しつつ、極めて薄い半導体装置を製造することが可能である。
【0091】
上述の工程により、半導体装置1を製造することができる。半導体装置1は、集積回路12及び電極14が形成された半導体チップ70と、絶縁層40と、導電層50と、を含む。絶縁層40は、半導体チップ70の第1の面(図12では集積回路及び電極が形成された面)からそれに連続する側面にかけて連続的に形成されている。絶縁層40は、半導体チップ70の側面の全体を覆うことが好ましい。導電層50は、半導体チップ70の側面で絶縁層40上に形成されている。そして、半導体チップ70の側面の導電層50から露出する部分は、絶縁層40で覆われている。導電層50は、電極14との電気的な接続部52を有する。なお、その他の構成は、上述した製造方法によって得られる内容である。
【0092】
次に、図13に示すように、複数(図13では4つ)の半導体チップ70(詳しくは半導体装置1)を積層する。半導体チップ70は、他の半導体チップ70の電極14の形成された面又はそれとは反対の面に積層される。複数の半導体チップ70を接着材料84によって接着してもよい。上述の製造方法で得られた半導体チップ70は、極めて薄いため、このように3次元的実装形態に使用すると効果的である。
【0093】
複数の半導体チップ70を、電極14の形成された面が同一方向(図13では基板とは反対方向)を向くように積層してもよい。変形例として、いずれかの半導体チップ70の電極14の形成された面は、他の半導体チップ70の電極14の形成された面とは反対方向を向いてもよい。
【0094】
図13に示すように、ほぼ同じ大きさの外形を有する複数の半導体チップ70を積層してもよい。その場合、各半導体チップ70の外周を一致させてもよい。言い換えれば、複数の半導体チップ70を、その外形の全部が重複するように積層してもよい。あるいは、複数の半導体チップ70を、その外形の一部が重複するように積層してもよい。
【0095】
変形例として、異なる大きさの外形を有する複数の半導体チップ70を積層してもよい。例えば、半導体チップ70にそれよりも外形の小さい他の半導体チップ70を順次積層し、全体がピラミッド形状になるようにしてもよい。
【0096】
図13に示すように、複数の半導体チップ70を基板80に搭載してもよい。基板80には、配線パターン82が形成されている。図13に示す例では、基板80は、回路基板(例えばマザーボード)である。回路基板には、他の電子部品(抵抗器、コンデンサ、コイルなど)も搭載される。あるいは、基板80は、半導体装置のインターポーザであってもよい。その場合、基板80には、電気的な接続部となる外部端子(例えばハンダボール)が形成されている。
【0097】
複数の半導体チップ70を基板80上で積層してもよいし、積層した後に基板80に搭載してもよい。図13に示すように、複数の半導体チップ70を、電極14の形成された面が基板80とは反対方向を向くように、基板80に搭載してもよい。変形例として、電極14の形成された面が基板80の方向を向くようにしてもよい。
【0098】
そして、複数の半導体チップ70同士を電気的に接続する。詳しくは、いずれかの半導体チップ70の導電層50と、他の半導体チップ70の導電層50と、を電気的に接続する。これによれば、全部の半導体チップ70を積層した後に、一括して複数の半導体チップ70同士を電気的に接続するので、製造工程が簡単である。
【0099】
複数の半導体チップ70を基板80に搭載した場合には、半導体チップ70を配線パターン82に電気的に接続する。半導体チップ70を、導電層50を介して、配線パターン82に電気的に接続してもよい。
【0100】
本実施の形態では、それらの電気的な接続工程を、複数の半導体チップ70を積層し、かつ、複数の半導体チップ70を基板80に搭載した後に行う。こうすることで、組み立て工程と、電気的な接続工程とを1回ずつ行うことで半導体装置を製造することができるので、製造工程が極めて簡単になる。
【0101】
図13に示すように、複数の半導体チップ70の導電層50同士を、第2の導電層90によって電気的に接続してもよい。第2の導電層90は、配線となるように細長く形成してもよい。第2の導電層90は、少なくとも1つの半導体チップ70の側面に形成する。第2の導電層90は、半導体チップ70同士の間を通るように形成する。その場合、第2の導電層90は、半導体チップ70同士の間において、少なくとも1つの半導体チップ70の側面を通るように形成してもよい。これによれば、第2の導電層90を半導体チップ70の側面に形成するので、半導体チップ70同士の間を厚くすることなく、極めて薄い半導体装置を製造することができる。
【0102】
第2の導電層90を、導電性材料の微粒子を含む溶媒92を吐出することで形成してもよい。詳しくは、溶媒92の液滴を、液滴吐出装置86のノズルから吐出する。これによれば、溶媒92を吐出させることで、例えば複数の第2の導電層90を一括して形成することができる。また、あらかじめ決定しておいたパターンに沿って溶媒92を吐出させれば、無駄なく簡単に第2の導電層90を形成することができる。
【0103】
導電性材料の微粒子を含む溶媒92の材料として、例えば、真空冶金株式会社製「パーフェクトゴールド」「パーフェクトシルバー」を使用してもよい。
【0104】
例えば、インクジェット方式を適用して、溶媒92の液滴を吐出させてもよい。その場合、液滴吐出装置86は、インクジェットヘッドであってもよい。インクジェットヘッドは、静電アクチュエータの構造を有し、詳しくはマイクロマシニング技術による微細加工技術を用いて形成された微小構造のアクチュエータを有する。このような微小構造のアクチュエータとしては、その駆動源として静電気力を用いている。インクジェットヘッドは、静電気力を利用してノズルから溶媒92の液滴を吐出させる。これによれば、インクジェットプリンタ用に実用化された技術を応用することで、高速かつ材料を無駄なく経済的に吐出することが可能である。
【0105】
あるいは、ディスペンサによって溶媒92の液滴を吐出させてもよい。ディスペンサは取り扱いやすいので、簡単な工程で第2の導電層90を形成することができる。
【0106】
第2の導電層90をろう材(軟ろう及び硬ろうのいずれも含む)によって形成してもよい。ろう材は、ハンダペーストであってもよい。可能であれば、ろう材を液滴吐出装置86で吐出させてもよい。
【0107】
半導体チップ70の導電層50は、上述の導電性材料の微粒子を含む溶媒92によって配線パターン82に電気的に接続してもよいし、ろう材によって配線パターン82に電気的に接続してもよい。その場合、溶媒92又はろう材の液滴を、インクジェット方式を適用して吐出させてもよい。図13に示すように、半導体チップ70同士の電気的な接続と、半導体チップ70と配線パターン82との電気的な接続とを同時に行えば、製造工程が簡単になる。
【0108】
図14に示すように、必要があれば、外部に露出する導電部分(導電層50及び第2の導電層90など)を被覆部材88で覆ってもよい。図14に示す例では、被覆部材88は、絶縁材料(例えば樹脂)からなるフィルムである。
【0109】
本実施の形態に係る半導体装置の製造方法によれば、半導体チップ70の側面に形成された導電層50によって、複数の積層された半導体チップ70を電気的に接続する。導電層50は、半導体基板10の状態で一括して形成することができるので、製造工程が簡単である。導電層50は、他の半導体チップ70によって覆われることがないので、半導体チップ70の外形及び電極14の位置に制限されることなく、設計自由度の高い半導体装置(スタック型の半導体装置)を製造することができる。したがって、薄型かつ高集積の半導体装置を簡単な工程で製造することができる。
【0110】
こうして、スタック型の半導体装置を製造することができる。図14では、半導体装置が回路基板に実装されている。この半導体装置は、複数の半導体チップ70(詳しくは半導体装置1(図12参照))と、第2の導電層90と、を含む。第2の導電層90は、少なくとも1つの半導体チップ70の側面に形成されている。これによれば、バンプを介して上下の半導体チップ70を電気的に接続するよりも、バンプ高さを省略することができるので、極めて薄い半導体装置を提供することができる。なお、基板80がインターポーザである場合、この半導体装置は、基板80をさらに含む。
【0111】
半導体チップ70は、例えば、フラッシュメモリ、SRAM(Static RAM)又はDRAM(Dynamic RAM)などの各種メモリであってもよいし、MPU(MicroProcessor Unit)又はMCU(Micro Controller Unit)などのマイクロプロセッサであってもよい。複数の半導体チップ70の組み合わせとして、メモリ同士(例えばフラッシュメモリとSRAM、SRAM同士、DRAM同士)又はメモリとマイクロプロセッサなどがある。
【0112】
例えば、複数の半導体チップ70の少なくとも2つがメモリであるときに、同一配列の導電層50を第2の導電層90によって電気的に接続して、それぞれのメモリの同じアドレスのメモリセルに、情報の読み出し又は書き込みを行ってもよい。さらに、チップセレクト端子の接続においてのみ、第2の導電層90を分離しておくことで、同一配列の導電層50を用いて、少なくとも2つ(複数に可能である)の半導体チップ70を別々にコントロールしてもよい。チップセレクト端子は、例えば、矩形をなす半導体チップ70の4辺に、少なくとも1つずつ形成してもよい。チップセレクト端子を各辺ごとに配置を変更して形成すれば、設計上同一の半導体チップ70を積層した場合でも、各半導体チップ70を90°ずつ回転させれば、4つの半導体チップ70を別々にコントロールすることが可能である。
【0113】
その他の構成は、上述した製造方法によって得られる内容である。
【0114】
本実施の形態に係る半導体装置によれば、半導体チップ70の側面の導電層50から露出する部分が絶縁層で覆われているので、導電層50以外の部分での、外部との電気的な導通を遮断することができる。また、導電層50は他の半導体チップ70によって覆われることがないので、半導体チップ70の外形及び電極14の位置に制限されることなく、設計自由度の高い半導体装置を提供することができる。
【0115】
また、本実施の形態に係る半導体装置は、上述の製造方法から選択したいずれかの特定事項から導かれる構成を含み、その効果は上述の効果を備える。本実施の形態に係る半導体装置は、上述の製造方法とは異なる方法によって製造されるものを含む。
【0116】
次に、本実施の形態に係る半導体装置(スタック型の半導体装置)の変形例を説明する。なお、以下の説明では、他の形態(上述及び他の変形例)の内容と重複する部分は省略する。
【0117】
図15は、本実施の形態に係る半導体装置の第1の変形例を説明する図である。この半導体装置は、複数の半導体チップ70(詳しくは半導体装置1(図12参照))と、第2の導電層90と、を含み、最上層の半導体チップ70の電極14(詳しくは電極上の導電層の接続部52)にワイヤ100の一方の端部がボンディングされ、他方の端部が配線パターン82にボンディングされている。そして、複数の半導体チップ70及びワイヤ100は、樹脂などからなる封止部102によって封止されている。
【0118】
図16は、本実施の形態に係る半導体装置の第2の変形例を説明する図である。この半導体装置は、複数の半導体チップ70(詳しくは半導体装置1(図12参照))と、第2の導電層90と、を含み、最下層の半導体チップ70が基板80にフェースダウン実装されている。例えば、最下層の半導体チップ70の電極14にバンプ106が設けられ、ハンダなどのろう材108を介して、バンプ106と配線パターン82とが電気的に接続されてもよい。あるいは、両者の電気的な接続を、金属接合又は異方性導電材料による接合などで達成してもよい。必要があれば、最下層の半導体チップ70と基板80との間に、アンダーフィル材(例えば樹脂)104を設けてもよい。
【0119】
図16に示すように、少なくとも1つ(図16では上側3つ)の半導体チップ70の電極14の形成された面は、最下層の半導体チップ70の電極14の形成された面とは反対方向を向いてもよい。そして、図16に示す例では、最上層の半導体チップ70の電極14にワイヤ100の一方の端部がボンディングされ、他方の端部が配線パターン82にボンディングされている。これによれば、最上層及び最下層の両方の半導体チップ70から配線パターン82に電気的に接続させることができる。
【0120】
図16に示すように、半導体チップ70同士の間に絶縁部材110(例えば絶縁性の基板)が設けられてもよい。これによって、半導体チップ70同士が電気的にショートするのを確実に防ぐことができる。絶縁部材110は、半導体チップ70の外形の全部と重なってもよいし、一部と重なっていてもよい。図16に示すように、絶縁部材110を、半導体チップ70の側面よりも突出するように設けてもよい。これによれば、絶縁部材110の突出部112によって、例えば絶縁部材110の両側(上側と下側)に配置される導電層50同士が電気的にショートするのを防ぐことができる。例えば、第2の導電層90を導電性材料の微粒子を含む溶媒を吐出させて形成する場合に、突出部112によって溶媒の流動を規制することができるので、導電層50同士が電気的にショートするのを確実に防ぐことができる。
【0121】
図17は、本実施の形態に係る半導体装置の第3の変形例を説明する図であり、図18のXVII−XVII線断面図に相当する。図18は、半導体装置の側面図である。この半導体装置は、絶縁部材110を有する。図17に示す例では、最上層の半導体チップ70とその下層の半導体チップ70との間に、絶縁部材110が設けられている。そして、絶縁部材110は、半導体チップ70の外形の一部と重なっている(図18参照)。その他の構成は第1の変形例で説明した内容と同一である。
【0122】
図18に示すように、複数の半導体チップ70の側面には、複数の導電層50が露出している。複数の導電層50は、複数行複数列に配列されてもよい。複数の導電層50は、電極14と導通してなる第1の端子120と、電極14と導通していない第2の端子(ダミー端子)122と、のいずれかである。
【0123】
第2の導電層90は、半導体チップ70の高さ方向(図18では縦方向)に延びるように形成されてもよい。そして、第2の導電層90は、半導体チップ70の幅方向(図18では横方向)に一致してなる導電層50同士を電気的に接続する。言い換えれば、第2の導電層90は、同一列に配置された複数の導電層50を電気的に接続する。その場合、第2の導電層90を、少なくとも2つの第1の端子120を結ぶように形成する。図18の最も右側の列に示すように、第2の導電層90は、少なくとも2つの第1の端子120の間で、少なくとも1つの第2の端子122を通ってもよい。これによれば、第2の導電層90を第2の端子122を避けて引き回さずに済むので、製造工程が簡単である。
【0124】
第2の導電層90は、半導体チップ70の幅方向に延びる部分を有してもよい。そして、第2の導電層90は、半導体チップ70の幅方向にずれてなる導電層50同士を電気的に接続する。言い換えれば、第2の導電層90は、異なる列(図18では隣の列同士であるが1列又は複数列を飛ばしてもよい)に配置された複数の導電層50を電気的に接続する。その場合、第2の導電層90の一部は、絶縁部材110の突出部112に形成されてもよい。こうすることで、第2の導電層90が他の部材(例えば接続したくない導電層50)と電気的にショートするのを防ぐことができる。なお、第2の導電層90は、図18に示す例とは別に同一行に配置された第2の端子122を通ってもよい。
【0125】
図19は、本実施の形態に係る半導体装置の第4の変形例を説明する図であり、図20のXIX−XIX線断面図に相当する。図20は、半導体装置の平面図である。この半導体装置は、半導体チップ70(詳しくは半導体装置1(図12参照))と、半導体チップ70よりも小さい外形を有する半導体チップ71(詳しくは半導体装置3)と、第2の導電層90と、を含む。半導体装置3のその他の構成は、上述の半導体装置1の構成と同一である。図19に示す例では、複数の半導体チップ70が積層され、最上層に半導体チップ71がさらに積層されている。そして、図20に示すように、最上層の下層の半導体チップ70には、電極14の形成された面に、導電層50の一部が配線となって引き回されている。その場合、導電層50は、半導体チップ70の端部に形成された電極14から中央部に延びるように形成されてもよい。そして、半導体チップ70の中央部に、半導体チップ71が積層されてもよい。第2の導電層90は、半導体チップ70,71の導電層50同士を電気的に接続する。
【0126】
上述した半導体装置を有する電子機器として、図21には、ノート型パーソナルコンピュータ1000が示され、図22には、携帯電話2000が示されている。
【0127】
本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成(例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成)を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。
【図面の簡単な説明】
【図1】図1は、本発明の実施の形態で使用される半導体基板の一部を示す図である。
【図2】図2は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図3】図3は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図4】図4は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図5】図5は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図6】図6は、図5のVI−VI線断面図である。
【図7】図7は、本発明の実施の形態に係る半導体装置の製造方法の変形例を示す図である。
【図8】図8は、本発明の実施の形態に係る半導体装置の製造方法の変形例を示す図である。
【図9】図9は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図10】図10は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図11】図11は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図12】図12は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図13】図13は、本発明の実施の形態に係る半導体装置の製造方法を示す図である。
【図14】図14は、本発明の実施の形態に係る半導体装置を示す図である。
【図15】図15は、本発明の実施の形態に係る半導体装置の第1の変形例を示す図である。
【図16】図16は、本発明の実施の形態に係る半導体装置の第2の変形例を示す図である。
【図17】図17は、本発明の実施の形態に係る半導体装置の第3の変形例を示す図である。
【図18】図18は、本発明の実施の形態に係る半導体装置の第3の変形例を示す図である。
【図19】図19は、本発明の実施の形態に係る半導体装置の第4の変形例を示す図である。
【図20】図20は、本発明の実施の形態に係る半導体装置の第4の変形例を示す図である。
【図21】図21は、本発明の実施の形態に係る電子機器を示す図である。
【図22】図22は、本発明の実施の形態に係る電子機器を示す図である。
【符号の説明】
10 半導体基板、 12 集積回路、 14 電極、 20 第1の面、
22 第2の面、 30,32,34 溝、 40,44,46 絶縁層、
50,54,56 導電層、 70 半導体チップ、 80 基板、
82 配線パターン、 90 第2の導電層、 92 溶媒
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, a circuit board, and an electronic device.
[0002]
BACKGROUND OF THE INVENTION
Semiconductor devices having a three-dimensional mounting form have been developed. For example, it is known that upper and lower electrical connections are made by wires. However, wires must be bonded to the electrodes of each semiconductor chip, and when many semiconductor chips are stacked, the process becomes complicated. Further, since it is necessary to expose a region for wire bonding, the outer shape of the semiconductor chip, the positions of the electrodes, and the like are limited.
[0003]
It is also known that a through hole is formed in a semiconductor chip, an insulating layer is formed on the inner surface of the through hole, and a through electrode is formed inside the insulating layer. In that case, it is difficult to form an insulating layer on the inner surface of the small through hole, and it is also difficult to form a conductive electrode inside the insulating layer. Further, since it is necessary to design the integrated circuit while avoiding the through-holes, there are many design restrictions.
[0004]
An object of the present invention is to manufacture a thin and highly integrated semiconductor device by a simple process.
[0005]
[Means for Solving the Problems]
(1) A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a groove from a first surface in a semiconductor substrate on which an integrated circuit and an electrode are formed;
(B) forming an insulating layer on at least the inner surface of the groove;
(C) forming a conductive layer on the insulating layer on the inner surface of the groove;
(D) polishing the semiconductor substrate from a second surface opposite to the first surface to a thickness at which the groove is exposed, and polishing the semiconductor substrate so that the conductive layer is exposed on side surfaces; Dividing into the semiconductor chips,
(E) stacking a plurality of the semiconductor chips, and
(F) electrically connecting the conductive layer of any one of the semiconductor chips of the plurality of semiconductor chips to the conductive layer of another of the semiconductor chips.
[0006]
According to the present invention, a plurality of stacked semiconductor chips are electrically connected by the conductive layer formed on the side surface of the semiconductor chip. Since the conductive layer can be formed collectively in the state of the semiconductor substrate, the manufacturing process is simple. Further, since the conductive layer is not covered by another semiconductor chip, a semiconductor device with a high degree of design freedom can be manufactured without being limited by the outer shape of the semiconductor chip and the positions of the electrodes.
[0007]
(2) In this method of manufacturing a semiconductor device,
In the step (b), the insulating layer may be formed continuously from the inner surface of the groove to the first surface.
[0008]
Thus, the corners of the semiconductor chip can be covered with the insulating layer. Therefore, since the corners of the semiconductor chip can be protected by the insulating layer, occurrence and enlargement of chipping can be reduced, and separation of elements and wirings of the integrated circuit formed on the first surface can be prevented. Can be.
[0009]
(3) In this method of manufacturing a semiconductor device,
In the step (c), the conductive layer may be formed continuously from the inner surface of the groove to the first surface.
[0010]
According to this, the conductive layer may be formed to be a wiring.
[0011]
(4) In this method of manufacturing a semiconductor device,
In the step (c), the conductive layer may be electrically connected to the electrode.
[0012]
(5) In the method of manufacturing a semiconductor device,
In the step (e), a plurality of the semiconductor chips may be stacked such that the surfaces on which the electrodes are formed face in the same direction.
[0013]
(6) In this method of manufacturing a semiconductor device,
In the step (e), the plurality of semiconductor chips are oriented such that the surface of one of the semiconductor chips on which the electrodes are formed faces in the opposite direction to the surface of the other semiconductor chip on which the electrodes are formed. They may be stacked.
[0014]
(7) In this method of manufacturing a semiconductor device,
The step (e) may include providing an insulating member between the semiconductor chips.
[0015]
This can prevent the semiconductor chips from being electrically short-circuited.
[0016]
(8) In this method of manufacturing a semiconductor device,
In the step (e), the insulating member may be provided so as to protrude from a side surface of the semiconductor chip.
[0017]
According to this, it is possible to prevent, for example, the conductive layers disposed on both sides of the insulating member from being electrically short-circuited by the protrusion of the insulating member.
[0018]
(9) In this method of manufacturing a semiconductor device,
The step (f) may include forming a second conductive layer for electrically connecting the conductive layers on at least one side surface of the semiconductor chip.
[0019]
According to this, since the second conductive layer is formed on the side surface of the semiconductor chip, an extremely thin semiconductor device can be manufactured without increasing the thickness between the semiconductor chips.
[0020]
(10) In this method of manufacturing a semiconductor device,
In the step (f), the second conductive layer is formed so as to extend in the height direction of the semiconductor chip, thereby electrically connecting the conductive layers formed in the width direction of the semiconductor chip. You may connect.
[0021]
(11) In this method of manufacturing a semiconductor device,
In the step (f), the second conductive layer is formed so as to have a portion extending in the width direction of the semiconductor chip, thereby electrically connecting the conductive layers displaced in the width direction of the semiconductor chip. May be connected.
[0022]
According to this, a semiconductor device having a higher degree of freedom in design can be manufactured.
[0023]
(12) In this method of manufacturing a semiconductor device,
In the step (f), a part of the second conductive layer may be formed on the protrusion of the insulating member.
[0024]
According to this, it is possible to prevent the second conductive layer from being electrically short-circuited with another member.
[0025]
(13) In this method of manufacturing a semiconductor device,
In the step (f), the second conductive layer may be formed of a brazing material.
[0026]
(14) In this method of manufacturing a semiconductor device,
In the step (f), the second conductive layer may be formed by discharging a solvent containing fine particles of a conductive material.
[0027]
According to this, by discharging the solvent, for example, a plurality of second conductive layers can be formed collectively.
[0028]
(15) In this method of manufacturing a semiconductor device,
At least after the step (d),
(G) mounting a plurality of the semiconductor chips on a substrate;
(H) The method may further include electrically connecting the semiconductor chip to a wiring pattern on the substrate.
[0029]
(16) In this method of manufacturing a semiconductor device,
After the steps (e) and (g) are completed, the steps (f) and (h) may be performed.
[0030]
According to this, a plurality of semiconductor chips are stacked, and after mounting them on a substrate, an electrical connection step is performed. That is, since the semiconductor device can be manufactured by performing the assembly process and the electrical connection process once each, the manufacturing process is extremely simplified.
[0031]
(17) In this method of manufacturing a semiconductor device,
In the step (h), the conductive layer may be electrically connected to the wiring pattern by a brazing material.
[0032]
(18) In this method of manufacturing a semiconductor device,
In the step (h), the conductive layer may be electrically connected to the wiring pattern by discharging a solvent containing fine particles of a conductive material.
[0033]
According to this, by discharging the solvent, for example, a plurality of conductive layers can be collectively electrically connected to the wiring pattern.
[0034]
(19) A semiconductor device according to the present invention is manufactured by the above method.
[0035]
(20) A semiconductor device according to the present invention includes a plurality of semiconductor chips having a first surface, on which an integrated circuit and an electrode are formed and stacked,
An insulating layer formed continuously from the first surface of the semiconductor chip to a side surface continuous with the first surface;
A conductive layer formed on the insulating layer on a side surface of the semiconductor chip,
A second conductive layer that electrically connects the conductive layer of any one of the semiconductor chips and the conductive layer of another semiconductor chip among the plurality of semiconductor chips;
Including
A portion of the side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer,
The second conductive layer is formed on a side surface of at least one semiconductor chip.
[0036]
According to the present invention, since the portion of the side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer, it is possible to cut off the electrical continuity with the outside in the portion other than the conductive layer. In addition, since the conductive layer is not covered with another semiconductor chip, a semiconductor device with high design flexibility can be provided without being limited by the outer shape of the semiconductor chip and the positions of the electrodes. Further, since the second conductive layer is formed on the side surface of the semiconductor chip, an extremely thin semiconductor device can be provided without increasing the thickness between the semiconductor chips.
[0037]
(21) In this semiconductor device,
The conductive layer may be formed continuously from a side surface of the semiconductor chip to the first surface.
[0038]
According to this, the conductive layer may be formed to be a wiring.
[0039]
(22) In this semiconductor device,
The conductive layer may be electrically connected to the electrode.
[0040]
(23) In this semiconductor device,
The plurality of semiconductor chips may be stacked such that the surfaces on which the electrodes are formed face in the same direction.
[0041]
(24) In this semiconductor device,
The plurality of semiconductor chips may be stacked such that a surface of any of the semiconductor chips on which the electrodes are formed faces in a direction opposite to a surface of another semiconductor chip on which the electrodes are formed.
[0042]
(25) In this semiconductor device,
An insulating member may be provided between the semiconductor chips.
[0043]
This can prevent the semiconductor chips from being electrically short-circuited.
[0044]
(26) In this semiconductor device,
The insulating member may protrude from a side surface of the semiconductor chip.
[0045]
According to this, it is possible to prevent, for example, the conductive layers disposed on both sides of the insulating member from being electrically short-circuited by the protrusion of the insulating member.
[0046]
(27) In this semiconductor device,
The second conductive layer may extend in a height direction of the semiconductor chip, and may electrically connect the conductive layers formed in a width direction of the semiconductor chip.
[0047]
(28) In this semiconductor device,
The second conductive layer may have a portion extending in the width direction of the semiconductor chip, and may electrically connect the conductive layers shifted in the width direction of the semiconductor chip.
[0048]
According to this, it is possible to provide a semiconductor device having a higher degree of freedom in design.
[0049]
(29) In this semiconductor device,
A part of the second conductive layer may be formed on the protrusion of the insulating member.
[0050]
According to this, it is possible to prevent the second conductive layer from being electrically short-circuited with another member.
[0051]
(30) In this semiconductor device,
The second conductive layer may be formed of a brazing material.
[0052]
(31) In this semiconductor device,
The second conductive layer may be formed by a solvent containing fine particles of a conductive material.
[0053]
(32) In this semiconductor device,
Further comprising a substrate on which a wiring pattern is formed,
The plurality of semiconductor chips may be mounted on the substrate and may be electrically connected to the wiring pattern via the conductive layer.
[0054]
(33) In this semiconductor device,
The external dimensions of the plurality of semiconductor chips may be substantially the same.
[0055]
(34) In this semiconductor device,
The size of the outer shape of one of the plurality of semiconductor chips may be different from the size of the outer shape of the other semiconductor chip.
[0056]
(35) The semiconductor device is mounted on a circuit board according to the present invention.
[0057]
(36) An electronic apparatus according to the present invention includes the above-described semiconductor device.
[0058]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 13 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. In the present embodiment, a semiconductor substrate (for example, a silicon substrate) 10 is used. The semiconductor substrate 10 may be a semiconductor wafer. FIG. 1 shows a part of a semiconductor wafer. The planar shape of the semiconductor substrate 10 is not limited. For example, in the case of a semiconductor wafer, it is generally circular.
[0059]
On a semiconductor substrate 10, a plurality of integrated circuits (for example, circuits having transistors and memories) 12 are formed. A plurality of electrodes (for example, pads) 14 are formed on the semiconductor substrate 10. Each electrode 14 is electrically connected to the integrated circuit 12. Each electrode 14 may be formed in a region that does not overlap with the integrated circuit 12 (a region outside the integrated circuit in FIG. 1). Each electrode 14 may be formed of an aluminum-based or copper-based metal. The shape of the surface of the electrode 14 is not particularly limited, but is often rectangular. When the semiconductor substrate 10 is a semiconductor wafer, two or more (one group) of electrodes 14 are formed in each region to be a plurality of semiconductor chips. In the example shown in FIG. 1, the electrodes 14 are arranged along four sides of a region to be a semiconductor chip. However, the electrodes 14 may be arranged along two sides or in the center.
[0060]
The semiconductor substrate 10 has a first surface 20 on the side on which the integrated circuit 12 is formed, and a second surface 22 opposite thereto. The plurality of electrodes 14 are exposed from the first surface 20 to the outside.
[0061]
At least one insulating layer (second insulating layer) 16 is formed on the semiconductor substrate 10. In the example shown in FIG. 2, the insulating layer 16 is formed on the first surface 20 of the semiconductor substrate 10. The insulating layer 16 is called a passivation film. 2 , SiN, polyimide resin, or the like. The insulating layer 16 has an opening 18 exposing at least a part of the electrode 14. After the insulating layer 16 is formed to cover the surface of the electrode 14, a part of the insulating layer 16 may be etched to expose a part of the electrode 14. As shown in FIG. 2, the insulating layer 16 may be formed so as to open the center of the electrode 14 and cover the outer peripheral end.
[0062]
The virtual line 24 shown in FIGS. 1 and 2 divides the semiconductor substrate 10 into a plurality of regions (regions serving as semiconductor chips). The virtual line 24 may be formed avoiding the integrated circuit 12 and the electrode 14. The outer shape of each region (semiconductor chip) may be a rectangle, a circle, or another polygon, and is not limited.
[0063]
As shown in FIG. 3, a groove 30 is formed in the semiconductor substrate 10 from the first surface 20. In the present embodiment, the groove 30 is formed along the virtual line 24. That is, the groove 30 is formed so as to partition the semiconductor substrate 10 into regions that become a plurality of semiconductor chips. In the example shown in FIG. 3, the groove 30 is formed avoiding the integrated circuit 12 and the electrode 14. The groove 30 may be formed mechanically by cutting the semiconductor substrate 10 with a blade or the like, may be formed chemically by etching or the like, or may be formed optically by laser or the like. .
[0064]
The groove 30 may have a wall surface provided with a taper inclined from the first surface 20 (for example, a taper expanding in the opening direction of the groove), or a wall surface falling vertically from the first surface 20. May be. The groove 30 may have a concave shape with a bottom surface formed, or may have a V shape without a bottom surface.
[0065]
The groove 30 is formed so as not to penetrate the semiconductor substrate 10. The groove 30 is formed so as to be deeper than the thickness of the semiconductor chip as a finished product. Further, the groove 30 is formed so as to be deeper than elements and wirings of the integrated circuit 12 formed inside the semiconductor substrate 10. Note that a semiconductor portion (for example, silicon) is exposed on the inner surface of the groove 30 of the semiconductor substrate 10.
[0066]
As shown in FIG. 4, the insulating layer 40 is formed on the semiconductor substrate 10. As a material of the insulating layer 40, an oxide film (eg, SiO 2 2 ), A nitride film (for example, SiN) or a resin (for example, a polyimide resin).
[0067]
The insulating layer 40 is formed at least on the inner surface of the groove 30. In the example shown in FIG. 4, the insulating layer 40 is formed on the inner wall surface and the bottom surface of the groove 30, but may be formed only on the inner wall surface of the groove 30. However, the insulating layer 40 is formed so as not to fill the groove 30. That is, a groove (or a concave portion) is formed by the insulating layer 40. In the example shown in FIG. 4, the entire inner surface (the inner wall surface and the bottom surface in FIG. 4) of the groove 30 is covered with the insulating layer 40.
[0068]
The insulating layer 40 may be formed continuously from the inner surface of the groove 30 to the first surface 20. For example, the insulating layer 40 may be formed so as to cover the first surface 20 of the semiconductor substrate 10 and the inner surface of the groove 30, and a necessary portion may be etched to be exposed from the insulating layer 40. In the example shown in FIG. 4, a portion of the insulating layer 40 covering the electrode 14 is etched to form an opening 42 exposing the electrode 14.
[0069]
Since the corner between the inner surface (specifically, the inner wall surface) of the groove 30 and the first surface 20 corresponds to the corner of the semiconductor chip, the corner of the semiconductor chip can be covered with the insulating layer 40 (FIG. 12). Therefore, since the corners of the semiconductor chip can be protected by the insulating layer, occurrence and enlargement of chipping are reduced, and separation of elements and wiring of the integrated circuit 12 formed on the first surface 20 is prevented. be able to.
[0070]
When the insulating layer (second insulating layer) 16 is formed on the first surface 20, a part of the insulating layer 40 (portion on the first surface) is formed as an insulating layer (second insulating layer). 16 is formed.
[0071]
As shown in FIG. 5, the conductive layer 50 is formed on the semiconductor substrate 10. The conductive layer 50 is made of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), gold (Au), aluminum (Al), nickel vanadium (NiV), tungsten Any of (W) may be stacked or formed of any one layer. The conductive layer 50 may be formed by etching after applying photolithography, may be formed by sputtering, or may be formed by applying an additive method using electroless plating. Good. Alternatively, the conductive layer 50 may be formed using an inkjet method. According to this, it is possible to provide the material of the conductive layer 50 at high speed and economically without waste by applying the technology practically used for the ink jet printer.
[0072]
The conductive layer 50 is formed on the insulating layer 40 on the inner surface (specifically, the inner wall surface) of the groove 30. In the example shown in FIG. 5, the conductive layer 50 is formed on the inner wall surface and the bottom surface of the groove 30, but may be formed only on the inner wall surface of the groove 30. However, the conductive layer 50 is formed so as not to fill the groove 30. That is, a groove (or a concave portion) is formed by the insulating layer 50. Since the insulating layer 40 is interposed between the inner surface of the groove 30 and the conductive layer 50, the electrical connection between the two is cut off.
[0073]
The conductive layer 50 may be formed on the inner surface of the groove 30 so as to extend along the depth direction. Alternatively, the conductive layer 50 may be formed in a land shape (such as a circle or a rectangle). The portion of the inner surface of the groove 30 that is exposed from the conductive layer 50 has the insulating layer 40 exposed.
[0074]
FIG. 6 is a sectional view taken along line VI-VI of FIG. In the example shown in FIG. 6, the conductive layer 50 is formed so as to protrude from the surface of the insulating layer 40 in the direction inside the groove 30.
[0075]
As a modification, as shown in FIG. 7, the conductive layer 54 may be formed so as to be flush with the surface of the insulating layer 44 on the inner surface of the groove 32. In that case, the conductive layer 54 enters the inside of the insulating layer 44. As another modification, as shown in FIG. 8, the conductive layer 56 may be formed so as to be recessed on the inner surface of the groove 34 than the surface of the insulating layer 46. Also in that case, the conductive layer 56 enters the inside of the insulating layer 46. However, the conductive layer 56 is exposed without being covered with the insulating layer 46.
[0076]
According to these modifications, the adhesion between the conductive layers 54 and 56 and the insulating layers 44 and 46 is increased, so that the conductive layers 54 and 56 can be hardly peeled off from the insulating layers 44 and 46. Note that, if necessary, after the conductive layer forming step, the insulating layer forming step may be performed again to form a thick portion around the conductive layer in the insulating layer.
[0077]
As shown in FIG. 5, the conductive layer 50 may be formed continuously from the inner surface of the groove 30 to the first surface 20. That is, the conductive layer 50 may be formed as a wiring so as to extend from the inner surface of the groove 30 toward the first surface 20.
[0078]
As shown in FIG. 5, the conductive layer 50 may be electrically connected to the electrode 14. The conductive layer 50 extends to the first surface 20 and has a connecting portion 52 that is electrically connected to the electrode 14 in the openings 18 and 42 of the plurality of insulating layers 16 and 40. The connection section 52 may be formed so as to cover the electrode 14.
[0079]
As a modification, the conductive layer 50 may not be electrically connected to the electrode 14. That is, the conductive layer 50 may be formed as a dummy wiring (a wiring that does not conduct with the integrated circuit).
[0080]
According to this, the conductive layer 50 can be formed on the side surface of the semiconductor chip. For example, if the conductive layer 50 is electrically connected to the electrode 14, external terminals electrically connected to the integrated circuit 12 can be easily formed on the side surface of the semiconductor chip. Therefore, the degree of freedom of the wiring structure on the semiconductor chip can be improved.
[0081]
Next, the semiconductor substrate 10 is polished to divide it into a plurality of semiconductor chips 70. In the present embodiment, the semiconductor substrate 10 is polished while being held by the sheet 60. The sheet 60 is a holding member for the semiconductor substrate 10.
[0082]
As shown in FIG. 9, a sheet 60 is attached to the semiconductor substrate 10 from the first surface 20. The sheet 60 holds the semiconductor substrate 10 from the first surface 20. The sheet 60 may be an adhesive, for example, a UV tape made of an ultraviolet-curable resin. According to the UV tape, the adhesive force of the sheet 60 can be controlled depending on the presence or absence of the irradiation of the ultraviolet light, so that the UV tape is suitable for holding the semiconductor substrate 10 and peeling the semiconductor chip 70.
[0083]
In the example shown in FIG. 9, a filler 62 such as a resin is provided between the sheet 60 and the semiconductor substrate 10, and the sheet 60 holds the semiconductor substrate 10 via the filler 62. The filler 62 fills at least the groove 30 of the semiconductor substrate 10 and may be provided on the first surface 20 as shown in FIG. The filler 62 may be applied to the semiconductor substrate 10 from the first surface 20 before attaching the sheet 60, or may be provided on the sheet 60 in advance and provided in the groove 30 by attaching the sheet 60. You may.
[0084]
As a modification, the sheet 60 may be attached to the semiconductor substrate 10 without the filler 62. Alternatively, a part of the sheet 60 may be the filler 62.
[0085]
Thus, the semiconductor substrate 10 is polished from the second surface 22 as shown in FIG. That is, the back surface of the semiconductor substrate 10 is polished. For example, the semiconductor substrate 10 to which the sheet 60 is attached is fixed to a stage (not shown), and the semiconductor substrate 10 is mechanically moved from the second surface 22 by a grindstone provided on a polishing jig (not shown). Grind. In this step, the semiconductor substrate 10 is polished to a thickness at which the groove 30 is exposed. Thereby, the semiconductor substrate 10 can be divided into a plurality of semiconductor chips 70 and each semiconductor chip 70 can be thinned.
[0086]
According to this, since the sheet 60 is adhered to the semiconductor substrate 10 from the first surface 20, a plurality of semiconductor chips 70 divided separately can be held collectively. Therefore, the plurality of divided semiconductor chips 70 can be easily handled.
[0087]
In addition, since the filling material 62 is provided in the groove 30 at the time of the polishing step, it is possible to prevent powdery foreign matter generated in the polishing step from entering the groove 30. Therefore, damage to the semiconductor chip 70 and attachment of foreign matter can be prevented, and the reliability of the semiconductor device can be improved.
[0088]
As shown in FIG. 11, if necessary, an insulating layer (third insulating layer) 72 may be formed on the polished surfaces of the plurality of semiconductor chips 70. If the plurality of semiconductor chips 70 are held on the sheet 60, the polished surfaces of the plurality of semiconductor chips 70 can be collectively subjected to insulation treatment. Further, as shown in FIG. 11, if the filler 62 is provided between the plurality of semiconductor chips 70, for example, after forming the insulating layer 72 on the entire surface including the polished surfaces of the plurality of semiconductor chips 70, The portion of the filler 62 in the layer 72 may be removed by etching. The insulating layer 72 may be formed of the same material as the insulating layer 40. By forming the insulating layer 72, electrical conduction between the polished surface of the semiconductor chip 70 and the outside can be cut off. In addition, since the entire surface of the semiconductor portion (for example, silicon) of the semiconductor chip 70 can be covered with the insulating layers 16, 40, and 72, the portion other than the terminals (for example, the conductive layer 50) of the semiconductor chip 70 may be connected to the outside. Electrical conduction can be cut off.
[0089]
After that, the semiconductor chip 70 is separated from the sheet 60. When the filler 62 is provided between the semiconductor chip 70 and the sheet 60, the semiconductor chip 70 is separated from the filler 62. For example, each semiconductor chip 70 is picked up via a sheet 60 by a tool (not shown). Thus, the individual semiconductor chips 70 can be taken out.
[0090]
According to the above steps, the insulating layer 40 is formed on the inner surface of the groove 30 of the semiconductor substrate 10. The inner surface of the groove 30 of the semiconductor substrate 10 corresponds to the side surface of the plurality of semiconductor chips 70. Therefore, in the state of the semiconductor substrate 10, the side surfaces of the plurality of semiconductor chips 70 can be collectively subjected to the insulation treatment. Further, since the insulating layer 40 is formed before the semiconductor substrate 10 is polished, it is possible to manufacture an extremely thin semiconductor device while avoiding cracking and damage of the semiconductor substrate 10.
[0091]
Through the above-described steps, the semiconductor device 1 can be manufactured. The semiconductor device 1 includes a semiconductor chip 70 on which the integrated circuit 12 and the electrode 14 are formed, an insulating layer 40, and a conductive layer 50. The insulating layer 40 is formed continuously from the first surface (the surface on which the integrated circuit and the electrodes are formed in FIG. 12) of the semiconductor chip 70 to the side surface continuous therewith. The insulating layer 40 preferably covers the entire side surface of the semiconductor chip 70. The conductive layer 50 is formed on the insulating layer 40 on the side surface of the semiconductor chip 70. The portion of the side surface of the semiconductor chip 70 exposed from the conductive layer 50 is covered with the insulating layer 40. The conductive layer 50 has an electrical connection 52 with the electrode 14. The other configuration is the content obtained by the above-described manufacturing method.
[0092]
Next, as shown in FIG. 13, a plurality (four in FIG. 13) of semiconductor chips 70 (specifically, the semiconductor device 1) are stacked. The semiconductor chip 70 is stacked on a surface of another semiconductor chip 70 on which the electrodes 14 are formed or on a surface opposite thereto. The plurality of semiconductor chips 70 may be bonded by the bonding material 84. Since the semiconductor chip 70 obtained by the above-described manufacturing method is extremely thin, it is effective to use it in such a three-dimensional mounting form.
[0093]
The plurality of semiconductor chips 70 may be stacked such that the surfaces on which the electrodes 14 are formed face the same direction (the direction opposite to the substrate in FIG. 13). As a modification, the surface of one of the semiconductor chips 70 on which the electrodes 14 are formed may face the opposite direction to the surface of the other semiconductor chip 70 on which the electrodes 14 are formed.
[0094]
As shown in FIG. 13, a plurality of semiconductor chips 70 having substantially the same outer shape may be stacked. In that case, the outer periphery of each semiconductor chip 70 may be made to coincide. In other words, the plurality of semiconductor chips 70 may be stacked such that all of their outer shapes overlap. Alternatively, a plurality of semiconductor chips 70 may be stacked such that a part of their outer shape overlaps.
[0095]
As a modification, a plurality of semiconductor chips 70 having different sizes of outer shapes may be stacked. For example, another semiconductor chip 70 having a smaller outer shape may be sequentially stacked on the semiconductor chip 70 so that the whole becomes a pyramid shape.
[0096]
As shown in FIG. 13, a plurality of semiconductor chips 70 may be mounted on a substrate 80. A wiring pattern 82 is formed on the substrate 80. In the example shown in FIG. 13, the board 80 is a circuit board (for example, a motherboard). Other electronic components (resistors, capacitors, coils, etc.) are also mounted on the circuit board. Alternatively, the substrate 80 may be an interposer of a semiconductor device. In that case, external terminals (for example, solder balls) serving as electrical connection portions are formed on the substrate 80.
[0097]
A plurality of semiconductor chips 70 may be stacked on the substrate 80, or may be mounted on the substrate 80 after being stacked. As shown in FIG. 13, a plurality of semiconductor chips 70 may be mounted on the substrate 80 such that the surface on which the electrodes 14 are formed faces in the opposite direction to the substrate 80. As a modification, the surface on which the electrodes 14 are formed may be directed to the substrate 80.
[0098]
Then, the plurality of semiconductor chips 70 are electrically connected to each other. Specifically, the conductive layer 50 of one of the semiconductor chips 70 is electrically connected to the conductive layer 50 of the other semiconductor chip 70. According to this, after all the semiconductor chips 70 are stacked, the plurality of semiconductor chips 70 are electrically connected to one another at a time, so that the manufacturing process is simple.
[0099]
When a plurality of semiconductor chips 70 are mounted on the substrate 80, the semiconductor chips 70 are electrically connected to the wiring patterns 82. The semiconductor chip 70 may be electrically connected to the wiring pattern 82 via the conductive layer 50.
[0100]
In the present embodiment, the electrical connection process is performed after the plurality of semiconductor chips 70 are stacked and the plurality of semiconductor chips 70 are mounted on the substrate 80. By doing so, the semiconductor device can be manufactured by performing the assembling process and the electrical connection process once each, so that the manufacturing process is extremely simplified.
[0101]
As shown in FIG. 13, the conductive layers 50 of the plurality of semiconductor chips 70 may be electrically connected to each other by the second conductive layer 90. The second conductive layer 90 may be formed to be elongated so as to be a wiring. The second conductive layer 90 is formed on a side surface of at least one semiconductor chip 70. The second conductive layer 90 is formed so as to pass between the semiconductor chips 70. In that case, the second conductive layer 90 may be formed so as to pass through at least one side surface of the semiconductor chip 70 between the semiconductor chips 70. According to this, since the second conductive layer 90 is formed on the side surface of the semiconductor chip 70, an extremely thin semiconductor device can be manufactured without increasing the thickness between the semiconductor chips 70.
[0102]
The second conductive layer 90 may be formed by discharging a solvent 92 containing fine particles of a conductive material. Specifically, the droplet of the solvent 92 is discharged from the nozzle of the droplet discharge device 86. According to this, by discharging the solvent 92, for example, a plurality of second conductive layers 90 can be formed collectively. In addition, if the solvent 92 is discharged according to a predetermined pattern, the second conductive layer 90 can be easily formed without waste.
[0103]
As the material of the solvent 92 containing the fine particles of the conductive material, for example, “Perfect Gold” and “Perfect Silver” manufactured by Vacuum Metallurgy Co., Ltd. may be used.
[0104]
For example, a droplet of the solvent 92 may be ejected by applying an inkjet method. In that case, the droplet discharge device 86 may be an inkjet head. The inkjet head has the structure of an electrostatic actuator, and more specifically, has an actuator having a microstructure formed using a micromachining technique using a micromachining technique. Such a microstructured actuator uses electrostatic force as a driving source. The ink jet head discharges droplets of the solvent 92 from a nozzle using electrostatic force. According to this, it is possible to discharge the material at high speed and economically without waste by applying the technology practically used for the ink jet printer.
[0105]
Alternatively, droplets of the solvent 92 may be discharged by a dispenser. Since the dispenser is easy to handle, the second conductive layer 90 can be formed by a simple process.
[0106]
The second conductive layer 90 may be formed of a brazing material (including both a soft solder and a hard solder). The brazing material may be a solder paste. If possible, the brazing material may be discharged by the droplet discharge device 86.
[0107]
The conductive layer 50 of the semiconductor chip 70 may be electrically connected to the wiring pattern 82 by a solvent 92 containing fine particles of the above-described conductive material, or may be electrically connected to the wiring pattern 82 by a brazing material. . In that case, droplets of the solvent 92 or the brazing material may be ejected by applying an inkjet method. As shown in FIG. 13, when the electrical connection between the semiconductor chips 70 and the electrical connection between the semiconductor chip 70 and the wiring pattern 82 are simultaneously performed, the manufacturing process is simplified.
[0108]
As shown in FIG. 14, if necessary, a conductive portion (such as the conductive layer 50 and the second conductive layer 90) exposed to the outside may be covered with a covering member 88. In the example shown in FIG. 14, the covering member 88 is a film made of an insulating material (for example, resin).
[0109]
According to the method of manufacturing a semiconductor device according to the present embodiment, a plurality of stacked semiconductor chips 70 are electrically connected by conductive layer 50 formed on the side surface of semiconductor chip 70. Since the conductive layer 50 can be formed collectively in the state of the semiconductor substrate 10, the manufacturing process is simple. Since the conductive layer 50 is not covered by another semiconductor chip 70, a semiconductor device (stack-type semiconductor device) having a high degree of freedom in design is not limited by the outer shape of the semiconductor chip 70 and the position of the electrode 14. Can be manufactured. Therefore, a thin and highly integrated semiconductor device can be manufactured by a simple process.
[0110]
Thus, a stack type semiconductor device can be manufactured. In FIG. 14, the semiconductor device is mounted on a circuit board. This semiconductor device includes a plurality of semiconductor chips 70 (specifically, semiconductor device 1 (see FIG. 12)) and a second conductive layer 90. The second conductive layer 90 is formed on a side surface of at least one semiconductor chip 70. According to this, the height of the bumps can be reduced as compared with the case where the upper and lower semiconductor chips 70 are electrically connected via the bumps, so that an extremely thin semiconductor device can be provided. When the substrate 80 is an interposer, the semiconductor device further includes the substrate 80.
[0111]
The semiconductor chip 70 may be, for example, various memories such as a flash memory, an SRAM (Static RAM), or a DRAM (Dynamic RAM), or a microprocessor such as an MPU (Micro Processor Unit) or an MCU (Micro Controller Unit). You may. Examples of the combination of the plurality of semiconductor chips 70 include memories (for example, flash memories and SRAMs, SRAMs and DRAMs) or memories and microprocessors.
[0112]
For example, when at least two of the plurality of semiconductor chips 70 are memories, the conductive layers 50 in the same arrangement are electrically connected by the second conductive layer 90, and information is stored in the memory cells of each memory at the same address. May be read or written. Further, by separating the second conductive layer 90 only at the connection of the chip select terminal, at least two (a plurality of) semiconductor chips 70 can be separated using the conductive layers 50 of the same arrangement. May be controlled. For example, at least one chip select terminal may be formed on each of four sides of the rectangular semiconductor chip 70. If the chip select terminals are formed by changing the arrangement for each side, even if the same semiconductor chips 70 are stacked in design, if each semiconductor chip 70 is rotated by 90 °, the four semiconductor chips 70 are separated. It is possible to control.
[0113]
Other configurations are contents obtained by the above-described manufacturing method.
[0114]
According to the semiconductor device according to the present embodiment, the portion exposed from the conductive layer 50 on the side surface of the semiconductor chip 70 is covered with the insulating layer. The conduction can be cut off. Further, since the conductive layer 50 is not covered with another semiconductor chip 70, a semiconductor device with a high degree of freedom in design can be provided without being limited by the outer shape of the semiconductor chip 70 and the positions of the electrodes 14.
[0115]
Further, the semiconductor device according to the present embodiment includes a configuration derived from any specific item selected from the above-described manufacturing method, and the effect has the above-described effect. The semiconductor device according to the present embodiment includes one manufactured by a method different from the above-described manufacturing method.
[0116]
Next, a modified example of the semiconductor device (stacked semiconductor device) according to the present embodiment will be described. In the following description, portions that are the same as those in other embodiments (the above and other modified examples) will be omitted.
[0117]
FIG. 15 is a diagram illustrating a first modification of the semiconductor device according to the present embodiment. This semiconductor device includes a plurality of semiconductor chips 70 (specifically, the semiconductor device 1 (see FIG. 12)) and a second conductive layer 90, and the electrodes 14 (specifically, on the electrodes) of the uppermost semiconductor chip 70 One end of the wire 100 is bonded to the connection portion 52) of the conductive layer, and the other end is bonded to the wiring pattern 82. The plurality of semiconductor chips 70 and the wires 100 are sealed by a sealing portion 102 made of resin or the like.
[0118]
FIG. 16 is a diagram illustrating a second modification of the semiconductor device according to the present embodiment. This semiconductor device includes a plurality of semiconductor chips 70 (specifically, the semiconductor device 1 (see FIG. 12)) and a second conductive layer 90. The lowermost semiconductor chip 70 is face-down mounted on a substrate 80. I have. For example, a bump 106 may be provided on the electrode 14 of the lowermost semiconductor chip 70, and the bump 106 and the wiring pattern 82 may be electrically connected via a brazing material 108 such as solder. Alternatively, the electrical connection between them may be achieved by metal bonding or bonding with an anisotropic conductive material. If necessary, an underfill material (eg, resin) 104 may be provided between the lowermost semiconductor chip 70 and the substrate 80.
[0119]
As shown in FIG. 16, the surface of at least one (upper three in FIG. 16) of the semiconductor chip 70 on which the electrodes 14 are formed is in the opposite direction to the surface of the lowermost semiconductor chip 70 on which the electrodes 14 are formed. You may turn to. In the example shown in FIG. 16, one end of the wire 100 is bonded to the electrode 14 of the uppermost semiconductor chip 70, and the other end is bonded to the wiring pattern 82. According to this, it is possible to electrically connect the wiring pattern 82 from both the uppermost and lowermost semiconductor chips 70.
[0120]
As shown in FIG. 16, an insulating member 110 (for example, an insulating substrate) may be provided between the semiconductor chips 70. Thereby, it is possible to reliably prevent the semiconductor chips 70 from being electrically short-circuited. The insulating member 110 may overlap the entire outer shape of the semiconductor chip 70 or may partially overlap. As shown in FIG. 16, the insulating member 110 may be provided so as to protrude from the side surface of the semiconductor chip 70. According to this, the projecting portions 112 of the insulating member 110 can prevent, for example, the conductive layers 50 arranged on both sides (upper and lower sides) of the insulating member 110 from being electrically short-circuited. For example, in the case where the second conductive layer 90 is formed by discharging a solvent containing fine particles of a conductive material, the flow of the solvent can be regulated by the protrusions 112, so that the conductive layers 50 are electrically short-circuited to each other. Can be reliably prevented.
[0121]
FIG. 17 is a diagram illustrating a third modification of the semiconductor device according to the present embodiment and corresponds to a cross-sectional view taken along line XVII-XVII of FIG. FIG. 18 is a side view of the semiconductor device. This semiconductor device has an insulating member 110. In the example shown in FIG. 17, an insulating member 110 is provided between the uppermost semiconductor chip 70 and the lower semiconductor chip 70. The insulating member 110 overlaps a part of the outer shape of the semiconductor chip 70 (see FIG. 18). Other configurations are the same as those described in the first modification.
[0122]
As shown in FIG. 18, the plurality of conductive layers 50 are exposed on the side surfaces of the plurality of semiconductor chips 70. The plurality of conductive layers 50 may be arranged in a plurality of rows and a plurality of columns. The plurality of conductive layers 50 are either a first terminal 120 that is electrically connected to the electrode 14 or a second terminal (dummy terminal) 122 that is not electrically connected to the electrode 14.
[0123]
The second conductive layer 90 may be formed to extend in the height direction (the vertical direction in FIG. 18) of the semiconductor chip 70. Then, the second conductive layer 90 electrically connects the conductive layers 50 formed in the width direction of the semiconductor chip 70 (the horizontal direction in FIG. 18). In other words, the second conductive layer 90 electrically connects the plurality of conductive layers 50 arranged in the same column. In that case, the second conductive layer 90 is formed so as to connect at least two first terminals 120. As shown in the rightmost column of FIG. 18, the second conductive layer 90 may pass through at least one second terminal 122 between at least two first terminals 120. According to this, since the second conductive layer 90 does not have to be routed around the second terminal 122, the manufacturing process is simple.
[0124]
The second conductive layer 90 may have a portion extending in the width direction of the semiconductor chip 70. Then, the second conductive layer 90 electrically connects the conductive layers 50 shifted in the width direction of the semiconductor chip 70. In other words, the second conductive layer 90 electrically connects the plurality of conductive layers 50 arranged in different columns (in FIG. 18, adjacent columns, but one or more columns may be skipped). . In that case, a part of the second conductive layer 90 may be formed on the protrusion 112 of the insulating member 110. This can prevent the second conductive layer 90 from being electrically short-circuited with another member (for example, the conductive layer 50 which is not desired to be connected). Note that the second conductive layer 90 may pass through the second terminals 122 arranged on the same row separately from the example shown in FIG.
[0125]
FIG. 19 is a diagram illustrating a fourth modification of the semiconductor device according to the present embodiment, and corresponds to a cross-sectional view taken along line XIX-XIX of FIG. FIG. 20 is a plan view of the semiconductor device. This semiconductor device includes a semiconductor chip 70 (specifically, the semiconductor device 1 (see FIG. 12)), a semiconductor chip 71 having an outer shape smaller than the semiconductor chip 70 (specifically, the semiconductor device 3), and a second conductive layer 90. ,including. The other configuration of the semiconductor device 3 is the same as the configuration of the semiconductor device 1 described above. In the example shown in FIG. 19, a plurality of semiconductor chips 70 are stacked, and a semiconductor chip 71 is further stacked on the uppermost layer. Then, as shown in FIG. 20, in the semiconductor chip 70 in the lowermost layer of the uppermost layer, a part of the conductive layer 50 is routed as a wiring on the surface on which the electrode 14 is formed. In that case, the conductive layer 50 may be formed to extend from the electrode 14 formed at the end of the semiconductor chip 70 to the center. Then, the semiconductor chip 71 may be stacked at the center of the semiconductor chip 70. The second conductive layer 90 electrically connects the conductive layers 50 of the semiconductor chips 70 and 71 to each other.
[0126]
As an electronic apparatus having the above-described semiconductor device, a notebook personal computer 1000 is shown in FIG. 21, and a mobile phone 2000 is shown in FIG.
[0127]
The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the invention includes configurations substantially the same as the configurations described in the embodiments (for example, a configuration having the same function, method, and result, or a configuration having the same object and result). Further, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. Further, the invention includes a configuration having the same operation and effect as the configuration described in the embodiment, or a configuration capable of achieving the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.
[Brief description of the drawings]
FIG. 1 is a diagram showing a part of a semiconductor substrate used in an embodiment of the present invention.
FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a sectional view taken along line VI-VI of FIG. 5;
FIG. 7 is a view showing a modification of the method for manufacturing a semiconductor device according to the embodiment of the present invention;
FIG. 8 is a view showing a modification of the method of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 12 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 13 is a view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 14 is a diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 15 is a diagram showing a first modification of the semiconductor device according to the embodiment of the present invention;
FIG. 16 is a diagram showing a second modification of the semiconductor device according to the embodiment of the present invention;
FIG. 17 is a diagram showing a third modification of the semiconductor device according to the embodiment of the present invention;
FIG. 18 is a diagram showing a third modification of the semiconductor device according to the embodiment of the present invention;
FIG. 19 is a diagram showing a fourth modification of the semiconductor device according to the embodiment of the present invention;
FIG. 20 is a diagram showing a fourth modification of the semiconductor device according to the embodiment of the present invention;
FIG. 21 is a diagram illustrating an electronic apparatus according to an embodiment of the present invention.
FIG. 22 is a diagram illustrating an electronic apparatus according to an embodiment of the present invention.
[Explanation of symbols]
10 semiconductor substrate, 12 integrated circuit, 14 electrodes, 20 first surface,
22 second surface, 30, 32, 34 groove, 40, 44, 46 insulating layer,
50, 54, 56 conductive layer, 70 semiconductor chip, 80 substrate,
82 wiring pattern, 90 second conductive layer, 92 solvent

Claims (36)

(a)集積回路及び電極が形成された半導体基板に第1の面から溝を形成すること、
(b)少なくとも前記溝の内面に絶縁層を形成すること、
(c)前記溝の内面で前記絶縁層上に導電層を形成すること、
(d)前記半導体基板を前記第1の面とは反対側の第2の面から前記溝が露出する厚さまで研磨して、前記半導体基板を、前記導電層が側面に露出してなる複数の前記半導体チップに分割すること、
(e)複数の前記半導体チップを積層すること、及び、
(f)複数の前記半導体チップのうち、いずれかの前記半導体チップの前記導電層と、他の前記半導体チップの前記導電層と、を電気的に接続することを含む半導体装置の製造方法。
(A) forming a groove from a first surface in a semiconductor substrate on which an integrated circuit and an electrode are formed;
(B) forming an insulating layer on at least the inner surface of the groove;
(C) forming a conductive layer on the insulating layer on the inner surface of the groove;
(D) polishing the semiconductor substrate from a second surface opposite to the first surface to a thickness at which the groove is exposed, and polishing the semiconductor substrate so that the conductive layer is exposed on side surfaces; Dividing into the semiconductor chips,
(E) stacking a plurality of the semiconductor chips, and
(F) A method for manufacturing a semiconductor device, comprising electrically connecting the conductive layer of any one of the semiconductor chips to the conductive layer of another of the plurality of semiconductor chips.
請求項1記載の半導体装置の製造方法において、
前記(b)工程で、前記絶縁層を、前記溝の内面から前記第1の面にかけて連続的に形成する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step (b), the insulating layer is continuously formed from an inner surface of the groove to the first surface.
請求項1又は請求項2に記載の半導体装置の製造方法において、
前記(c)工程で、前記導電層を前記溝の内面から前記第1の面にかけて連続的に形成する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein in the step (c), the conductive layer is continuously formed from the inner surface of the groove to the first surface.
請求項1から請求項3のいずれかに記載の半導体装置の製造方法において、
前記(c)工程で、前記導電層を前記電極に電気的に接続させる半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the conductive layer is electrically connected to the electrode in the step (c).
請求項1から請求項4のいずれかに記載の半導体装置の製造方法において、
前記(e)工程で、複数の前記半導体チップを、前記電極の形成された面が同一方向を向くように積層する半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 1, wherein
A method of manufacturing a semiconductor device, wherein in the step (e), a plurality of the semiconductor chips are stacked so that surfaces on which the electrodes are formed face in the same direction.
請求項1から請求項4のいずれかに記載の半導体装置の製造方法において、
前記(e)工程で、複数の前記半導体チップを、いずれかの前記半導体チップの前記電極の形成された面が他の前記半導体チップの前記電極の形成された面とは反対方向を向くように積層する半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 1, wherein
In the step (e), the plurality of semiconductor chips are oriented such that the surface of one of the semiconductor chips on which the electrodes are formed faces in the opposite direction to the surface of the other semiconductor chip on which the electrodes are formed. A method for manufacturing a semiconductor device to be laminated.
請求項1から請求項6のいずれかに記載の半導体装置の製造方法において、
前記(e)工程は、前記半導体チップ同士の間に絶縁部材を設けることを含む半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the step (e) includes providing an insulating member between the semiconductor chips.
請求項7記載の半導体装置の製造方法において、
前記(e)工程で、前記絶縁部材を、前記半導体チップの側面よりも突出するように設ける半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 7,
In the method (e), the insulating member is provided so as to protrude from a side surface of the semiconductor chip.
請求項1から請求項8のいずれかに記載の半導体装置の製造方法において、
前記(f)工程は、前記導電層同士を電気的に接続する第2の導電層を、少なくとも1つの前記半導体チップの側面に形成することを含む半導体装置の製造方法。
9. The method for manufacturing a semiconductor device according to claim 1, wherein:
The method of manufacturing a semiconductor device, wherein the step (f) includes forming a second conductive layer that electrically connects the conductive layers on at least one side surface of the semiconductor chip.
請求項9記載の半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、前記半導体チップの高さ方向に延びるように形成することで、前記半導体チップの幅方向に一致してなる前記導電層同士を電気的に接続する半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 9,
In the step (f), the second conductive layer is formed so as to extend in the height direction of the semiconductor chip, thereby electrically connecting the conductive layers formed in the width direction of the semiconductor chip. A method for manufacturing a semiconductor device to be connected.
請求項9記載の半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、前記半導体チップの幅方向に延びる部分を有するように形成することで、前記半導体チップの幅方向にずれてなる前記導電層同士を電気的に接続する半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 9,
In the step (f), the second conductive layer is formed so as to have a portion extending in the width direction of the semiconductor chip, thereby electrically connecting the conductive layers displaced in the width direction of the semiconductor chip. Of manufacturing a semiconductor device connected to a semiconductor device.
請求項8を引用する請求項11記載の半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層の一部を前記絶縁部材の前記突出部に形成する半導体装置の製造方法。
12. The method of manufacturing a semiconductor device according to claim 11, wherein
In the method (f), a part of the second conductive layer is formed on the protruding portion of the insulating member.
請求項9から請求項12のいずれかに記載の半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、ろう材によって形成する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 9, wherein
The method of manufacturing a semiconductor device, wherein in the step (f), the second conductive layer is formed of a brazing material.
請求項9から請求項12のいずれかに記載の半導体装置の製造方法において、
前記(f)工程で、前記第2の導電層を、導電性材料の微粒子を含む溶媒を吐出することで形成する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 9, wherein
In the method (f), the second conductive layer is formed by discharging a solvent containing fine particles of a conductive material.
請求項1から請求項14のいずれかに記載の半導体装置の製造方法において、
少なくとも前記(d)工程後に、
(g)複数の前記半導体チップを基板に搭載すること、及び、
(h)前記半導体チップを前記基板の配線パターンに電気的に接続することをさらに含む半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1, wherein
At least after the step (d),
(G) mounting a plurality of the semiconductor chips on a substrate;
(H) a method for manufacturing a semiconductor device, further comprising electrically connecting the semiconductor chip to a wiring pattern on the substrate.
請求項15記載の半導体装置の製造方法において、
前記(e)及び(g)工程を終了した後に、前記(f)及び(h)工程を行う半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 15,
After the steps (e) and (g) are completed, a method of manufacturing a semiconductor device in which the steps (f) and (h) are performed.
請求項15又は請求項16記載の半導体装置の製造方法において、
前記(h)工程で、前記導電層を、ろう材によって前記配線パターンに電気的に接続する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 15 or 16,
The method of manufacturing a semiconductor device, wherein in the step (h), the conductive layer is electrically connected to the wiring pattern by a brazing material.
請求項15又は請求項16記載の半導体装置の製造方法において、
前記(h)工程で、前記導電層を、導電性材料の微粒子を含む溶媒を吐出することで前記配線パターンに電気的に接続する半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 15 or 16,
In the method for manufacturing a semiconductor device, in the step (h), the conductive layer is electrically connected to the wiring pattern by discharging a solvent containing fine particles of a conductive material.
請求項1から請求項18のいずれかに記載の方法によって製造されてなる半導体装置。A semiconductor device manufactured by the method according to claim 1. 第1の面を有し、集積回路及び電極が形成されるとともに積層されてなる複数の半導体チップと、
前記半導体チップの前記第1の面からそれに連続する側面にかけて連続的に形成された絶縁層と、
前記半導体チップの側面で前記絶縁層上に形成された導電層と、
前記複数の半導体チップのうち、いずれかの半導体チップの前記導電層と、他の半導体チップの前記導電層と、を電気的に接続する第2の導電層と、
を含み、
前記半導体チップの側面の前記導電層から露出する部分は、前記絶縁層で覆われてなり、
前記第2の導電層は、少なくとも1つの半導体チップの側面に形成されてなる半導体装置。
A plurality of semiconductor chips having a first surface, on which an integrated circuit and an electrode are formed and stacked;
An insulating layer formed continuously from the first surface of the semiconductor chip to a side surface continuous with the first surface;
A conductive layer formed on the insulating layer on a side surface of the semiconductor chip,
A second conductive layer that electrically connects the conductive layer of any one of the semiconductor chips and the conductive layer of another semiconductor chip among the plurality of semiconductor chips;
Including
A portion of the side surface of the semiconductor chip exposed from the conductive layer is covered with the insulating layer,
A semiconductor device, wherein the second conductive layer is formed on a side surface of at least one semiconductor chip.
請求項20記載の半導体装置において、
前記導電層は、前記半導体チップの側面から前記第1の面にかけて連続的に形成されてなる半導体装置。
The semiconductor device according to claim 20,
The semiconductor device, wherein the conductive layer is continuously formed from a side surface of the semiconductor chip to the first surface.
請求項20又は請求項21に記載の半導体装置において、
前記導電層は、前記電極に電気的に接続されてなる半導体装置。
22. The semiconductor device according to claim 20, wherein
The semiconductor device, wherein the conductive layer is electrically connected to the electrode.
請求項20から請求項22のいずれかに記載の半導体装置において、
前記複数の半導体チップは、前記電極の形成された面が同一方向を向くように積層されてなる半導体装置。
23. The semiconductor device according to claim 20, wherein
A semiconductor device, wherein the plurality of semiconductor chips are stacked such that surfaces on which the electrodes are formed face in the same direction.
請求項20から請求項22のいずれかに記載の半導体装置において、
前記複数の半導体チップは、いずれかの前記半導体チップの前記電極の形成された面が他の前記半導体チップの前記電極の形成された面とは反対方向を向くように積層されてなる半導体装置。
23. The semiconductor device according to claim 20, wherein
A semiconductor device, wherein the plurality of semiconductor chips are stacked such that a surface of any of the semiconductor chips on which the electrodes are formed faces in a direction opposite to a surface of the other semiconductor chips on which the electrodes are formed.
請求項20から請求項24のいずれかに記載の半導体装置において、
前記半導体チップ同士の間に絶縁部材が設けられてなる半導体装置。
The semiconductor device according to any one of claims 20 to 24,
A semiconductor device comprising an insulating member provided between the semiconductor chips.
請求項25記載の半導体装置において、
前記絶縁部材は、前記半導体チップの側面よりも突出してなる半導体装置。
26. The semiconductor device according to claim 25,
The semiconductor device, wherein the insulating member protrudes from a side surface of the semiconductor chip.
請求項20から請求項26のいずれかに記載の半導体装置において、
前記第2の導電層は、前記半導体チップの高さ方向に延びてなり、前記半導体チップの幅方向に一致してなる前記導電層同士を電気的に接続する半導体装置。
The semiconductor device according to any one of claims 20 to 26,
The semiconductor device, wherein the second conductive layer extends in a height direction of the semiconductor chip, and electrically connects the conductive layers formed in a width direction of the semiconductor chip.
請求項20から請求項26のいずれかに記載の半導体装置において、
前記第2の導電層は、前記半導体チップの幅方向に延びる部分を有し、前記半導体チップの幅方向にずれてなる前記導電層同士を電気的に接続する半導体装置。
The semiconductor device according to any one of claims 20 to 26,
The semiconductor device, wherein the second conductive layer has a portion extending in the width direction of the semiconductor chip, and electrically connects the conductive layers that are shifted in the width direction of the semiconductor chip.
請求項26を引用する請求項28記載の半導体装置において、
前記第2の導電層の一部は、前記絶縁部材の前記突出部に形成されてなる半導体装置。
28. The semiconductor device according to claim 28, wherein claim 26 is cited.
A semiconductor device in which a part of the second conductive layer is formed on the protrusion of the insulating member.
請求項20から請求項29のいずれかに記載の半導体装置において、
前記第2の導電層は、ろう材によって形成されてなる半導体装置。
The semiconductor device according to any one of claims 20 to 29,
The semiconductor device, wherein the second conductive layer is formed of a brazing material.
請求項20から請求項29のいずれかに記載の半導体装置において、
前記第2の導電層は、導電性材料の微粒子を含む溶媒によって形成されてなる半導体装置。
The semiconductor device according to any one of claims 20 to 29,
The semiconductor device, wherein the second conductive layer is formed of a solvent containing fine particles of a conductive material.
請求項20から請求項31のいずれかに記載の半導体装置において、
配線パターンが形成された基板をさらに含み、
前記複数の半導体チップは、前記基板に搭載されるとともに、前記導電層を介して前記配線パターンに電気的に接続されてなる半導体装置。
The semiconductor device according to any one of claims 20 to 31,
Further comprising a substrate on which a wiring pattern is formed,
A semiconductor device, wherein the plurality of semiconductor chips are mounted on the substrate and electrically connected to the wiring pattern via the conductive layer.
請求項20から請求項32のいずれかに記載の半導体装置において、
前記複数の半導体チップの外形の大きさは、ほぼ同じである半導体装置。
The semiconductor device according to any one of claims 20 to 32,
A semiconductor device in which the plurality of semiconductor chips have substantially the same outer dimensions.
請求項20から請求項32のいずれかに記載の半導体装置において、
前記複数の半導体チップのうち、いずれかの前記半導体チップの外形の大きさは、他の前記半導体チップの外形の大きさとは異なっている半導体装置。
The semiconductor device according to any one of claims 20 to 32,
A semiconductor device in which the size of the outer shape of one of the plurality of semiconductor chips is different from the size of the outer shape of the other semiconductor chips.
請求項19から請求項34のいずれかに記載の半導体装置が実装された回路基板。A circuit board on which the semiconductor device according to claim 19 is mounted. 請求項19から請求項34のいずれかに記載の半導体装置を有する電子機器。An electronic apparatus comprising the semiconductor device according to claim 19.
JP2002277454A 2002-09-24 2002-09-24 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus Expired - Fee Related JP4081666B2 (en)

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US20040142509A1 (en) 2004-07-22
US7180168B2 (en) 2007-02-20

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