JP2004119442A - Method for manufacturing wiring board with solder bump - Google Patents

Method for manufacturing wiring board with solder bump Download PDF

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Publication number
JP2004119442A
JP2004119442A JP2002277127A JP2002277127A JP2004119442A JP 2004119442 A JP2004119442 A JP 2004119442A JP 2002277127 A JP2002277127 A JP 2002277127A JP 2002277127 A JP2002277127 A JP 2002277127A JP 2004119442 A JP2004119442 A JP 2004119442A
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Japan
Prior art keywords
solder
layer
paste
bonding pad
wiring board
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JP2002277127A
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JP3967989B2 (en
Inventor
Yuji Tanaka
田中 祐二
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Kyocera Corp
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Kyocera Corp
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Priority to JP2002277127A priority Critical patent/JP3967989B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

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  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board with a solder bump in which a void is hardly formed in the solder bump and which can rigidly connect an electrode of an electronic component to a solder connecting pad via the solder bump. <P>SOLUTION: The method for manufacturing the wiring board with the solder bump includes the steps of forming a solder resistant resin layer 4 having a plurality of solder connecting pads 3 and openings 4a for exposing a centers of the pads 3 on a surface of an insulating board 2, then coating the pads 3 with a solder plating layer 21, then coating the layer 21 with a solder paste 22, and then heating to melt the solder in the paste 2 and the layer 21 to form the solder bumps 5. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子や抵抗器等の電子部品を搭載するための半田バンプ付き配線基板およびその製造方法に関する。
【0002】
【従来の技術】
近年、半導体素子や抵抗器等の電子部品を搭載するために用いられる配線基板には、ガラス基材および熱硬化性樹脂から成る絶縁板と銅箔等から成る配線導体層とを交互に複数積層して成るプリント基板や、絶縁板上に熱硬化性樹脂およびフィラーから成る絶縁層と銅めっき層から成る配線導体層とを複数積層して成るビルドアップ基板が用いられてきている。そして、このようなプリント基板やビルドアップ基板等の配線基板の上面には、半導体素子等の電子部品の電極を接続するための半田接合パッドおよびこの半田接合パッドの中央部を露出させる耐半田樹脂層が被着形成されており、さらに、耐半田樹脂層から露出した半田接合パッド上には電子部品と半田接合パッドとを接合するための半田バンプが形成されている。
【0003】
そして、このような半田バンプ付きの配線基板においては、電子部品をその各電極がそれぞれ対応する半田バンプに当接するようにして配線基板の上面に載置するとともに、これらを例えば電気炉等の加熱装置で加熱して半田バンプを溶融させて半田バンプと電子部品の電極とを接合させることによって、電子部品が配線基板上に実装される。
【0004】
なお、このような半田バンプ付きの配線基板は、内部および/または表面に複数の配線導体を有する絶縁基板の表面に、配線導体に接続された略円形の複数の半田接合パッドおよびこの半田接合パッドの中央部を露出させる開口部を有する耐半田樹脂層を被着させ、次に前記半田接合パッド上にフラックスおよび半田粉末から成る半田ペーストを従来周知のスクリーン印刷法を採用して半田バンプに対応する量だけ一度に印刷塗布するとともにこれを加熱して半田ペースト中のフラックスを気化除去するとともに半田ペースト中の半田粉末を溶融させて半田接合パッド上に半田バンプを形成することによって製作されている(特許文献1)。
【0005】
【特許文献1】
特開平6−122090号公報
【0006】
【発明が解決しようとする課題】
しかしながら、従来の半田バンプ付き配線基板によれば、半田接合パッド上に印刷塗布した半田ペースト中のフラックスを気化除去するとともに半田ペースト中の半田粉末を溶融させて半田接合パッド上に半田バンプを形成する際に、一度に塗布した半田ペースト中に含有されるフラックスの一部が溶融した半田中に取り残されて半田バンプ中にボイドを発生させてしまいやすく、半田バンプ中にそのようなボイドが多量に発生すると、電子部品の電極と半田接合パッドとを半田バンプを介して接合する際に、電子部品の電極と半田接合パッドとの接合がボイドにより阻害されたり、半田バンプの強度が弱いものとなって、電子部品の電極と半田接合パッドとを半田バンプを介して強固に接合することができなくなってしまうという問題点を有していた。
【0007】
本発明は、かかる従来の問題点に鑑み案出されたものであり、その目的は、半田接合パッド上に形成された半田バンプ中にボイドが形成されにくく、電子部品の電極と半田接合パッドとを半田バンプを介して強固に接合することが可能な半田バンプ付き配線基板の製造方法を提供することにある。
【0008】
【課題を解決するための手段】
本発明の半田バンプ付き配線基板の製造方法は、配線導体を有する絶縁基板の表面に、前記配線導体に接続された複数の半田接合パッドおよびこの半田接合パッドの中央部を露出させる開口部を有する耐半田樹脂層を形成する工程と、前記開口部内に露出した前記半田接合パッド上に半田めっき層を被着させる工程と、この半田めっき層上に半田ペーストを塗布する工程と、この半田ペースト中の半田および前記半田めっき層を加熱溶融させて前記半田接合パッド上に半田バンプを形成する工程とを行なうことを特徴とするものである。
【0009】
本発明の半田バンプ付き配線基板の製造方法によれば、耐半田樹脂層の開口部内に露出した半田接合パッド上に半田めっき層を被着させる工程と、半田めっき層上に半田ペーストを塗布する工程と、この半田ペースト中の半田および半田めっき層を加熱溶融させて半田接合パッド上に半田バンプを形成する工程とを行なうことから、半田接合パッド上に被着された半田めっき層が溶融することにより半田接合パッドと半田バンプとが良好に接合されるとともに、その上に塗布された半田ペーストによりボイドの少ない十分な高さの半田バンプを形成することができる。
【0010】
【発明の実施の形態】
次に、本発明を添付の図面に基づき詳細に説明する。図1は、本発明の製造方法により製作される半田バンプ付き配線基板の実施の形態の一例を示す断面図である。また、図2は本発明の半田バンプ付き配線基板の製造方法を説明するための工程毎の要部拡大断面図である。
【0011】
図1において、1は絶縁基板、2は配線導体、3は半田接合パッド、4は耐半田樹脂層、5は半田バンプ、6は外部リードピンであり、主にこれらで本例の半田バンプ付き配線基板が構成されている。なお、この例では外部リードピン6を有する例を示したが、外部リードピン6は必ずしも必要ではなく、外部リードピン6に代えて例えば半田から成る外部接続用の端子を設けてもよい。
【0012】
絶縁基板1は、例えばガラス繊維を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状の芯体1aの上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る絶縁層1bをそれぞれ複数層ずつ積層して成り、芯体1aや各絶縁層1bの表面には銅箔や銅めっき膜等の導体層から成る複数の配線導体2が形成されている。
【0013】
絶縁基板1を構成する芯体1aは、厚みが0.3〜1.5mm程度であり、その上面から下面にかけて直径が0.1〜1.0mm程度の複数の貫通孔7を有している。そして、各貫通孔7の内壁には配線導体2の一部が被着されており、芯体1aの上下面に形成された配線導体2同士が貫通孔7内の配線導体2を介して電気的に接続されている。
【0014】
このような芯体1aは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートを熱硬化させた後、これに上面から下面にかけて貫通孔7用のドリル加工を施すことにより製作される。なお、芯体1aの上下面の配線導体2は、芯体1a用のシートの上下全面に厚みが3〜50μm程度の銅箔を貼着しておくとともに、この銅箔をシートの硬化後にエッチング加工することにより芯体1aの上下面に所定のパターンに形成される。また、貫通孔7内の配線導体2は、芯体1aに貫通孔7を設けた後に、この貫通孔7の内壁に無電解めっき法および電解めっき法により厚みが3〜50μm程度の銅めっき膜を析出させることにより貫通孔7の内壁に被着形成される。
【0015】
さらに、芯体1aは、その貫通孔7の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱8が充填されている。樹脂柱8は、貫通孔7を塞ぐことにより貫通孔7の直上および直下に絶縁層1bを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂を貫通孔7内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。そして、この樹脂柱8を含む芯体1aの上下面に絶縁層1bが積層されている。
【0016】
芯体1aの上下面に積層された絶縁層1bは、それぞれの厚みが20〜60μm程度であり、各層の上面から下面にかけて直径が30〜100μm程度の複数の貫通孔9を有しており、これらの貫通孔9内には配線導体2の一部が被着形成されている。これらの絶縁層1bは、配線導体2を高密度に配線するための絶縁間隔を提供するためのものである。そして、上層の配線導体2と下層の配線導体2とを貫通孔9内の配線導体2を介して電気的に接続することにより高密度配線を立体的に形成可能としている。
【0017】
このような絶縁層1bは、厚みが20〜60μm程度の未硬化の熱硬化性樹脂のフィルムを芯体1a上下面に貼着し、これを熱硬化させるとともにレーザ加工により貫通孔9を穿孔し、さらにその上に同様にして次の絶縁層1bを順次積み重ねることによって形成される。なお、各絶縁層1b表面および貫通孔内に被着された配線導体2は、各絶縁層1bを形成する毎に各絶縁層1bの表面および貫通孔9内に5〜50μm程度の厚みの銅めっき膜を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。
【0018】
さらに、最表層の絶縁層1b上には耐半田樹脂層4が被着されている。耐半田樹脂層4は、例えばアクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを30〜70質量%程度分散させた絶縁材料から成り、表層の配線導体2同士の電気的絶縁信頼性を高めるとともに、後述する半田接合パッド3やピン接合パッド10の絶縁基板1への接合強度を大きなものとする作用をなす。
【0019】
このような耐半田樹脂層4は、その厚みが10〜50μm程度であり、感光性を有する耐半田樹脂層4用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最表層の絶縁層1b上に塗布し、これを乾燥させた後、露光および現像処理を行なって半田接合パッド3やピン接合パッド10の中央部を露出させる開口部4a、4bを形成した後、これを熱硬化させることによって形成される。あるいは、耐半田樹脂層4用の未硬化の樹脂フィルムを最上層の絶縁層1b上に貼着した後、これを熱硬化させ、しかる後、半田接合パッド3やピン接合パッド10に対応する位置にレーザビームを照射し、硬化した樹脂フィルムを部分的に除去することによって半田接合パッド3やピン接合パッド10を露出させる開口部4a、4bを有するように形成される。
【0020】
また、絶縁基板1の上面から下面にかけて形成された配線導体2は、電子部品の各電極を外部電気回路基板に接続するための導電路として機能し、絶縁基板1の上面の実装領域に設けられた部位の一部が電子部品の各電極に例えば鉛−錫合金から成る半田バンプ5を介して接合される半田接合パッド3を、絶縁基板1の下面に露出した部位の一部が外部電気回路基板に接続される外部リードピン6を接合するためのピン接合パッド10を形成している。このような半田接合パッド3やピン接合パッド10は、配線導体2に接続された導体層から成る略円形のパターンの外周部を耐半田樹脂層4により15〜35μm程度の幅で被覆してその外周縁を画定することによりその直径が、半田接合パッド3であれば70〜200μm程度に、ピン接合パッド10であれば0.5〜2.5mm程度になるように形成されている。なお、このように半田接合パッド3およびピン接合パッド10の外周部を耐半田樹脂層4により被覆することによって、半田接合パッド3同士やピン接合パッド10同士の電気的な短絡が有効に防止されるとともに、半田接合パッド3やピン接合パッド10の絶縁基板1に対する接合強度が高いものとなっている。
【0021】
なお、通常であれば、半田接合パッド3およびピン接合パッド10の露出する表面には、半田接合パッド3やピン接合パッド10の酸化腐蝕の防止と半田バンプ5や外部リードピン6との接続を良好にするために、ニッケル、金等の良導電性で耐腐蝕性に優れた金属をめっき法により1〜20μmの厚さに被着することが好ましい。
【0022】
また、半田接合パッド3には、半田バンプ5が固着形成されている。半田バンプ5は、鉛−錫合金等の半田材料から成り、半田接合パッド3と電子部品とを電気的および機械的に接続するための端子として機能し、電子部品の各電極がそれぞれ対応する半田バンプ5に当接するようにして絶縁基板1上に電子部品を載置するとともに、これらを例えば電気炉などの加熱装置で加熱して半田バンプ5を溶融させることにより半田バンプ5と電子部品の電極とが接続される。
【0023】
また、ピン接合パッド10は、銅や鉄−ニッケル−コバルト合金等の金属から成る外部リードピン6が半田バンプ5よりも融点が高い半田を介して接合されている。外部リードピン6は、絶縁基板1に実装される電子部品を外部電気回路基板に電気的に接続するための端子部材として機能し、外部リードピン6を外部電気回路基板の配線導体に半田やソケットを介して接続することにより、電子部品が外部電気回路に電気的に接続されることとなる。
【0024】
次に本発明の半田バンプ付き配線基板の製造方法によって半田接合パッド3上に半田バンプ5を形成する方法について説明する。
【0025】
先ず、図2(a)に示すように、配線導体2を有する絶縁基板1の上面に、配線導体2に接続された半田接合パッド3およびこの半田接合パッド3の中央部を露出させる開口部4aを有する耐半田樹脂層4を形成する。半田接続パッド3は、絶縁基板1を構成する最上層の絶縁層1b上に5〜20μm程度の厚みの銅めっき膜を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。また、耐半田樹脂層4は、感光性を有する耐半田樹脂層4用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最上層の絶縁層1b上に塗布し、これを乾燥させた後、露光および現像処理を行なって半田接合パッド3の中央部を露出させる開口部4aを形成した後、これを熱硬化させることによって形成される。あるいは、耐半田樹脂層4用の未硬化の樹脂フィルムを最上層の絶縁層1b上に貼着した後、これを熱硬化させ、しかる後、半田接合パッド3に対応する位置にレーザビームを照射し、硬化した樹脂フィルムを部分的に除去することによって半田接合パッド3を露出させる開口部4aを有するように形成される。なお、耐半田樹脂層4の開口部4aから露出した半田接合パッド3の表面には、その酸化腐食を防止するとともに半田バンプ5との接合を強固なものとするために2〜5μmの厚みのニッケルめっき層と0.01〜0.03μmの厚みの金めっき層を電解めっき法や無電解めっき法により順次被着させる。
【0026】
次に、図2(b)に示すように、耐半田樹脂層4の開口部4aから露出した半田接合パッド3上に例えば、鉛−錫合金から成る半田めっき層21を被着させる。半田接合パッド3上に半田めっき層21を被着させるには、半田接続パッドおよび耐半田樹脂層が形成された絶縁基板1を、例えば、ホウフッ化第一錫130g/l、ホウフッ化第一鉛50g/l、ホウフッ化第一水素酸125g/l、ホウフッ化第一ホウ素25g/lから成る温度が20〜30℃の半田めっき液中に1〜5分間程度浸漬すればよい。
【0027】
このとき、半田めっき層21の高さを、耐半田樹脂層4の高さに対して−5μm〜+15μmの範囲としておくことが好ましい。半田めっき層21の高さが耐半田樹脂層4の高さに対して−5μmより低い場合、半田めっき層21の上に後述する第二の半田ペースト22を印刷塗布するとともにそれを加熱して半田バンプ5を形成する際に、半田めっき層21と耐半田樹脂層4との間に形成される段差部により半田バンプ5の内部にフラックスが取り残されてボイドが発生しやすくなる傾向にあり、他方、+15μmより高い場合、半田ペースト22を印刷塗布する際に印刷マスクと絶縁基板1の間に隙間が生じて半田塗布量にばらつきが生じるという傾向にあるからである。
【0028】
次に、図2(c)に示すように、半田めっき層21の上に半田ペースト22を例えば従来周知のスクリーン印刷法を採用して30〜50μmの厚みに塗布する。半田粉末としては、例えば粒径が5〜25μm程度の鉛−錫合金等の半田から成る球状の粉末が使用される。なお、半田ペースト22中のフラックス量が5質量%未満の場合、半田ペースト22にペーストとしての適度な粘度を付与することができずに半田ペースト22を半田めっき層21上に良好に塗布することが困難となる傾向にあり、他方、15質量%を超えると、後述するように半田ペースト22および半田めっき層21を加熱して半田ペースト22中のフラックスを気化除去するとともに半田ペースト22中の半田粉末および半田めっき層21を溶融させて半田バンプ5を形成する際に半田ペースト22中のフラックス量が多いので気化したフラックスが半田バンプ5内に取り残されて多量のボイドが発生しやすくなる傾向にある。したがって、半田ペースト22の中のフラックス量は5〜15質量%の範囲が好ましい。
【0029】
次に図2(d)に示すように、半田ペースト22および半田めっき層21を加熱して半田ペースト22中のフラックスを気化除去するとともに、半田ペースト22中の半田粉末および半田めっき層21を溶融させて半田接合パッド3上に半田バンプ5を形成する。このとき、半田接合パッド3上には予め半田めっき層21が被着されていることから、その半田めっき層21が溶融することにより半田接合パッド3と半田バンプ5とが良好に接合される。また、半田めっき層21により半田接合パッド3と半田バンプ5とが良好に接合されることから、半田ペースト22中に多量のフラックスを含有させる必要がなく半田ペースト22および半田めっき層21を加熱して半田ペースト22中のフラックスを気化除去するとともに半田ペースト22中の半田粉末および半田めっき層21を溶融させて半田バンプ5を形成する際に気化したフラックスが半田バンプ5内に取り残されにくく、ボイドの少ない半田バンプ5を形成することができる。
【0030】
かくして、本発明により提供される半田バンプ付き配線基板によると、配線基板1の上面に電子部品をその電極が半田バンプ5に当接するようにして載置するとともに、半田バンプ5を溶融させて電子部品の電極と半田接合パッド3とを接合させることにより製品としての電子装置となる。
【0031】
なお、本発明は、上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更が可能であることはいうまでもない。
【0032】
【発明の効果】
本発明の半田バンプ付き配線基板の製造方法によれば、耐半田樹脂層の開口部内に露出した半田接合パッド上に半田めっき層を被着させ、次にその半田めっき層上に半田ペーストを印刷するとともに半田ペースト中の半田および半田めっき層を溶融させて半田接合パッド上に半田バンプを形成することから、半田接合パッド上に被着された半田めっき層が溶融することにより半田接合パッドと半田バンプとが良好に接合されるとともに、その上に塗布された半田ペーストによりボイドの少ない十分な高さの半田バンプを形成することができる。したがって、電子部品の電極と半田接合パッドとを半田バンプを介して強固に接合することが可能な半田バンプ付き配線基板を提供することができる。
【図面の簡単な説明】
【図1】本発明の製造方法により製造される半田バンプ付き配線基板の実施形態の一例を示す断面図である。
【図2】(a)〜(d)は本発明の半田バンプ付き配線基板の製造方法を説明するための工程毎の要部拡大断面図である。
【符号の説明】
1・・・・・絶縁基板
2・・・・・配線導体
3・・・・・半田接合パッド
4・・・・・耐半田樹脂層
4a・・・・耐半田樹脂層の開口部
5・・・・・半田バンプ
21・・・・・半田めっき層
22・・・・・半田ペースト
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board with solder bumps for mounting electronic components such as semiconductor elements and resistors, and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, wiring boards used for mounting electronic components such as semiconductor elements and resistors have been alternately laminated with an insulating plate made of a glass base material and a thermosetting resin and a wiring conductor layer made of a copper foil or the like. And a build-up board in which a plurality of insulating layers made of a thermosetting resin and a filler and a wiring conductor layer made of a copper plating layer are laminated on an insulating plate. On the upper surface of a wiring board such as a printed board or a build-up board, a solder bonding pad for connecting an electrode of an electronic component such as a semiconductor element and a solder-resistant resin for exposing a central portion of the solder bonding pad are provided. A layer is formed, and a solder bump for joining the electronic component and the solder joint pad is formed on the solder joint pad exposed from the solder resistant resin layer.
[0003]
In such a wiring board with solder bumps, the electronic component is placed on the upper surface of the wiring board such that each electrode thereof comes into contact with the corresponding solder bump, and these are heated by, for example, an electric furnace. The electronic component is mounted on the wiring board by heating the device to melt the solder bump and joining the solder bump and the electrode of the electronic component.
[0004]
Note that such a wiring board with solder bumps has a plurality of substantially circular solder bonding pads connected to the wiring conductors and the solder bonding pads on the surface of an insulating substrate having a plurality of wiring conductors inside and / or on the surface. A solder-resistant resin layer having an opening for exposing the central portion of the solder bump is applied, and a solder paste made of flux and solder powder is applied to the solder bumps on the solder bonding pad by using a conventionally known screen printing method. It is manufactured by printing and applying a single amount at a time and heating it to vaporize and remove the flux in the solder paste and melt the solder powder in the solder paste to form solder bumps on the solder joint pads. (Patent Document 1).
[0005]
[Patent Document 1]
JP-A-6-122090
[Problems to be solved by the invention]
However, according to the conventional wiring board with solder bumps, the flux in the solder paste printed and applied on the solder bonding pads is vaporized and removed, and the solder powder in the solder paste is melted to form solder bumps on the solder bonding pads. When soldering, a part of the flux contained in the solder paste applied at a time is likely to be left in the molten solder and voids are likely to be generated in the solder bumps. When bonding occurs between the electrodes of the electronic component and the solder bonding pad via the solder bumps, the bonding between the electrode of the electronic component and the solder bonding pad may be hindered by voids or the strength of the solder bump may be weak. As a result, it becomes impossible to firmly join the electrodes of the electronic component and the solder joint pads via the solder bumps. It was.
[0007]
The present invention has been devised in view of such a conventional problem, and an object of the present invention is to prevent a void from being formed in a solder bump formed on a solder bonding pad, and to form an electrode of an electronic component and a solder bonding pad. Is to provide a method for manufacturing a wiring board with solder bumps, which can firmly join the wiring boards via solder bumps.
[0008]
[Means for Solving the Problems]
The method for manufacturing a wiring board with solder bumps according to the present invention includes, on a surface of an insulating substrate having a wiring conductor, a plurality of solder bonding pads connected to the wiring conductor and an opening exposing a central portion of the solder bonding pad. A step of forming a solder-resistant resin layer, a step of applying a solder plating layer on the solder bonding pad exposed in the opening, a step of applying a solder paste on the solder plating layer, Forming a solder bump on the solder joint pad by heating and melting the solder and the solder plating layer.
[0009]
According to the method for manufacturing a wiring board with solder bumps of the present invention, a step of applying a solder plating layer on a solder bonding pad exposed in an opening of a solder resistant resin layer, and applying a solder paste on the solder plating layer Since the step and the step of heating and melting the solder and the solder plating layer in the solder paste to form a solder bump on the solder joint pad are performed, the solder plating layer applied on the solder joint pad melts. As a result, the solder bonding pad and the solder bump are satisfactorily bonded, and the solder paste applied thereon can form a solder bump having a sufficient height with few voids.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing an example of an embodiment of a wiring board with solder bumps manufactured by the manufacturing method of the present invention. FIG. 2 is an enlarged cross-sectional view of a main part in each step for explaining a method of manufacturing a wiring board with solder bumps according to the present invention.
[0011]
In FIG. 1, reference numeral 1 denotes an insulating substrate, 2 denotes a wiring conductor, 3 denotes a solder joint pad, 4 denotes a solder-resistant resin layer, 5 denotes a solder bump, and 6 denotes an external lead pin. A substrate is configured. In this example, the example having the external lead pins 6 is shown. However, the external lead pins 6 are not always necessary, and instead of the external lead pins 6, an external connection terminal made of, for example, solder may be provided.
[0012]
The insulating substrate 1 is formed by impregnating a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin into a glass fabric in which glass fibers are woven vertically and horizontally. A plurality of insulating layers 1b each made of a thermosetting resin such as a resin, and a plurality of wiring conductors formed of a conductive layer such as a copper foil or a copper plating film on the surface of the core body 1a or each insulating layer 1b; 2 are formed.
[0013]
The core 1a constituting the insulating substrate 1 has a thickness of about 0.3 to 1.5 mm and has a plurality of through holes 7 with a diameter of about 0.1 to 1.0 mm from the upper surface to the lower surface. . A part of the wiring conductor 2 is attached to the inner wall of each through hole 7, and the wiring conductors 2 formed on the upper and lower surfaces of the core 1 a are electrically connected to each other through the wiring conductor 2 in the through hole 7. Connected.
[0014]
Such a core 1a is manufactured by thermally curing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then performing drilling for the through holes 7 from the upper surface to the lower surface. . The wiring conductors 2 on the upper and lower surfaces of the core 1a are attached with copper foil having a thickness of about 3 to 50 μm on the entire upper and lower surfaces of the sheet for the core 1a, and the copper foil is etched after the sheet is cured. By processing, a predetermined pattern is formed on the upper and lower surfaces of the core 1a. The wiring conductor 2 in the through-hole 7 is formed by forming a through-hole 7 in the core 1a and then forming a copper plating film having a thickness of about 3 to 50 μm on the inner wall of the through-hole 7 by electroless plating and electrolytic plating. Is deposited on the inner wall of the through-hole 7.
[0015]
Further, the core 1a is filled with a resin column 8 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin inside the through hole 7. The resin pillar 8 is for enabling the insulating layer 1b to be formed directly above and directly below the through hole 7 by closing the through hole 7, and the uncured paste-like thermosetting resin is placed in the through hole 7. It is formed by filling by a screen printing method, thermally curing the material, and then polishing the upper and lower surfaces thereof to be substantially flat. An insulating layer 1b is laminated on the upper and lower surfaces of the core 1a including the resin columns 8.
[0016]
The insulating layer 1b laminated on the upper and lower surfaces of the core 1a has a thickness of about 20 to 60 μm, and has a plurality of through holes 9 having a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. A part of the wiring conductor 2 is formed in these through holes 9. These insulating layers 1b are for providing an insulating interval for wiring the wiring conductors 2 at high density. By electrically connecting the upper layer wiring conductor 2 and the lower layer wiring conductor 2 via the wiring conductor 2 in the through-hole 9, high-density wiring can be formed three-dimensionally.
[0017]
Such an insulating layer 1b is formed by attaching an uncured thermosetting resin film having a thickness of about 20 to 60 μm to the upper and lower surfaces of the core body 1a, thermosetting the same, and forming the through holes 9 by laser processing. The insulating layer 1b is formed by successively stacking the next insulating layers 1b in a similar manner. The wiring conductor 2 attached to the surface of each insulating layer 1b and the inside of the through-hole has a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and inside the through-hole 9 every time the insulating layer 1b is formed. It is formed by applying a plating film to a predetermined pattern by a known pattern forming method such as a semi-additive method or a subtractive method.
[0018]
Further, a solder-resistant resin layer 4 is provided on the outermost insulating layer 1b. The solder-resistant resin layer 4 is made of, for example, an insulating material in which an inorganic powder filler such as silica or talc is dispersed in an acrylic-modified epoxy resin by about 30 to 70% by mass, and improves the electrical insulation reliability between the surface wiring conductors 2. At the same time, it acts to increase the bonding strength of the solder bonding pad 3 and the pin bonding pad 10 to be described later to the insulating substrate 1.
[0019]
Such a solder-resistant resin layer 4 has a thickness of about 10 to 50 μm. The uncured resin paste for the solder-resistant resin layer 4 having photosensitivity is formed on the outermost layer by using a roll coater method or a screen printing method. After coating on the insulating layer 1b and drying it, exposure and development treatments are performed to form openings 4a and 4b for exposing the central portions of the solder bonding pads 3 and the pin bonding pads 10, and then, heat is applied. It is formed by curing. Alternatively, after an uncured resin film for the solder-resistant resin layer 4 is adhered on the uppermost insulating layer 1b, this is thermally cured, and then the position corresponding to the solder bonding pad 3 or the pin bonding pad 10 is set. Is formed so as to have openings 4a and 4b for exposing the solder bonding pads 3 and the pin bonding pads 10 by irradiating a laser beam to the resin film and partially removing the cured resin film.
[0020]
The wiring conductor 2 formed from the upper surface to the lower surface of the insulating substrate 1 functions as a conductive path for connecting each electrode of the electronic component to an external electric circuit board, and is provided in a mounting area on the upper surface of the insulating substrate 1. A part of the exposed part is connected to each electrode of the electronic component via a solder bump 5 made of, for example, a lead-tin alloy. A pin bonding pad 10 for bonding the external lead pins 6 connected to the substrate is formed. Such a solder bonding pad 3 or a pin bonding pad 10 is formed by covering an outer peripheral portion of a substantially circular pattern formed of a conductor layer connected to the wiring conductor 2 with a solder resin layer 4 to a width of about 15 to 35 μm. By defining the outer peripheral edge, the diameter is about 70 to 200 μm for the solder bonding pad 3 and about 0.5 to 2.5 mm for the pin bonding pad 10. By covering the outer peripheral portions of the solder bonding pads 3 and the pin bonding pads 10 with the solder-resistant resin layer 4, an electrical short circuit between the solder bonding pads 3 and between the pin bonding pads 10 is effectively prevented. In addition, the bonding strength of the solder bonding pad 3 and the pin bonding pad 10 to the insulating substrate 1 is high.
[0021]
Normally, on the exposed surfaces of the solder bonding pads 3 and the pin bonding pads 10, the prevention of oxidation corrosion of the solder bonding pads 3 and the pin bonding pads 10 and the good connection with the solder bumps 5 and the external lead pins 6 are provided. In this case, it is preferable to apply a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, to a thickness of 1 to 20 μm by plating.
[0022]
The solder bumps 5 are fixedly formed on the solder bonding pads 3. The solder bump 5 is made of a solder material such as a lead-tin alloy, and functions as a terminal for electrically and mechanically connecting the solder joint pad 3 to the electronic component. The electronic components are mounted on the insulating substrate 1 so as to be in contact with the bumps 5, and are heated by a heating device such as an electric furnace to melt the solder bumps 5 so that the solder bumps 5 and the electrodes of the electronic components are melted. And are connected.
[0023]
The pin bonding pad 10 has external lead pins 6 made of a metal such as copper or an iron-nickel-cobalt alloy bonded via solder having a higher melting point than the solder bumps 5. The external lead pin 6 functions as a terminal member for electrically connecting an electronic component mounted on the insulating substrate 1 to an external electric circuit board, and connects the external lead pin 6 to a wiring conductor of the external electric circuit board via solder or a socket. In this case, the electronic component is electrically connected to the external electric circuit.
[0024]
Next, a method for forming the solder bumps 5 on the solder bonding pads 3 by the method for manufacturing a wiring board with solder bumps of the present invention will be described.
[0025]
First, as shown in FIG. 2A, on an upper surface of an insulating substrate 1 having a wiring conductor 2, a solder bonding pad 3 connected to the wiring conductor 2 and an opening 4 a exposing a central portion of the solder bonding pad 3. Is formed. The solder connection pad 3 is formed by forming a copper plating film having a thickness of about 5 to 20 μm on the uppermost insulating layer 1b constituting the insulating substrate 1 into a predetermined pattern by a pattern forming method such as a known semi-additive method or a subtractive method. It is formed by applying. The solder-resistant resin layer 4 is formed by applying an uncured resin paste for the solder-resistant resin layer 4 having photosensitivity to the uppermost insulating layer 1b by using a roll coater method or a screen printing method, and drying the paste. After that, an opening 4a for exposing the central portion of the solder bonding pad 3 is formed by performing exposure and development treatments, and is formed by heat curing. Alternatively, after an uncured resin film for the solder-resistant resin layer 4 is adhered on the uppermost insulating layer 1b, it is thermally cured, and then a laser beam is irradiated to a position corresponding to the solder bonding pad 3. Then, the cured resin film is partially removed to form an opening 4a for exposing the solder bonding pad 3. The surface of the solder bonding pad 3 exposed from the opening 4a of the solder-resistant resin layer 4 has a thickness of 2 to 5 μm in order to prevent its oxidation and corrosion and to make the bonding with the solder bump 5 strong. A nickel plating layer and a gold plating layer having a thickness of 0.01 to 0.03 μm are sequentially deposited by an electrolytic plating method or an electroless plating method.
[0026]
Next, as shown in FIG. 2B, a solder plating layer 21 made of, for example, a lead-tin alloy is applied on the solder bonding pad 3 exposed from the opening 4a of the solder-resistant resin layer 4. In order to apply the solder plating layer 21 on the solder bonding pad 3, the insulating substrate 1 on which the solder connection pad and the solder-resistant resin layer are formed may be formed, for example, by using stannous borofluoride 130 g / l and lead borofluoride. What is necessary is just to immerse for about 1 to 5 minutes in a solder plating solution having a temperature of 20 to 30 ° C., which is composed of 50 g / l, 125 g / l of borofluoric acid, and 25 g / l of boron borofluoride.
[0027]
At this time, it is preferable that the height of the solder plating layer 21 be in a range of −5 μm to +15 μm with respect to the height of the solder-resistant resin layer 4. When the height of the solder plating layer 21 is lower than −5 μm with respect to the height of the solder-resistant resin layer 4, a second solder paste 22 described below is printed and applied on the solder plating layer 21 and heated. When the solder bump 5 is formed, a flux is left inside the solder bump 5 due to a step formed between the solder plating layer 21 and the solder-resistant resin layer 4, and a void tends to be generated. On the other hand, if it is higher than +15 μm, a gap is formed between the print mask and the insulating substrate 1 when the solder paste 22 is applied by printing, and the amount of applied solder tends to vary.
[0028]
Next, as shown in FIG. 2C, a solder paste 22 is applied on the solder plating layer 21 to a thickness of 30 to 50 μm by using, for example, a conventionally known screen printing method. As the solder powder, for example, a spherical powder made of solder such as a lead-tin alloy having a particle size of about 5 to 25 μm is used. When the amount of flux in the solder paste 22 is less than 5% by mass, the solder paste 22 cannot be provided with an appropriate viscosity as a paste, and the solder paste 22 should be applied well on the solder plating layer 21. On the other hand, if it exceeds 15% by mass, the solder paste 22 and the solder plating layer 21 are heated to vaporize and remove the flux in the solder paste 22 and the solder in the solder paste 22 as described later. When the powder and the solder plating layer 21 are melted to form the solder bumps 5, the amount of flux in the solder paste 22 is large, so that the vaporized flux tends to be left in the solder bumps 5 and a large amount of voids are easily generated. is there. Therefore, the flux amount in the solder paste 22 is preferably in the range of 5 to 15% by mass.
[0029]
Next, as shown in FIG. 2D, the solder paste 22 and the solder plating layer 21 are heated to vaporize and remove the flux in the solder paste 22, and the solder powder and the solder plating layer 21 in the solder paste 22 are melted. Thus, the solder bumps 5 are formed on the solder bonding pads 3. At this time, since the solder plating layer 21 is previously applied on the solder bonding pad 3, the solder plating layer 21 is melted, so that the solder bonding pad 3 and the solder bump 5 are satisfactorily bonded. Further, since the solder bonding pad 3 and the solder bump 5 are satisfactorily bonded by the solder plating layer 21, it is not necessary to include a large amount of flux in the solder paste 22, and the solder paste 22 and the solder plating layer 21 are heated. The flux in the solder paste 22 is vaporized and removed, and the solder powder and the solder plating layer 21 in the solder paste 22 are melted to form the solder bump 5. It is possible to form the solder bumps 5 with a small amount.
[0030]
Thus, according to the wiring board with the solder bumps provided by the present invention, the electronic component is placed on the upper surface of the wiring board 1 such that its electrodes are in contact with the solder bumps 5 and the solder bumps 5 are melted. An electronic device as a product is obtained by joining the electrode of the component and the solder joint pad 3.
[0031]
It should be noted that the present invention is not limited to the example of the above-described embodiment, and various changes can be made without departing from the scope of the present invention.
[0032]
【The invention's effect】
According to the method for manufacturing a wiring board with solder bumps of the present invention, a solder plating layer is applied on a solder bonding pad exposed in an opening of a solder resistant resin layer, and then a solder paste is printed on the solder plating layer. Since the solder and the solder plating layer in the solder paste are melted and the solder bumps are formed on the solder bonding pads, the solder plating layer deposited on the solder bonding pads is melted and the solder bonding pads and the solder are melted. The solder bumps are satisfactorily bonded to each other, and the solder paste applied thereon can form a solder bump having a sufficient height with few voids. Therefore, it is possible to provide a wiring board with solder bumps that can firmly join the electrodes of the electronic component and the solder joining pads via the solder bumps.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board with solder bumps manufactured by a manufacturing method of the present invention.
FIGS. 2A to 2D are enlarged cross-sectional views of a main part in each step for explaining a method of manufacturing a wiring board with solder bumps according to the present invention.
[Explanation of symbols]
1, an insulating substrate 2, a wiring conductor 3, a solder bonding pad 4, a solder-resistant resin layer 4a, an opening 5 in the solder-resistant resin layer, etc. ... Solder bump 21 ... Solder plating layer 22 ... Solder paste

Claims (1)

配線導体を有する絶縁基板の表面に、前記配線導体に接続された複数の半田接合パッドおよび該半田接合パッドの中央部を露出させる開口部を有する耐半田樹脂層を形成する工程と、前記開口部内に露出した前記半田接合パッド上に半田めっき層を被着させる工程と、該半田めっき層上に半田ペーストを塗布する工程と、該半田ペースト中の半田および前記半田めっき層を加熱溶融させて前記半田接合パッド上に半田バンプを形成する工程とを行なうことを特徴とする半田バンプ付き配線基板の製造方法。Forming, on a surface of an insulating substrate having a wiring conductor, a solder-resistant resin layer having a plurality of solder bonding pads connected to the wiring conductor and an opening exposing a central portion of the solder bonding pad; A step of applying a solder plating layer on the solder bonding pad exposed to the step, a step of applying a solder paste on the solder plating layer, and heating and melting the solder in the solder paste and the solder plating layer, Forming a solder bump on the solder bonding pad.
JP2002277127A 2002-09-24 2002-09-24 Manufacturing method of wiring board with solder bump Expired - Fee Related JP3967989B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2007305774A (en) * 2006-05-11 2007-11-22 Shinko Electric Ind Co Ltd Substrate with built-in electronic component and its manufacturing method
CN108990265A (en) * 2018-08-28 2018-12-11 竞华电子(深圳)有限公司 A kind of solderability pcb board and its manufacture craft

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305774A (en) * 2006-05-11 2007-11-22 Shinko Electric Ind Co Ltd Substrate with built-in electronic component and its manufacturing method
CN108990265A (en) * 2018-08-28 2018-12-11 竞华电子(深圳)有限公司 A kind of solderability pcb board and its manufacture craft

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