JP2004117441A - Device and method for displaying video - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent discontinuous display from occurring at the adjacent parts of split areas even in the case of high speed scroll display when a video signal is split-displayed on a single display device. <P>SOLUTION: When the display device 30 is divided into the upper and lower screens 1, 2, for displaying, a plurality of unit processors UP of a 2nd group for processing display onto the screen 2 continuously operates to make the display timing of the screens 1 and 2 continuous with each other after a plurality of unit processors UP of a 1st group for processing display onto the screen 1 operates. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a video display device, and more particularly, to a video display device that divides and displays a video signal on a display device.
[0002]
[Prior art]
JP-A-8-335057 discloses that when displaying an image on a single LED display device using a plurality of LED lamps, the gradation data for each of the RGB colors for one screen stored in a memory circuit is displayed. A plurality of read circuits are provided for each display block in order to secure the display data, and when the gradation data read from each read circuit is divided and displayed on the corresponding display block, particularly, when the screen is scrolled in the horizontal direction, This presents a problem that an unnatural level difference occurs in a vertical line due to a mismatch between a writing speed and a reading speed with respect to a memory circuit, particularly, because a writing speed is higher than a reading speed (FIG. 5 to FIG. 8, paragraphs 0002 to 0004).
[0003]
Japanese Patent Application Laid-Open No. H8-335057 proposes, as a solution, (1) providing two storage units or (2) adjusting display timing.
[0004]
Further, a full-color large-sized image display device for displaying a color image on a large screen of full dots or more is widely used. In such a full-color large-size image display device, there is a problem of ensuring display time disclosed in Japanese Patent Application Laid-Open No. H8-335057 and a new problem caused by providing a plurality of readout circuits to overcome the problem. Encounter different tasks.
In a full-color large-size image display device, it is necessary to divide a video signal using a plurality of image processing devices and perform various processes due to a limitation of signal processing performed by one image processing device. Is divided and displayed on one large display device.
When a video signal obtained by dividing a video signal is displayed on one large display device, no problem occurs in a still image.
[0005]
[Patent Document 1]
JP-A-8-335057
[0006]
[Problems to be solved by the invention]
However, when a moving image, in particular, an image is scroll-displayed at high speed over a divided area, a discontinuous image occurs between the divided images as illustrated in FIG.
Also, when the display is divided into two parts on the left and right sides and scrolled, a discontinuous image is generated at the boundary between the left and right screens.
[0007]
On the other hand, when a video signal is signal-processed by, for example, four image processors, and the processing result is divided and displayed on a plurality of screens, the processing result shown in FIG. A discontinuous image as shown occurs. When the displayed line is a horizontal line, it is not a vertical line as illustrated in FIG. 2 but an unnatural image similar to the above at the upper and lower screen boundaries.
[0008]
Details of the generation of the unnatural or discontinuous video in FIGS. 1 and 2 will be described later.
[0009]
The discontinuity of the image at the boundary of the divided screen described above as the first and second examples is conspicuous because the display device 10 is large. In addition to the above-mentioned display of lines, especially when characters such as alphanumeric characters are scrolled at high speed across the screen boundary, if the above-mentioned discontinuous image occurs, it can not be recognized or difficult to recognize Can also occur.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a video display device that displays a display device by dividing the display device into a plurality of portions, in which discontinuous or unnatural display does not occur at boundaries between screens even when high-speed scrolling is performed. It is in.
[0011]
[Means for Solving the Problems]
In order to overcome the above-mentioned problems, in the present invention, timing adjustment is performed in a plurality of image processing units or unit display processing units so that discontinuous or unnatural images do not occur even at screen boundaries.
Such a timing adjustment is generally a widely used technique as disclosed in Japanese Patent Application Laid-Open No. H8-335057, but in the present invention, a method suitable for a display device and a divided display is used. And take measures.
[0012]
According to a first aspect of the present invention, a display device having M display units in a horizontal direction and N display units in a vertical direction using m × n dots as one display unit; M × N unit display processing means provided corresponding to N display units and performing display processing for each m × n dot of each display unit; and k (where k is an integer of 2 or more) K) image signal processing means for dividing and performing predetermined signal processing, and outputting the divided signal-processed video signals to the corresponding unit display processing means of the plurality of unit display processing means. An image display device, wherein the display device is divided and displayed on k screens, wherein the image signal processing means is arranged such that images of adjacent dots are continuously displayed on a boundary of the k divided screens. Timing of video signal processed by Having a timing adjustment unit that, the video display apparatus is provided.
[0013]
The display device is preferably a display device in which each pixel has a gradation of RGB and each pixel can be displayed by unit display processing means.
[0014]
According to a second aspect of the present invention, there is provided an image display method for processing a video signal, dividing the processed video signal into a plurality of screens on a display device, and displaying the divided video signal on a display device. The pixel data is set so that the image of the last pixel of the previous screen is displayed continuously from the first pixel of the next screen so that the image of the adjacent pixel is displayed continuously at the boundary of the screen. An image display method for adjusting the timing for display is provided.
[0015]
When the display device is divided into a plurality of screens and the video signal is divided and displayed, the display of the divided video signal is performed so that the pixel data on the adjacent screen is continuously displayed according to the display timing of the video signal. Adjust the timing or the drive timing of the pixel portion.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the video display device and the method thereof according to the present invention will be described with reference to the accompanying drawings.
[0017]
First embodiment
A first embodiment of the video display device of the present invention will be described with reference to FIGS.
FIG. 3 is a configuration diagram of an image display device as a first embodiment of the image display device of the present invention.
The image display device 1 illustrated in FIG. 3 includes two image signal processing devices (or image processors) 10 and 12, a plurality of unit display processing devices (or unit processors, UPs) 20, a display device 30, Having.
The image signal processing devices 10 and 12 correspond to the image signal processing means of the present invention, the unit processor group 20 corresponds to the unit display processing means of the present invention, and the display device 30 corresponds to the display device of the present invention.
[0018]
Display device
FIG. 4 is a diagram showing an outline of the configuration of the display device 30 illustrated in FIG. The display device 30 is a large-sized display device that is installed on a wall of a building using LEDs and has, for example, 640 dots (pixels) in the horizontal direction and 480 dots (pixels) in the vertical direction. One pixel is constituted by a light emitting diode (LED) capable of color display of three colors RGB and gray scale, for example, 256 gray scales.
[0019]
Image signal processing device
The configuration of the first and second image signal processing devices 10 and 12 as image signal processing means of the present invention and the reason for using two of them will be described.
Each of the image signal processing apparatuses 10 and 12 has a configuration illustrated in FIG. Hereinafter, the image signal processing device 10 will be described as a representative.
[0020]
An image signal processing device 10 illustrated in FIG. 5 includes an A / D conversion unit 101 that A / D converts a video signal VIDEO and converts it into a digital video signal, and performs an interlocking / progression process on the A / D converted video signal. IP conversion section 102 for conversion and rate conversion, enlargement / reduction processing section 103 for performing enlargement / reduction processing according to designation of the result converted by IP conversion section 102, and result of enlargement / reduction processing A color conversion unit 104 that performs color conversion and color temperature conversion, an image memory 105 that stores the result of the color conversion processing, and a case where a signal-processed video signal stored in the image memory 105 is output to a corresponding unit processor UP. And an address adding unit 106 that adds an address corresponding to the P / P and a P / P that converts a parallel signal into a serial signal. And a conversion unit 107.
The image signal processing device 10 also includes a memory control unit 108 that controls writing of data to the image memory 105 and reading of data from the image memory 105, and a line address generating unit that generates a line address to be added to the address adding unit 106. 109.
[0021]
As described above, the image signal processing devices 10 and 12 perform the above-described various processes on each of a total of 640 × 480 pixels of the NTSC video signal VIDEO input in 30 frames per second. Therefore, one image signal processing device encounters a limitation in processing speed.
As described above, in the present embodiment, the processing of the video signal VIDEO is shared by using the two image signal processing devices 10 and 12.
In the present embodiment, the first image signal processing device 10 processes a video signal displayed on the screen 1 in the upper half of the display device 30, and the second image signal processing device 12 performs processing on the lower half of the display device 30. The video signal displayed on the screen 2 is processed.
[0022]
Unit processor
Each unit of the group of unit processors 20 as one example of the unit display processing means of the present invention performs display processing of one display unit (display unit) of 16 dots × 16 dots on the display device 30 illustrated in FIG. One display unit is defined by pixels of m × n dots. In the present embodiment, one display unit is 16 dots × 16 dots. Therefore, in the present embodiment, each unit processor UP displays an LED corresponding to 16 × 16 = 256 pixels for color display based on the signal-processed video signal received from the image signal processing device 10 or 12. Is performed.
FIG. 6 is a configuration diagram of the unit processor UP.
[0023]
The unit processor UP illustrated in FIG. 6 includes a receiving unit 201 that receives signals from the image signal processing devices 10 and 12, a communication gate array (CGA) 202, a filter 203, a variable control oscillator (VCO) 204, An arithmetic processing unit (CPU) 205 of the microcomputer, a system clock generator 206, a MEMORY 207, a first clock generator 211 for generating a clock for an NTSC video signal, and a clock for a PAL video signal. It has a second clock generator 212 that generates a clock, a clock selector 213, and a plurality of driver circuits 220 that are turned on and connected to corresponding LEDs of the display device 30.
[0024]
An address bus ADRES and a data bus DATA are provided between the CPU 205, the communication gate array (CGA) 202, the MEMORY 207, and the driver circuit 220, and the unit processor UP itself is similar to a normal microprocessor. Operate.
The filter 203 and the variable control oscillator (VCO) 204 operate as a clock for a communication gate array (CGA) 202.
The CPU 205 operates according to the clock from the system clock generator 206.
[0025]
In this embodiment, since the video signal of the NTSC system is used, the clock selector 213 selects the clock from the first clock generator 211 that generates the clock for the video signal of the NTSC system, and sends the clock to the driver circuit 220. Apply. When a PAL video signal is used, the clock selector 213 selects a clock of the second clock generator 212 that generates a clock for the PAL video signal and applies the selected clock to the driver circuit 220.
The clock selected by the clock selector 213 is applied to the driver circuit 220 to adjust the driving timing of each pixel display element in the display device 30, that is, the LED.
[0026]
FIG. 7 is a configuration diagram of one packet of data transmitted from the image signal processing devices 10 and 12 to the unit processor UP.
One packet is composed of a synchronization code SYNC-CODE, an address ADRES, 8-bit (gradation) × 3 (RGB) digital image data, and EOF (End \ Of \ File). One packet contains video data of 16 × 16 pixels.
[0027]
The receiving unit 201 receives the data illustrated in FIG. 7 from the corresponding image signal processing apparatuses 10 and 12 and outputs the data to the communication gate array (CGA) 202. The communication gate array (CGA) 202 outputs the received data to the arithmetic processing unit (CPU) 205. The CPU 205 temporarily stores the data in the MEMORY 207, and stores the data in the MEMORY 207 according to the display timing of each display element, that is, the LED. The image processing data is read out, and the corresponding LED is turned on via the driver circuit 220 to display a desired image.
[0028]
Since the unit processor UP has the CPU 205, various signal processing and timing adjustment can be performed in the unit processor UP.
On the other hand, since the unit processor UP performs various types of signal processing, 16 × 16 pixels are processed by one unit processor UP in consideration of its processing capability. 640/16 = 40 unit processors UP are provided in the horizontal direction (column direction), and 480/16 = 30 unit processors UP in the vertical direction (row direction).
[0029]
FIG. 8 shows a connection relationship between a first image signal processing device 10 for processing a video signal displayed on the upper screen 1 of the display device 30 and a plurality of unit processors UP connected to the image signal processing device 10. FIG.
Display on the upper screen 1 is performed by turning on LEDs corresponding to 1 to 40 unit processors UP in the horizontal direction and 15 unit processors UP in the vertical direction.
The first image signal processing device 10 cyclically drives the unit processors UP and UP1 to UP15 in the vertical direction in the horizontal direction in a daisy chain.
[0030]
As described above, the video display device 1 performs the first-stage video signal processing in the image signal processing devices 10 and 12 and directly drives each LED of the display device 30 in each unit processor UP of the unit processor group 20. The processing system of function sharing that performs the above processing is configured.
As described above, the video signal of the NTSC system is displayed for each frame on one display device 30 using the two image signal processing devices 10 and 12 and the many unit processor groups 20.
[0031]
FIGS. 9A to 9F are diagrams showing conventional operation timings when a discontinuous display appears between the screens 1 and 2 during high-speed scroll display, as illustrated in FIG. It is.
As illustrated in FIGS. 9A, 9B, 9D, and 9E, the image signal processing devices 10 and 12 receive the video signal VIDEO for each vertical synchronization signal V-SYNC, and Various signal processes are performed on the upper and lower halves of the signal VIDEO in each section illustrated in FIG. Each of the image signal processing devices 10 and 12 outputs a signal processing result to the unit processor group 20.
[0032]
Conventionally, the half unit processor UP displaying the screen 1 of the unit processor group 20 and the half unit processor UP displaying the screen 2 are provided at the same timing as shown in FIGS. The corresponding LED in 30 was lit (lit). At the light emission timings illustrated in FIGS. 9C and 9F, the corresponding display units are sequentially turned on from the first unit controller UC to the fifteenth unit controller UC.
In such a light emission timing, the uppermost unit 1 of the upper screen 1 and the uppermost unit 16 of the lower screen 2 have the same light emission timing, and the lowermost unit 15 of the upper screen 1 and the lower screen 15 have the same light emission timing. Since the lowermost unit 30 has the same light emission timing, the light emission timings of the unit 15 and the unit 16 are shifted, and discontinuity occurs in an image near the boundary between the screens 1 and 2. As a result, when the circular image illustrated in FIG. 1 is scroll-displayed from the top to the bottom of the screen, as shown in FIG. 1, a problem has occurred that a circular image that should be continuous becomes discontinuous.
[0033]
A first embodiment of the present invention that solves such a problem will be described.
FIGS. 10A to 10G are diagrams showing the operation timing of the present embodiment in which the discontinuous display illustrated in FIG. 1 does not occur even when a high-speed scroll display is performed.
[0034]
As illustrated in FIGS. 10A, 10B, 10D, and 10E, the image signal processing devices 10 and 12 receive the video signal VIDEO for each vertical synchronization signal V-SYNC, and Various signal processes are performed on the upper and lower halves of the signal VIDEO in each section illustrated in FIG.
The processing results of the image signal processing devices 10 and 12 are sent to the group of unit processors 20.
The first image signal processing device 10 sequentially transmits the first to fifteenth unit processors in the vertical direction from time t3 to the first unit processor UP of the unit processor group 20 that performs lighting processing of the screen 1 in the upper half of the display device 30. The light-emission timing is specified so that the unit processor UP performs light-emission processing. The timing of the light emission processing is specified to each unit processor UP based on the vertical synchronizing signal V-SYNC from the image signal processing apparatus 10 and how long after the clock time has elapsed is specified to each unit processor UP. The (CPU) 205 adjusts the timing and performs light emission processing via the corresponding driver circuit 220.
[0035]
The second image signal processing device 12 sends the first fifteenth unit processor to the latter half of the unit processors 16 to 30 of the unit processor group 20 for lighting the lower half screen 2 of the display device 30 after the lapse of the time t3. After the UP light emission process, the light emission timing is sequentially specified to the 16th to 30th unit processors UP in the vertical direction so that the LED light emission operation is continuously performed from the time point t4.
The timing of the light emission processing is also specified to each unit processor UP based on the vertical synchronization signal V-SYNC from the image signal processing device 12, and the number of clock times after which the lighting processing is performed is specified to each unit processor UP. The (CPU) 205 adjusts the timing, and performs light emission processing of the corresponding LED via the corresponding driver circuit 220.
Accordingly, the 16th to 30th unit processors UP which perform the light emission processing of the screen 2 do not immediately perform the light emission processing of the LED even after receiving the signal, and wait until their own light emission processing timing arrives.
[0036]
Thus, the display is performed continuously from the lowermost unit display portion of the screen 1 of the display device 30 and subsequently to the uppermost unit display portion of the screen 2 of the display device 30.
In this manner, the second image signal processing device 12 designates the light emission timing to the corresponding unit processor UP, and each unit processor UP waits until its own light emission timing to perform light emission processing, whereby the screen 1 to the screen 2 can be transmitted. The display is performed continuously without any discontinuity, and the discontinuous display due to the scroll described with reference to FIG. 1 does not occur.
[0037]
In the first embodiment, the timing adjusting means of the present invention corresponds to the second image signal processing device 12 and the unit processor UP connected to the second image signal processing device 12, which cooperate with the screen 1 and the screen 1. The discontinuous display between the two is eliminated.
The above-described timing adjustment is realized only by the processing function built in the unit processor UP and the timing designation by the second image signal processing device 12, so that it can be implemented very easily.
[0038]
Modification of First Embodiment
The display device 30 using LEDs is not raster-scanned like a CRT device, and can display individual LEDs by emitting light. Therefore, display processing can be performed by dividing the display device 30 right and left.
In the case where the display device 30 is divided into left and right and displayed, the second half of the right half LED is processed by the second image signal processing device 12 which processes the video signal of the right half screen so as to be continuously displayed on the left and right screens. The operation start timing of the unit processor UP for performing the light emission processing is designated.
[0039]
Second embodiment
A second embodiment of the video display device according to the present invention will be described with reference to FIGS.
FIG. 11 is a configuration diagram of a video display device as a second embodiment of the video display device of the present invention.
The video display device 2 illustrated in FIG. 11 includes, for example, a video signal distributor 40 that divides a video signal VIDEO of one frame output from the video tape recording / reproducing device 100 into four, and four image signal processing devices (or It has image processors 51 to 54, a plurality of unit display processing devices (or unit processors, UPs) 20A, and a display device 30.
The image signal processing devices 51 to 54 correspond to the image signal processing means of the present invention, the unit processor group 20A corresponds to the unit display processing means of the present invention, and the display device 30 corresponds to the display device of the present invention.
[0040]
Display device
The display device 30 is, for example, a large-sized display device having 640 dots × 480 dots and installed on a wall surface of a building using LEDs, for example, as described with reference to FIG. Has 640 dots (pixels) and 480 dots (pixels) in the vertical direction. One pixel is constituted by a light emitting diode (LED) capable of color display of three colors RGB and gradations, for example, 256 gradations. In the second embodiment, it is illustrated in FIG. 2 and FIG. As described above, the image is displayed divided into four in the vertical and horizontal directions.
[0041]
Image signal processing device
The configuration of the first to fourth image signal processing devices 51 to 54 as image signal processing means of the present invention and the reason for using four of them will be described.
The first to fourth image signal processing devices 51 to 54 have the same configuration, and have the configuration illustrated in FIG. Hereinafter, the first image signal processing device 51 will be described as a representative.
The image signal processing device 51 illustrated in FIG. 13 is similar to the configuration of the image signal processing device 10 of the first embodiment described with reference to FIG. That is, an A / D converter 301 corresponding to the A / D converter 101 for A / D converting the video signal VIDEO into a digital video signal, and an IP converter corresponding to the IP converter 102. 302, an enlargement / reduction processing unit 303 corresponding to the enlargement / reduction processing unit 103, a color conversion unit 304 corresponding to the color conversion unit 104, an image memory 305 equivalent to the image memory 105, and an equivalent to the address addition unit 106 An address adding unit 306, a P / S conversion unit 307 corresponding to the P / S conversion unit 107, a memory control unit 308 corresponding to the memory control unit 108, and a line address generator 309 corresponding to the line address generator 109. And
[0042]
However, since each of the image signal processing devices 51 to 54 has half the amount of data processed by each of the image signal processing devices 10 and 12 of the first embodiment, each of the image signal processing devices 10 and 12 The amount of processing becomes half, and for example, the image memory 305 may have half the memory capacity of the image memory 105. On the other hand, the image signal processing devices 51 to 54 can perform high-speed processing at twice the processing speed of the image signal processing devices 10 and 12.
[0043]
The first image signal processing device 51 further includes a data delay setting circuit 310 and a line address delay setting circuit 311.
As described later, the data delay setting circuit 310 sets a delay time in the memory control unit 308 and adjusts the output timing of data output from the image signal processing devices 51 to 54 to the unit processor UP.
Similarly, the line address delay setting circuit 311 sets a delay time in the line address generator 309, and adjusts the addition timing of the line address given from the image signal processing devices 51 to 54 to the unit processor UP.
[0044]
Since the first image signal processing device 51 does not need to perform the delay processing, the first image signal processing device 51 does not require the data delay setting circuit 310 and the line address delay setting circuit 311. A case where all of the devices 51 to 54 have the same circuit configuration will be described.
[0045]
The image signal processing devices 51 to 54 share and process four divided image data for a total of 640 × 480 pixels for each pixel of the video signal VIDEO input for 30 frames per second.
In the second embodiment, the first image signal processing device 51 processes a video signal displayed on the screen 1 at the upper left of the display device 30, and the second image signal processing device 52 performs processing at the lower left of the display device 30. The video signal displayed on the screen 2 is processed, the third image signal processing device 53 processes the video signal displayed on the screen 3 at the upper right of the display device 30, and the fourth image signal processing device 54 The video signal displayed on the lower right screen 4 of the display device 30 is processed.
[0046]
Unit processor
Each unit of the unit processor group 20A performs a display process on one display unit (display unit) of 16 dots × 16 dots for the display device 30 illustrated in FIG. One display unit is defined by pixels of m × n dots. In the second embodiment, as in the first embodiment, one display unit is 16 dots × 16 dots.
Each unit processor UP performs drive processing for color display of LEDs corresponding to 16 × 16 = 256 pixels based on signal-processed video signals received from the corresponding image signal processing devices 51 to 54.
The configuration of each unit processor UP is the same as that described with reference to FIG.
[0047]
The configuration of one packet of data output from the image signal processing devices 51 to 54 to each unit processor UP is the same as that described with reference to FIG. That is, one packet is composed of a synchronization code SYNC-CODE, an address ADRES, 8-bit (gradation) × 3 (RGB) digital image data, and EOF (End \ Of \ File). One packet contains video data of 16 × 16 pixels.
[0048]
The connection relationship between each of the image signal processing devices 51 to 54 and each unit processor UP is the same as that described with reference to FIG.
[0049]
The video display device 2 performs the first-stage video signal processing in the image signal processing devices 51 to 54, and performs processing for directly driving each LED of the display device 30 in each unit processor UP of the unit processor group 20A. It constitutes a processing system for sharing functions.
As described above, the NTSC video signal is displayed for each frame on one display device 30 by using the four image signal processing devices 51 to 54 and the unit processor group 20A.
[0050]
FIG. 14 shows a configuration in which the image signal processing devices 51 to 54 do not have the data delay setting circuit 310 and the line address delay setting circuit 311 illustrated in FIG. 13, respectively, and have a configuration similar to that illustrated in FIG. A display process is performed on the upper and lower screens 1 and 2 on the left side of the display device 30 illustrated in FIG. 12 using the image signal processing devices 51 and 52, and the display device is processed using the unit processor UP that performs a light emission process on the screens 1 and 2. FIG. 3 is a diagram showing operation timings when the discontinuous display illustrated in FIG. 2 is performed when 30 is displayed.
However, in this example, the display device 30 has 7 × 2 = 14 display units (14 × 16 dots = 224 dots) in the horizontal direction and 20 × 2 = 40 display units (40 × 16 dots = 640 dots) in the vertical direction. It shows about the case of.
The operation timing of the unit processor UP that performs the display processing of the highest display unit of the screen 1 and the operation timing of the unit processor UP that performs the display processing of the highest display unit of the screen 2 match.
[0051]
The image signal processing devices 51 to 54 without the data delay setting circuit 310 and the line address delay setting circuit 311 in FIG. 13 convert the four video signals VIDEO distributed by the video signal distributor 40 into the video signals VIDEO shown in FIGS. (F) or at the same time as the timing illustrated in FIGS. 10 (a) to (f), and the image signal processing devices 51 to 54 process 1/4 of the video signal VIDEO.
However, of the four divided video signals VIDEO, the divided video signals received by the second to fourth image signal processing devices 52 to 54 are delayed with respect to the video signals received by the first image signal processing device 51. Then, a delay occurs due to signal processing in the image signal processing devices 51 to 54.
Therefore, when the timing illustrated in FIG. 14 causes the unit processor UP to operate, the image signal processing devices 51 to 54 and the unit processor may be shifted due to a phase shift of the reception timing in the image signal processing devices 51 to 54, a delay due to signal processing, and the like. A shift occurs in the light emission timing of the LED of the display device 30 driven by the UP.
[0052]
When the display device 30 is driven from the unit processor UP despite the presence of such a phase shift, an unnatural display as illustrated in FIG. 2 occurs on the screen 1 and the screen 3. In the example illustrated in FIG. 14, a horizontal straight line becomes unnatural at the boundary between the screen 1 and the screen 2.
In FIG. 2A, when the vertical straight line of the image moves in the direction B from A, a phase shift occurs as illustrated in FIG. 2B, and the upper portion of the vertical straight line turns right on the screens 1 and 2. . When the vertical straight line of the image moves in the direction A from B, a phase shift occurs as illustrated in FIG. 2C, and the upper portion of the vertical straight line turns left on the screens 3 and 4.
The order of light emission is (1), (2), and (3). Although there is a time difference of one field between (1) and (3), the light emission time is close between (2) and (3) due to scanning. When the image moves, (2) also emits light when (3) emits light, but (1) has already emitted light and it looks like a turn. The time difference is ((1)-(2))> ((2)-(3)).
[0053]
FIG. 15 shows that each of the image signal processing devices 51 to 54 has the data delay setting circuit 310 and the line address delay setting circuit 311 illustrated in FIG. 13. For example, the upper and lower left and right sides of the display device 30 illustrated in FIG. When the display processing is performed using the image signal processing devices 51 and 52 for the screens 1 and 2 and the display device 30 is displayed using the unit processor UP that performs the light emission processing of the screens 1 and 2, the display illustrated in FIG. It is a figure which shows the operation timing which eliminates a continuous display.
Also in this example, the display device 30 has 7 × 2 = 14 display units (14 × 16 dots = 224 dots) in the horizontal direction and 20 × 2 = 40 display units (40 × 16 dots = 640 dots) in the vertical direction. Is shown.
[0054]
In FIG. 15, the second image signal processing device 52 transmits the light emission timing of the first display unit of the screen 2 from the second image signal processing unit 52 so that the light emission timing continues after the twentieth (last) display unit of the screen 1. The operation timing of the unit processor UP for processing the display of the portion is adjusted.
The method uses a memory control unit 308 illustrated in FIG. 13 to delay the timing of data read from the image memory 305 in the data delay setting circuit 310 in the second image signal processing device 52 as illustrated in FIG. The line address delay setting circuit 311 also sets a delay time so that the line address addition timing of the line address generator 309 is delayed in accordance with the data read timing from the image memory 305.
The unit processor UP which performs the display processing of the screen 2 of the display device 30 receives the data thus delayed and drives the driver circuit 220.
As a result, there is no discontinuous display at the boundary between the screen 1 and the screen 2.
[0055]
The same timing adjustment is performed between the screen 1 and the screen 3 and between the screen 2 and the screen 4.
As a result, the unnatural display caused by the phase shift described with reference to FIG. 2 is eliminated.
[0056]
In the second embodiment, the timing adjustment means of the present invention corresponds to the data delay setting circuit 310 and the line address delay setting circuit 311 illustrated in FIG.
[0057]
Although the display device using a plurality of LEDs as the display device 30 has been described, the present invention is not limited to the LED type display device, and performs display processing for each pixel without performing raster scanning unlike a CRT display device. The present invention can also be applied to the case of split display on a display device such as a liquid crystal display device.
In addition, the video display device of the present invention does not depend on the scale of the display device, and when one video signal related to one display device is divided and displayed, in particular, high-speed scroll display, and a phase shift in the divided video signal. It can be widely applied when it occurs.
[0058]
Further, the video signal targeted by the present invention is not limited to the video signal of the NTSC system, and can be applied to the divided display of the video signal of another system such as the video signal of the PAL system.
[0059]
【The invention's effect】
According to the present invention, even when a video signal is divided and displayed on one display device, it is possible to prevent an unnatural or discontinuous display from occurring at the boundary of the divided display area.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a case where two image processing devices (image processors) are used to divide and display one video signal vertically on a large display device using LEDs.
FIG. 2 is a diagram exemplifying that display processing of a video signal on a display device is divided into four by four image processing devices (image processors) and a discontinuous video is generated when scroll display is performed; It is.
FIG. 3 is a diagram illustrating a configuration of a video display device according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating an outline of a configuration of the display device illustrated in FIG. 3;
FIG. 5 is a configuration diagram of the image signal processing device illustrated in FIG. 3;
FIG. 6 is a configuration diagram of a unit processor.
7 is a configuration diagram of one packet of data transmitted from the image signal processing device illustrated in FIG. 5 to the unit processor illustrated in FIG. 6;
8 is a first image signal processing device for processing a video signal displayed on an upper screen of the display device illustrated in FIG. 1, and a plurality of unit processors connected to the image signal processing device. FIG. 5 is a diagram showing a connection relationship of the present invention.
9 (a) to 9 (f) show conventional operation timings when a discontinuous display appears between screens 1 and 2 when high-speed scroll display is performed as illustrated in FIG. FIG.
FIGS. 10A to 10G are diagrams illustrating operation timings of the video display device according to the first embodiment of the present invention illustrated in FIG. 3;
FIG. 11 is a diagram illustrating a configuration of a video display device according to a second embodiment of the present invention.
FIG. 12 is a diagram illustrating an outline of a configuration of the display device illustrated in FIG. 11;
FIG. 13 is a configuration diagram of the image signal processing device illustrated in FIG. 11;
FIG. 14 is a diagram showing conventional operation timing when a discontinuous display appears between the left and right screens.
FIG. 15 is a diagram illustrating operation timings of the video display device in FIG. 11;
[Explanation of symbols]
1..Image display device
10, 12, image signal processing device
51 to 54 ... Image signal processing device
101, 301... A / D converter
102, 302 ··· IP conversion unit
103, 303 ... enlargement / reduction processing unit
104, 304 ... color conversion unit
105, 305 ... Image memory
106, 306... Address adding unit
107, 307 P / S converter
108, 308 ··· Memory control unit
109, 309... Line address generator
310. · Data delay setting circuit
311 ··· Line address delay setting circuit
20, 20A unit processor (UP)
201: receiving unit, 202: communication gate array (CGA)
203 ・ ・ Filter 、 204 ・ ・ Variable control type oscillator
205: CPU, 206: System clock generator
207 MEMORY
211, 212 ··· Clock generator
213 clock selector, 220 driver circuit
30-Display device

Claims (8)

a display device having M display units in the horizontal direction and N display units in the vertical direction, using m × n dots as one display unit;
M × N unit display processing means provided corresponding to the M × N display units of the display device and performing display processing of a display element for every m × n dots of each display unit;
The video signal is divided into k (where k is an integer of 2 or more) and subjected to predetermined signal processing, and the divided signal-processed video signals are output to k unit display processing units corresponding to the plurality of unit display processing units. Image signal processing means,
A video display device, wherein the video signal is displayed by dividing the display device into k screens,
At a boundary of the k divided screens, a timing adjusting unit that adjusts timing of a video signal processed by the image signal processing unit so that images of adjacent dots are continuously displayed,
Video display device. The timing adjustment unit includes:
A plurality of unit display processes for displaying a display portion of the next screen so that the next pixel after the last pixel of the previously displayed screen is continuously displayed after the first pixel of the next displayed screen. Adjusting the display processing start timing in the means,
The video display device according to claim 1. The image signal processing means,
Conversion means for expanding or reducing the video signal,
Storage means for storing the video signal converted by the conversion means,
Address addition means for adding an address of a corresponding unit display processing means for driving a display element of a pixel of the display device to a video signal read from the storage means;
Timing designation means for designating the operation timing of the unit display processing means,
The timing designation means and the unit display processing means perform the timing adjustment in cooperation with each other;
The image display device according to claim 2. The unit display processing unit performs a display process on a corresponding portion of the display device according to an operation timing specified by the image signal processing unit.
The video display device according to claim 3. The timing adjustment unit includes:
After the last part of the previous screen, the video signal processed by the image signal processing means by adjusting the timing so that the first part of the next screen and subsequent parts are continuously displayed is displayed in the corresponding unit display processing. Sending to means,
The video display device according to claim 1. The image signal processing means,
Conversion means for expanding or reducing the video signal,
Storage means for storing the video signal converted by the conversion means,
Address addition means for adding an address of a corresponding unit display processing means for driving a display element of a pixel of the display device to a video signal read from the storage means;
First timing adjusting means for adjusting read timing of data read from the storage means;
Second timing adjusting means for adjusting the timing of adding the address.
The video display device according to claim 5. The display device is a display device in which each pixel has a gradation of RGB and each pixel can be displayed by the unit display processing means.
The video display device according to claim 1. A video display method of processing a video signal and dividing the signal-processed plurality of divided video signals into a plurality of screens on a display device for display,
The pixels of the last pixel of the previous screen are displayed continuously from the first pixel of the next screen so that the images of the adjacent pixels are continuously displayed at the boundaries of the plurality of screens. Adjust the timing of the data and display it.
Video display method.

Images