JP2009109875A - Video display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display system capable of minimizing the number of video distribution units in use even when the limit of a clock frequency for display data synchronization is exceeded because of the number of display units which are connected in a lateral direction. <P>SOLUTION: The video distribution unit 2 inputs display data generated by dividing a video signal into two right and left portions to a display unit 7 alternatively, and the display unit 7 separates the input display data by display data of right and left areas, performs display based on display data corresponding to an area where the display unit 7 is situated, and performs similar processing with the video distribution unit 2 on display data, exceeding storage capacity by which information corresponding to a light emitting element that the display unit 7 should display by single-time lighting, and inputs the data to the next display unit 7. Consequently, even when the limit of the clock frequency for display data synchronization is exceeded because of the number of display units 7 connected in the lateral direction, the number of video distribution units 2 to be added can be minimized and the cost can greatly be reduced as compared with a conventional video display system. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video display system that displays a video such as a moving image or characters in full color on a display medium using light emitting elements that emit light in red, green, and blue, such as an LED (Light Emitting Diode) display.

  Conventionally, as shown in FIG. 7, light emitting elements 101 emitting red, green, and blue light are arranged vertically and horizontally at equal intervals, and m rows and n columns are configured as one display unit 100 in the vertical and horizontal directions. There is a video display system that displays a video such as a moving image or text in full color as a single display medium 110 (see FIG. 8).

  As shown in FIG. 8, this video display system distributes video signals to a video transmission device 111 that converts a video to be displayed into a video signal suitable for the display medium 110 and each display unit 100 of the display medium 110. Thus, the video distribution unit 112 is inputted, and the display medium 110 is displayed. The display unit 100 in the horizontal direction is connected by a signal cable, and a video signal is input from the end display unit 100, and the video signal is transmitted to the next display unit 100 via the signal cable. Therefore, the video distribution unit 112 distributes and outputs video signals according to the number of display units 100 in the vertical direction.

  As shown in FIG. 9, the video signal output from the video distribution unit 112 to the display unit 100 includes display data, a clock for synchronizing display data, a latch signal for determining display data, and a lighting signal for controlling lighting. It comprises an enable signal and a gradation clock for gradation control. The display data is composed of three types of color data of red, green, and blue, and each color data is output in parallel with the number of bits corresponding to the maximum number of gradations of the display unit 100. For example, if the maximum number of gradations is 1024 gradations, the color data is 10 bits (0 to 1023). These red, green, and blue color data correspond to each light emitting element 101 and control lighting for a time corresponding to a gradation value.

  As shown in FIG. 10, the display unit 100 includes a display data receiving circuit 102 that receives display data and a synchronization clock, a memory 103 that can store display data of the number of light emitting elements 101 that are turned on at one time, and display data. And a light emitting element lighting circuit 105 that performs lighting control for all the light emitting elements 101 included in the display unit 100.

  The capacity of the memory 103 is related to the lighting control of the display unit 100. In the static control method in which all the light emitting elements 101 in m rows and n columns are turned on simultaneously by one lighting, the display data of m × n × 3 colors is displayed. It becomes the capacity which can store. Further, in the dynamic lighting method in which the light emitting elements 101 that are turned on at a time are used as a row unit and the lighting control is performed using the afterimage effect of the eyes, the capacity is n × 3 colors × the number of lighted rows.

  When the display data exceeding the number of light emitting elements that are turned on at one time is input, the display unit 100 stores the newly input display data in the memory 103 and outputs the old display data to the next display unit 100. To control. Therefore, if the number of display units 100 connected in the horizontal direction is N and the memory capacity of the display unit 100 is L, the display data is output to all the display units 100 in the horizontal direction by outputting N × L display data. Can be stored.

  When the output of the display data is finished, the video distribution unit 112 determines the display data stored in the memory 103 of each display unit 100 by the latch signal, and starts lighting by the enable signal. The lighting time of each light emitting element 101 is until the grayscale clock is counted and matches the grayscale number of the display data. By repeating this control, full color video display is possible.

International Patent Application No. 00/57397 (Patent No. 3294597)

  In the conventional video display system described above, the number of display data input to the display unit 100 by the video distribution unit 112 increases in proportion to the number of display units 100 connected in the horizontal direction. The video to be displayed is generally 60 frames per second, and in order to satisfy the number of frames, the frequency of the display data synchronization clock (synchronization clock shown in FIG. 10) is increased and the display per unit time is displayed. The number of data transmissions needs to be increased.

  However, the frequency of the synchronizing clock that can be input to the display data receiving circuit 102 and the light emitting element lighting circuit 105 inside the display unit 100 is limited, and the frequency of the synchronizing clock depends on the number of display units 100 connected in the horizontal direction. When the limit is exceeded, as shown in FIG. 11, the number of display units 100 connected in the horizontal direction is set within one frequency range of the synchronization clock, and one block is displayed. It has been necessary to configure using a plurality of video distribution units 112 arranged in the direction.

  Since the video distribution unit 112 becomes one unit, if the number of the video distribution units 112 is increased, there is a problem that the cost inevitably increases. Further, as the number of video distribution units 112 increases, the apparatus configuration becomes complicated.

  The present invention has been made in view of such circumstances, and increases the transmission data amount of display data and the number of display units connected in the horizontal direction within a range not exceeding the limit of the clock frequency for synchronizing display data. Accordingly, an object of the present invention is to provide a video display system capable of minimizing the number of video distribution units used.

  The video display system of the present invention is a video display system having a display unit configured by arranging a plurality of light emitting elements emitting red, green, and blue, wherein the display unit synchronizes display data input from the outside. Display data acquisition means for acquiring display data at the rising and falling timings of the clock, and data used at the current display timing and data used at the next display timing in synchronization with the synchronizing clock. Display data dividing means for distributing, storage means for temporarily storing data used at the next display timing distributed by the display data dividing means, and use at the current display timing distributed by the display data dividing means Synthesizing the data to be stored and the data stored in the storage means to synchronize with the synchronization clock Comprising a display data generating means for generating display data, a.

  According to such a configuration, when a number of display units are connected in the horizontal direction, the amount of display data transmission data can be increased as compared with the conventional case within a range not exceeding the limit of the clock frequency for synchronizing display data. . That is, the number of display units connected in the horizontal direction can be increased as compared with the conventional case.

  Also, the video display system of the present invention is a video display system having a video distribution unit for inputting display data and a clock for synchronizing the display data to the display unit, wherein the video distribution unit has a rising edge of the clock for synchronization. Display data output means for outputting different display data at the falling edge is provided.

  According to this configuration, display data for two data can be input to the display unit of the present invention during one cycle of the clock for synchronizing display data. Since the display unit of the above invention can increase the amount of display data transmission data as compared with the conventional display data as long as it does not exceed the limit of the clock frequency for display data synchronization, the number of display units connected in the horizontal direction can be increased. Can be increased. Therefore, when a large display device with a large number of display units connected in the horizontal direction is manufactured, the number of video distribution units can be reduced as compared with the conventional case, so that the large display device can be manufactured at low cost.

  The present invention increases the number of display data transmission data and increases the number of display units connected in the horizontal direction within a range that does not exceed the limit of the clock frequency for synchronizing display data. The cost can be reduced significantly compared to the conventional video display system.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments for carrying out the invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a video display system according to an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of the video distribution unit of FIG. FIG. 3 is a timing chart showing a video signal output from the video distribution unit of FIG. FIG. 4 is a diagram illustrating a relationship between a video signal output from the video distribution unit of FIG. 2 and display data.

  In FIG. 1, a video display system 1 according to the present embodiment includes a video distribution unit 2, a video transmission device 3, and a display medium 4. The video distribution unit 2 receives a video signal S3 from the video transmission device 3. The video signal S3 is configured in a format (hereinafter referred to as a frame) that can be displayed on the display medium 4, and is output from the video transmission device 3 at a timing of 60 frames per second. The video signal S3 is divided into two, one for the A area 5 of the display medium 4 and the other for the B area 6 of the display medium 4, and stored in the frame data storage memory 22 (see FIG. 2). The

  As shown in FIG. 2, the video distribution unit 2 includes a video signal control circuit 21, a frame data storage memory 22, a video signal generation circuit 23, and a clock generation circuit 24. When the video signal control circuit 21 receives the video signal S3 for two or more consecutive frames, the video signal S9 for the A area 5 and the video signal S10 for the B area 6 one frame before the A area 5 are received from the frame data storage memory 22. Is input to the video signal generation circuit 23.

  The video signal generation circuit 23 divides the video signal S9 and the video signal S10 for each display unit in each column, and generates a display signal S12 for each display unit. The display signal S12 is generated using a synchronization clock that is within the allowable frequency range generated by the clock generation circuit 24, and display data red D14 corresponding to the light emitting element 101 of the display unit 7 as shown in FIG. As the display data green D15 and the display data blue D16, the video signal S9 is alternately output at the rising edge of the clock, and the video signal S10 is alternately output at the falling edge of the clock.

  Here, the hatched portions in FIG. 3 correspond to the display data red D14, the display data green D15, and the B area 6 of the display data blue D16, and the unhatched portions are the display data red D14 and the display data green D15. This corresponds to the A area 5 of the display data blue D16, and this corresponds to the areas with and without hatching in FIG. The display signal S12 is continuously transmitted by repeating the above process every time a frame is received as the video signal S3.

  FIG. 4 is a diagram showing the continuity of the processing. In FIG. 4, when the video signal S3 continuous with the first frame 17, the second frame 18, the third frame 19 is input from the video transmission device 3, the areas of the A area 5 in each frame are respectively A1, A2, A3. When the area of the B area 6 is B1, B2, and B3, respectively, the display data D20 output from the video distribution unit 2 is that the A area is A1 in the first frame 17 and the B area is the B area 2 and 2 of the previous frame. In the frame 18, the A area is A2, the B area is B1, and in the third frame 19, the A area is A3, and the B area is B2.

  FIG. 5 is a block diagram showing a schematic configuration of the display unit 7. FIG. 6 is a conceptual diagram of display data division in the display unit 7. In FIG. 5, the display unit 7 includes a display data dividing circuit 71, a display data receiving circuit 72, a memory for temporarily storing undisplayed data 73, a memory 74, a display data generating circuit 75, a latch circuit 76, and a light emission. An element lighting circuit 77 is provided.

  The display data dividing circuit 71 generates an internal clock S25 (see FIG. 6) synchronized with the synchronization clock S22, and displays the display data red D14, the display data green D15, and the display data blue D16 in synchronization with the internal clock S25. The display data (A) D26 corresponding to the A area 5 and the display data (B) D27 corresponding to the B area 6 are divided. The display data is divided into display data (A) D26 corresponding to the A area 5 at the rising timing of the synchronization clock S22, and display data (B) D27 corresponding to the B area 6 at the falling timing. To do.

  The processing of the divided display data (A) D26 and display data (B) D27 differs depending on which area of the A area 5 or B area 6 the display unit 7 belongs to. For example, when the display unit 7 belongs to the A area 5, the display data (A) D26 is input to the display data receiving circuit 72 together with the internal clock S25, and the display data (B) D27 is undisplayed data as undisplayed data. It is stored in the temporary securing memory 73. That is, in this case, the display data (A) D26 is data used at the current display timing, and the display data (B) D27 is data used at the next display timing. When the display unit 7 belongs to the B area 6, the display data (B) D27 is input to the display data receiving circuit 72 together with the internal clock S25, and the display data (A) D26 is undisplayed data as undisplayed data. It is stored in the temporary securing memory 73.

  The display data receiving circuit 72 stores the display data (A) D 26 or the display data (B) D 27 from the display data dividing circuit 71 in the memory 74. The undisplayed data temporary securing memory 73 and the memory 74 have a capacity capable of storing information corresponding to the light emitting element 101 to be displayed by the display unit 7 to be turned on once. When the capacity is exceeded, a new display is performed. Data is stored and old display data is output to the next display unit 7. Therefore, the display data dividing circuit 71 acquires the display data exceeding the capacity from the display data receiving circuit 72, and the undisplayed data temporary securing memory 73 similarly reads the display data exceeding the capacity, and the next display unit. The display data generation circuit 75 inputs the display data (A) D26 and the display data (B) D27 for transmission.

  The display data generation circuit 75 generates the display signal S12 shown in FIG. 3 based on the display data (A) D26 and the display data (B) D27 from the display data dividing circuit 71 and inputs them to the next display unit 7. When the output of all the display data is completed, the display data stored in the memory 74 of each display unit 7 is determined by the latch circuit 76 by the latch signal S 32 and is input to the light emitting element lighting circuit 77.

  The light emitting element lighting circuit 77 starts lighting by the enable signal S35 and the gradation clock S36. The lighting time of each light emitting element 101 is until the grayscale clock S36 is counted and coincides with the grayscale number of the display data. By repeatedly performing the control, video display is performed in the A area 5 and the B area 6 at the timing shown in FIG.

Next, the operation of the video display system 1 having the above configuration will be described.
First, the operation of the video distribution unit 2 will be described.
When the video signal S3 is input from the video transmission device 3, the video signal control circuit 21 captures the video signal S3. The video signal control circuit 21 divides the captured video signal S3 into two for the A area 5 and B area 6 of the display medium 4 and stores them in the frame data storage memory 22. When the video signal control circuit 21 receives the video signal S3 for two or more consecutive frames, the video signal S9 in the A area 5 and the video signal S10 in the B area 6 one frame before the A area 5 are received from the frame data storage memory 22. Read and input to the video signal generation circuit 23.

  The video signal generation circuit 23 divides the input video signal S9 and video signal S10 for each display unit in each column, and generates a display signal S12 for each display unit. For generation of the display signal S12, a synchronization clock within the allowable frequency range generated by the clock generation circuit 24 is used, and the display data red D14, display data green D15, and display data corresponding to the light emitting element 101 of the display unit 7 are displayed. The video signal S9 and the video signal S10 are alternately output as the data blue D16. By repeating this process every time a frame is received as the video signal S3, the display signal S12 is continuously output.

Next, the operation of the display unit 7 will be described.
When the display signal S12 is input from the video distribution unit 2, the display data dividing circuit 71 generates an internal clock S25 (see FIG. 6) synchronized with the synchronization clock S22, and the display data red is synchronized with the internal clock S25. D14, display data green D15, and display data blue D16 are each divided into display data (A) D26 corresponding to A area 5 and display data (B) D27 corresponding to B area 6.

  When the display unit 7 belongs to the A area 5, the display data (A) D26 is input to the display data receiving circuit 72 together with the internal clock S25, and the display data (B) D27 is displayed as undisplayed data. Store in the temporary memory 73. When the display unit 7 belongs to the B area 6, the display data (B) D27 is input to the display data receiving circuit 72 together with the internal clock S25, and the display data (A) D26 is temporarily reserved as undisplayed data. Stored in the memory 73.

  When the display data (A) D26 or the display data (B) D27 from the display data dividing circuit 71 is input, the display data receiving circuit 72 stores the display data in the memory 74. The undisplayed data temporary securing memory 73 and the memory 74 have a capacity capable of storing information corresponding to the light emitting element 101 to be displayed by the display unit 7 to be turned on once. When the capacity is exceeded, a new display is performed. Data is stored and old display data is output to the next display unit 7.

  Therefore, the display data dividing circuit 71 acquires display data exceeding the capacity of the non-displayed data temporary securing memory 73 and the memory 74 from the display data receiving circuit 72, and the undisplayed data temporary securing memory 73 has the same capacity. Exceeding display data is read out and input to the display data generation circuit 75 as display data A26 and display data B27 for transmitting the next display unit.

  The display data generation circuit 75 generates a display signal S12 based on the display data (A) D26 and the display data (B) D27 from the display data dividing circuit 71 and inputs them to the next display unit 7. When the output of all the display data is completed, the display data stored in the memory 74 of each display unit 7 is determined by the latch circuit 76 by the latch signal S 32 and is input to the light emitting element lighting circuit 77. The light emitting element lighting circuit 77 starts lighting by the enable signal S35 and the gradation clock S36. The lighting time of each light emitting element 101 is until the grayscale clock S36 is counted and coincides with the grayscale number of the display data. By repeating the above control, video display is performed in the A area 5 and the B area 6.

  As described above, according to the video display system 1 of the present embodiment, the video distribution unit 2 alternately inputs display data obtained by dividing the video signal into left and right parts to the display unit 7, and the display unit 7 The displayed display data is separated for each display data of the left area and the right area, display is performed based on the display data corresponding to the area where the display unit 7 is located, and the display unit 7 should be displayed with one lighting. Display data that exceeds the capacity capable of storing information corresponding to the light emitting element 101 is processed in the same manner as the video distribution unit 2 and input to the next display unit 7, so that it is displayed according to the number of display units 7 connected in the horizontal direction. The amount of display data transmission data can be increased within the range that does not exceed the clock frequency for data synchronization, and the number of additional video distribution units 2 can be minimized. Attained significant cost-down than the display system.

  Further, since display data for two frames is input to the display unit 7 during one period of the synchronization clock which is a display data synchronization clock (that is, at each of the rise and fall of the synchronization clock). Since the display data is input), the display data input speed can be increased without increasing the frequency of the synchronization clock. This means that the display data input speed can be increased without increasing the frequency of the synchronization clock, and when the maximum number of clocks for synchronization is fixed and the clock frequency cannot be increased further. It is extremely effective.

  According to the present invention, the number of video distribution units can be reduced within the range of the clock frequency for synchronizing display data by the number of display units connected in the horizontal direction, and the cost can be greatly reduced as compared with the conventional video display system. It can be applied to a video display system for the purpose of advertising and advertising.

The block diagram which shows schematic structure of the video display system which concerns on one embodiment of this invention The block diagram which shows schematic structure of the video distribution unit in the video display system of FIG. Timing chart of video signal output from video distribution unit in video display system of FIG. FIG. 1 is a relationship diagram of video signals and display data in the video display system of FIG. The block diagram which shows schematic structure of the display unit in the video display system of FIG. Conceptual diagram of display data division of display unit in video display system of FIG. Arrangement of light emitting elements of display unit in conventional video display system The block diagram which shows schematic structure of the conventional video display system Timing chart of video signal in conventional video display system The block diagram which shows schematic structure of the display unit in the conventional video display system Block diagram showing a schematic configuration of a conventional video display system when the allowable frequency range is exceeded

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Video display system 2 Video distribution unit 3 Video transmission apparatus 4 Display medium 5 A area of display medium 6 B area of display medium 7 Display unit 21 Video signal control circuit 22 Frame data storage memory 23 Video signal generation circuit 24 Clock generation circuit 71 Display Data Dividing Circuit 72 Display Data Receiving Circuit 73 Memory for Temporarily Securing Undisplayed Data 74 Memory 75 Display Data Generating Circuit 76 Latch Circuit 77 Light Emitting Element Lighting Circuit 101 Light Emitting Element

Claims (2)

In a video display system having a display unit configured by arranging a plurality of light emitting elements emitting red, green, and blue,
The display unit is
Display data acquisition means for acquiring display data at the rising and falling timings of the synchronization clock for display data input from the outside;
Display data dividing means for distributing display data synchronized with the synchronization clock into data used at the current display timing and data used at the next display timing;
Storage means for temporarily storing data used at the next display timing distributed by the display data dividing means;
Display data generating means for synthesizing data used at the current display timing distributed by the display data dividing means and data stored in the storage means to generate display data synchronized with the synchronization clock;
A video display system comprising: A video display system having a video distribution unit for inputting display data and a clock for synchronizing the display data to the display unit of the video display system according to claim 1.
The video distribution unit includes:
A video display system comprising display data output means for outputting different display data at the rise and fall of the synchronization clock.

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