JP2004112671A - Waveform-shaping circuit, oscillator circuit, and integrated circuit for protecting against overcharging and discharging - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a consumed electric current due to a DC pass current accompanying waveform shaping, and avoid adverse effects to a peripheral analog circuit via a power supply. <P>SOLUTION: The waveform shaping circuit 1 comprises a first inverter circuit 2 of C-MOS configuration for example, a second inverter circuit 3 for inputting an output signal of the first inverter circuit 2, and reversing and outputting the same signal, and a feedback circuit 4, obtained by connecting first and second P-MOSs and first and second N-MOSs in series. In the feedback circuit 4, an output signal of the second inverter circuit 3 and an input signal into the first inverter circuit 2 are inputted, and a feedback signal for shaping the waveform of the input signal into the third inverter circuit 3 is prepared and is fed back to an output of the first inverter circuit 2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a waveform shaping circuit for shaping and outputting an input signal, and more particularly, to a waveform shaping circuit suitable for performing waveform shaping with low current consumption, an oscillation circuit using the same, and an integrated circuit for overcharge / discharge protection. It concerns the circuit.
[0002]
[Prior art]
A conventional waveform shaping circuit will be described with reference to FIGS.
[0003]
8 is a circuit diagram showing a configuration example of a conventional oscillation circuit. FIG. 9 is an explanatory diagram showing input / output waveforms of the oscillation circuit in FIG. 8, and FIG. 10 shows a configuration example of a conventional waveform shaping circuit. FIG. 11 is a circuit diagram, and FIG. 11 is an explanatory diagram showing input and output waveforms of the waveform shaping circuit in FIG.
[0004]
The circuit shown in FIG. 8 constitutes an oscillation circuit built in the integrated circuit. The integrated circuit 50A incorporates an oscillation inverter 51, a feedback resistor 52, and transistors 56 to 59 constituting an amplification inverter. ing.
[0005]
A feedback resistor 52 is connected between the input and output of the oscillation inverter 51, and an external crystal oscillator 53 is connected in parallel. External capacitors 54 and 55 are connected between both ends of the crystal oscillator 53 and the ground.
[0006]
As shown in FIG. 9A, the oscillation inverter 51 outputs a sine wave signal v1 having a potential of half the power supply voltage (VDD / 2) as the center of the amplitude. This signal v1 is amplified and waveform-shaped by a first-stage amplification inverter constituted by transistors 56 and 57 and a second-stage amplification inverter constituted by transistors 58 and 59.
[0007]
As a result, a substantially rectangular internal clock signal v2 as shown in FIG. 9B is output.
[0008]
However, in this crystal oscillation circuit, when the driving capability is increased, as shown in FIG. 9B, an overshoot occurs at the rising edge of the output waveform, and an undershoot occurs at the falling edge, which causes harmonic noise. was there.
[0009]
To solve such a problem, a circuit shown in FIG. 10 is disclosed as an oscillation circuit that does not generate overshoot or undershoot and does not generate harmonic noise even when the rising and falling edges of the output waveform are steep. 1.
[0010]
[Patent Document 1]
JP-A-11-340740
In FIG. 10, the integrated circuit 70B incorporates an oscillation inverter 71, a feedback resistor 72, and transistors 76 to 83 constituting an amplification inverter. A feedback resistor 72 is connected between the input and the output of the oscillation inverter 71, and an external crystal oscillator 73 is connected in parallel. External capacitors 74 and 75 are connected between both ends of the crystal oscillator 73 and the ground.
[0012]
As shown in FIG. 11A, the oscillation inverter 71 outputs a sine wave signal v1 having a potential of half the power supply voltage (VDD / 2) as the center of the amplitude. This signal v1 is amplified and waveform-shaped by a first-stage amplifying inverter composed of transistors 76 and 77, and then further amplified by a second-stage amplifying inverter composed of transistors 78 to 83 to form a waveform. Be shaped.
[0013]
The second-stage amplification inverter includes two N-channel transistors 78 and 80 connected in cascade (series) and two P-channel transistors 79 and 81 connected in cascade (series).
[0014]
Between the source and the drain of the N-channel transistor 80 connected to the high potential side of the power supply, an N-channel transistor 82 whose gate and source are short-circuited and constitutes a low-current circuit is connected. Similarly, a P-channel transistor 83 having a gate and a drain short-circuited and constituting a low-current circuit is connected between the source and the drain of the P-channel transistor 81 connected to the low potential side of the power supply.
[0015]
According to the circuit configuration shown in FIG. 10, the oscillation waveform output from the second-stage amplifying inverter has overshoot and undershoot as shown in FIG. The internal clock signal v2 'has a substantially rectangular waveform with no shoot. The reason is described below.
[0016]
At the rise, the high drive capability is secured by the operation of the N-channel transistor 82 and the voltage rises sharply. However, the output voltage v2 'approaches the power supply voltage VDD, and the difference between the gate voltage of the N-channel transistor 82 and the power supply voltage VDD is threshold. When the voltage becomes lower than the value voltage, the N-channel transistor 82 is turned off, and the driving capability is reduced. As a result, overshoot is suppressed.
[0017]
In the fall, the high drive capability is ensured by the action of the P-channel transistor 83, and the output falls sharply, but the output voltage v2 'approaches the ground potential, and the difference between the gate voltage of the P-channel transistor 83 and the ground potential is threshold. When the voltage becomes lower than the value voltage, the P-channel transistor 83 is turned off, and the driving capability is reduced. As a result, undershoot is suppressed.
[0018]
As described above, according to the waveform shaping circuit having the configuration shown in FIG. 10, by devising the configuration of the final stage of the amplifying inverter, overshoot and undershoot occur even though the rising and falling edges of the output waveform are steep. No harmonic noise is generated.
[0019]
However, even in such a waveform shaping circuit, the DC path current (through current = P-MOS and N-MOS constituting the C-MOS inverter circuit due to the dulling of the input pulse) in the C-MOS inverter circuit composed of each transistor is also used. Power is consumed due to the current flowing when both transistors are turned on).
[0020]
Such an increase in the DC path current has an adverse effect on the power supply voltage, such as switching noise and ripple, and becomes a serious problem particularly in an analog circuit embedded IC.
[0021]
[Problems to be solved by the invention]
The problems to be solved are that the conventional technology cannot reduce the current consumption due to the DC path current accompanying the waveform shaping, and cannot avoid adversely affecting peripheral analog circuits via the power supply.
[0022]
SUMMARY OF THE INVENTION An object of the present invention is to solve these problems of the prior art and improve the performance and reliability of a waveform shaping circuit.
[0023]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a waveform shaping circuit for shaping and outputting an input signal, a first inverter circuit having, for example, a C-MOS configuration for inputting an input signal, shaping the waveform, and outputting the input signal. A second inverter circuit of, for example, a C-MOS configuration which receives an output signal of the first inverter circuit and inverts the output signal, and receives an output signal of the second inverter circuit and an input signal to the first inverter circuit. And a feedback circuit that generates a feedback signal for shaping an input signal to the second inverter circuit and feeds it back to an output of the first inverter circuit.
As the feedback circuit, for example, a first P-MOS in which the drain is connected to the high potential side of the power supply to input the input signal to the gate, and a drain is connected to the source of the first P-MOS A second P-MOS for inputting the output signal of the second inverter circuit to the gate, and a source connected to the source of the second P-MOS for inputting the output signal of the second inverter circuit to the gate. Using a first N-MOS and a second N-MOS having a source connected to the drain of the first N-MOS and a drain connected to the lower potential side of the power supply to input an input signal to the gate; An output line of the first inverter circuit and an input line to the second inverter circuit are connected to the sources of the second P-MOS and the first N-MOS.
Further, a first constant current circuit composed of, for example, a P-channel MOS transistor for connecting the first inverter circuit to the high potential side of the power supply, and an N-channel MOS transistor for connecting the first inverter circuit to the low potential side of the power supply , A third constant current circuit such as a P-channel MOS transistor for connecting a feedback circuit to the high potential side of the power supply, and an N-channel connection for connecting the feedback circuit to the low potential side of the power supply A fourth constant current circuit including a MOS transistor is provided.
Then, the waveform shaping circuits having these configurations are provided in the transmission circuit and the overcharge / discharge protection integrated circuit.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
FIG. 1 is a block diagram showing a configuration example of a waveform shaping circuit according to the present invention, FIG. 2 is an explanatory diagram showing a first operation example of the waveform shaping circuit in FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing a second operation example of the waveform shaping circuit, FIG. 4 is an explanatory diagram showing a third operation example of the waveform shaping circuit in FIG. 1, and FIG. 5 is a fourth operation example of the waveform shaping circuit in FIG. FIG.
[0026]
The waveform shaping circuit 1 of the present embodiment shown in FIG. 1 is a low current consumption type waveform shaping circuit, which is a P-MOS transistor M1h and an N-MOS which inputs an external input signal OSC, shapes the waveform, and outputs the waveform. A first inverter circuit 2 of a C-MOS configuration including a transistor M2h, a second inverter circuit 3 of a C-MOS configuration for inputting and inverting and outputting an output signal of the first inverter circuit 2; The second inverter circuit 3 receives the output signal of the first inverter circuit 2 and the input signal OSC to the first inverter circuit 2 to generate a feedback signal for shaping the input signal to the second inverter circuit 3. And a feedback circuit 4 for feeding back to the output.
[0027]
The feedback circuit 4 includes a first P-MOS transistor M3h having a drain connected to the high potential VDD side of the power supply to input the input signal OSC to the gate, and a source connected to the first P-MOS transistor M3h. A second P-MOS transistor M4h having a drain connected to input the output signal of the second inverter circuit 3 to the gate; and a second inverter connected to the source of the second P-MOS transistor M4h by connecting the source to the source. A first N-MOS transistor M5h for inputting the output signal of the circuit 3 to the gate; a source connected to the drain of the first N-MOS transistor M5h; and a drain connected to the low potential VSS side of the power supply to input the signal. A second N-MOS transistor M6h for inputting OSC to the gate; Beauty and the input lines to the second inverter circuit 3 is configured connected to the second P-MOS transistor M4h and the source of the first N-MOS transistor M5H.
[0028]
Further, the first inverter circuit 2 includes a P-MOS transistor Mip0 as a first constant current circuit that connects the drain of the P-MOS transistor M1h included in the first inverter circuit 2 to the high potential VDD side of the power supply. An N-MOS transistor Min1 as a second constant current circuit for connecting the drain of the N-MOS transistor M2h to the low potential VSS side of the power supply, and a drain of the first P-MOS transistor M3h for the feedback circuit 4 P-MOS transistor Mip1 as a third constant current circuit connecting the power supply to the high potential VCC side of the power supply;
An N-MOS transistor Min0 as a fourth constant current circuit that connects the drain of the second N-MOS transistor M6h constituting the feedback circuit 4 to the low potential VSS side of the power supply is provided.
[0029]
In such a configuration, in the waveform shaping circuit 1 of the present example, the waveform shaping of the triangular waveform input signal OSC indicated by the broken line in FIGS. 2 to 5 is input to the first inverter circuit 2.
[0030]
The first inverter circuit 2 is a C-MOS inverter, and can output a signal having a waveform that rises and falls sharply with respect to the input signal OSC.
[0031]
Since the current of the first inverter circuit 2 is limited by the P-MOS transistor Mip0 and the N-MOS transistor Min1, the power supply DC path current (through current) of the C-MOS inverter is extremely small.
[0032]
However, the output signal from the first inverter circuit 2 is still a signal having a slightly rounded waveform as shown by a two-dot chain line in FIG. The output signal from the first inverter circuit 2 is input to the second inverter circuit 3 and inverted and output.
[0033]
In the waveform shaping circuit 1 of the present embodiment, positive feedback is applied to the output signal from the first inverter circuit 2 by the feedback circuit 4 using the signal inverted and output by the second inverter circuit 3. It is shaped.
[0034]
That is, in the feedback circuit 4, the input signal OSC is input to the gates of the first P-MOS transistor M3h and the second N-MOS transistor M6h, and the signal inverted and output by the second inverter circuit 3 is output. Input to the gates of the second P-MOS transistor M4h and the first N-MOS transistor M5h (out → NET).
[0035]
The output line (A) of the first inverter circuit 2 and the input line (in) of the second inverter circuit 3 are connected to the sources of the second P-MOS transistor M4h and the first N-MOS transistor M5h. And a feedback circuit 4 applies positive feedback to the output signal of the first inverter circuit 2, that is, the input signal of the second inverter circuit 3, using the signal inverted and output by the second inverter circuit 3. It has a configuration.
[0036]
With such a configuration, the input to the second inverter circuit 3 is a combination of the output of the first converter circuit 2 and the output of the feedback circuit 4, and the positive feedback signal is added and shaped. It will be.
[0037]
By shaping the input to the second inverter circuit 3 in this manner, the output of the second inverter circuit 3 becomes a signal with no sharpness and a sharp rise and fall as shown by a solid line in FIG. It becomes.
[0038]
Further, since the input to the second inverter circuit 3 is sharpened, the through current in the C-MOS constituting the second inverter circuit 3 is reduced.
[0039]
Furthermore, by providing the P-MOS transistor Mip1 and the N-MOS transistor Min0 as a constant current circuit for the feedback circuit 4, the occurrence of "overshoot" and "undershoot" in the feedback circuit 4 can be suppressed. .
[0040]
A voltage change at a node or the like between the source of the first P-MOS transistor M3h and the drain of the second P-MOS transistor M4h constituting the feedback circuit 4 is indicated by a dotted line in FIG. The voltage change at a node or the like between the drain of the first N-MOS transistor M5h and the source of the second N-MOS transistor M6h is indicated by a chain line in FIG.
[0041]
Next, an example in which the waveform shaping circuit 1 having such a configuration is provided in an oscillation circuit and an integrated circuit for overcharge / discharge protection will be described with reference to FIGS.
[0042]
FIG. 6 is a block diagram showing a configuration example of an oscillation circuit provided with the waveform shaping circuit in FIG. 1, and FIG. 7 shows a configuration example of an overcharge / discharge protection integrated circuit provided with the waveform shaping circuit in FIG. It is a block diagram.
[0043]
The oscillation circuit in FIG. 6 includes a waveform shaping circuit 1 shown in FIG. 1, an oscillator (described as an “oscillation circuit”) 20 for generating an input signal OSC to be input to the waveform shaping circuit 1, and a waveform shaping. It comprises a circuit 1 and a power supply section (described as an “Iref circuit”) 30 for supplying power to the transmitter 20.
[0044]
The power supply unit 30 generates VDD, VSS, Irefp, and Irefn from a power supply supplied from outside (not shown), and supplies power to the waveform shaping circuit 1 and the transmitter 20.
[0045]
The transmitter 20 has a configuration in which two inverters INV1 and INV2 are connected in series, and the output terminals of the respective inverters INV1 and INV2 are connected to VSS via capacitors C1 and C2. And generates a triangular wave having a waveform indicated by a broken line and outputs the generated triangular wave as an OSC signal.
[0046]
The triangular wave (OSC signal) is input to the waveform shaping circuit 1 and shaped as described above with reference to FIGS. The waveform shaping circuit 1 can perform such waveform shaping with low current consumption, and can also save power for the oscillation circuit of this example.
[0047]
The overcharge / discharge protection integrated circuit in FIG. 7 is an IC for overcharge, overdischarge and overcurrent protection of a Li-ion / Li polymer secondary battery by a high-voltage C-MOS process. Cell overcharge, overdischarge, discharge overcurrent, and charge overcurrent can be detected.
[0048]
Inside are four voltage detectors (described as "VD1 to VD4" in the figure), a short-circuit detection circuit (described as "Short Detector" in the figure), a reference voltage source, an oscillation circuit (described as "Oscillator" in the figure), and a counter. The circuit includes a circuit (described as “Counter” in the figure), a delay circuit (described as “Delay” in the figure), a logic circuit (described as “Logic Circuit” in the figure), and the like.
[0049]
In a semiconductor device that controls charging and discharging of a secondary battery, a clock signal for a delay time counter is required. However, this clock signal causes a problem that noise affects an analog circuit via a power supply. appear. In the integrated circuit for overcharge / discharge protection of this example, by providing the waveform shaping circuit 1 shown in FIG. 1 in the oscillation circuit (Oscillator), such an adverse effect on the analog circuit can be prevented.
[0050]
With such a configuration, when the overcharge / discharge protection integrated circuit in FIG. 7 detects overcharge or overcharge current, the COUT output becomes “L” level after a delay time fixed inside the IC, and When the discharge or discharge overcurrent is detected, the DOUT output becomes “L” level after a fixed delay time inside the IC.
[0051]
After overcharge detection and charge overcurrent detection, if the battery voltage drops below the overcharge detection voltage after disconnecting the charger and connecting the load, the battery returns from the overcharge state and the charge overcurrent state, and the COUT output becomes “H”. Become a level. In a state where the charger is still connected after the overcharge detection, the battery does not return from the overcharge state even if the battery voltage becomes lower than the overcharge detection voltage.
[0052]
After the overdischarge is detected, if the battery voltage becomes higher than the overdischarge detection voltage after connecting the charger, the battery returns from the overdischarge state, and the DOUT output becomes the “H” level. After the detection of the discharge overcurrent and the detection of the short circuit, the load is released to recover from the discharge overcurrent state and the short circuit state, and the DOUT output becomes “H” level.
[0053]
The current consumption after the detection of overdischarge is suppressed as much as possible by stopping the internal circuit.
[0054]
Further, by using the DS terminal, the test time of the protection circuit board can be reduced. When the DS terminal is set to the VDD level, the delay time other than the detection of the short circuit can be shortened. In particular, the overcharge detection delay time is about 1/90. When the DS terminal is set to an intermediate level, overcharge detection and charging overcurrent detection are output without passing through a delay circuit, so that the detection delay time is several tens of μs. The output form is a CMOS output.
[0055]
As described above with reference to FIGS. 1 to 7, in this example, in the waveform shaping operation, the power supply DC path current can be extremely reduced, and the power supply voltage fluctuation due to the waveform shaping can be suppressed. In addition to eliminating the adverse effects on analog circuits, it is possible to generate sharp waveforms that do not cause overshoot or undershoot and do not generate high-frequency noise, even though the rise and fall of the waveform are steep. Can go down.
[0056]
Further, in the waveform shaping circuit 1 of the present example, the feedback circuit 4 is provided, so that the waveform can be sharpened. Further, in this example, the current limiting transistors Mip0,1 and Min0,1 are provided, so that the DC path current can be reduced, the adverse effect on peripheral circuits can be avoided, and the current consumption can be reduced. .
[0057]
In addition, by providing the waveform shaping circuit of the present example in an oscillation circuit in an integrated circuit for controlling charging / discharging of a secondary battery, the waveform of a clock signal for a counter for generating a delay time is sharpened. This can prevent the noise of the clock signal from adversely affecting the analog circuit via the power supply.
[0058]
The present invention is not limited to the examples described with reference to FIGS. 1 to 7, and can be variously modified without departing from the gist thereof. For example, in this example, a C-MOS is used as the second inverter circuit 3 in order to reduce current consumption. However, other inverters such as those using only an N-MOS and those using a bipolar transistor are used. A configuration may be adopted.
[0059]
Further, in the example shown in FIG. 6, the oscillator is configured using the two inverter circuits INV1 and INV2, but an oscillation circuit including a crystal oscillator or LC and CR may be used.
[0060]
【The invention's effect】
According to the present invention, there are the problems that the current consumption due to the DC path current associated with the waveform shaping cannot be reduced and the problem that the peripheral analog circuits cannot be adversely affected via the power supply cannot be avoided. It is possible to improve the performance and reliability of the waveform shaping circuit, the oscillation circuit using the same, and the integrated circuit for overcharge / discharge protection.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a waveform shaping circuit according to the present invention.
FIG. 2 is an explanatory diagram showing a first operation example of the waveform shaping circuit in FIG. 1;
FIG. 3 is an explanatory diagram showing a second operation example of the waveform shaping circuit in FIG. 1;
FIG. 4 is an explanatory diagram showing a third operation example of the waveform shaping circuit in FIG. 1;
FIG. 5 is an explanatory diagram showing a fourth operation example of the waveform shaping circuit in FIG. 1;
6 is a block diagram illustrating a configuration example of an oscillation circuit provided with a waveform shaping circuit in FIG. 1;
FIG. 7 is a block diagram showing a configuration example of an overcharge / discharge protection integrated circuit provided with the waveform shaping circuit in FIG. 1;
FIG. 8 is a circuit diagram illustrating a configuration example of a conventional oscillation circuit.
9 is an explanatory diagram showing input / output waveforms of the oscillation circuit in FIG.
FIG. 10 is a circuit diagram illustrating a configuration example of a conventional waveform shaping circuit.
11 is an explanatory diagram showing input and output waveforms of the waveform shaping circuit in FIG.
[Explanation of symbols]
1: Waveform shaping circuit, 2: First inverter circuit, 3: Second inverter circuit, 4: Feedback circuit, 20: Oscillator ("oscillation circuit"), 30: Power supply unit ("Iref circuit"), 50A: Integrated circuit, 51: oscillation inverter, 52: feedback resistor, 53: crystal oscillator, 54, 55: capacitor, 56 to 59: transistor, 70B: integrated circuit, 71: oscillation inverter, 72: feedback resistor, 73: Crystal oscillators, 74 and 75: capacitors, 76 to 83: transistors.

Claims (7)

A waveform shaping circuit for shaping and outputting an input signal;
A first inverter circuit that receives the input signal, shapes the waveform, and outputs the shaped signal;
A second inverter circuit that receives an output signal of the first inverter circuit and inverts the output signal,
A feedback circuit which receives an output signal of the second inverter circuit and the input signal, generates a feedback signal for shaping an input signal to the second inverter circuit, and feeds it back to an output of the first inverter circuit; A waveform shaping circuit comprising: A waveform shaping circuit for shaping and outputting an input signal;
A first inverter circuit having a C-MOS configuration for inputting the input signal, shaping the waveform, and outputting the input signal;
A second inverter circuit having a C-MOS configuration for inputting an output signal of the first inverter circuit and inverting and outputting the output signal;
A feedback circuit which receives an output signal of the second inverter circuit and the input signal, generates a feedback signal for shaping an input signal to the second inverter circuit, and feeds it back to an output of the first inverter circuit; A waveform shaping circuit comprising: A waveform shaping circuit according to any one of claims 1 and 2,
The feedback circuit,
A first P-MOS having a drain connected to the high potential side of the power supply and inputting the input signal to a gate;
A second P-MOS having a drain connected to a source of the first P-MOS and inputting an output signal of the second inverter circuit to a gate;
A first N-MOS having a source connected to the source of the second P-MOS and inputting an output signal of the second inverter circuit to a gate;
A second N-MOS having a source connected to a drain of the first N-MOS, a drain connected to a low potential side of a power supply, and inputting the input signal to a gate,
A waveform shaping circuit, wherein an output line of the first inverter circuit and an input line to the second inverter circuit are connected to the sources of the second P-MOS and the first N-MOS. The waveform shaping circuit according to any one of claims 1 to 3, wherein
A first constant current circuit connecting the first inverter circuit to a high potential side of a power supply;
A second constant current circuit connecting the first inverter circuit to a low potential side of a power supply;
A third constant current circuit connecting the feedback circuit to a high potential side of a power supply;
A fourth constant current circuit that connects the feedback circuit to a low potential side of a power supply. The waveform shaping circuit according to claim 4, wherein
The first constant current circuit and the third constant current circuit are composed of P-channel MOS transistors,
A waveform shaping circuit, wherein the second constant current circuit and the fourth constant current circuit comprise N-channel MOS transistors. 6. A transmitting circuit, comprising: the waveform shaping circuit according to claim 1; and transmitting means for generating a signal to be input to the waveform shaping circuit. An overcharge detection circuit for detecting overcharge at the time of charging the secondary battery;
An overdischarge detection circuit for detecting overdischarge at the time of discharging the secondary battery,
A discharge overcurrent detection circuit for detecting an overcurrent when the secondary battery is discharged,
A charge overcurrent detection circuit that detects an overcurrent during charging of the secondary battery;
A short-circuit detection circuit that detects a short-circuit during charging and discharging of the secondary battery;
An oscillating circuit that oscillates by receiving the detection result of each detection circuit;
6. The waveform shaping circuit according to claim 1, wherein a signal oscillated by the oscillating means is input to perform waveform shaping.
A counter circuit for generating and outputting an operation clock for each internal circuit based on the signal shaped by the waveform shaping circuit.

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