JP2004095884A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor on the same substrate, wherein depletioning of a gate electrode is suppressed to obtain a sufficient on-current. <P>SOLUTION: This arrangement contains the steps of: forming a gate insulating film 4 on a substrate 1; depositing a first polysilicon film 5 doped with a p-type impurity on the entire surface; depositing a second polysilicon film 6 non-doped on the entire surface; patterning the first and second polysilicon films 5, 6 in a gate electrode shape; selectively ion-implanting the p-type impurity in a pMOS transistor formation region on the substrate 1; selectively ion-implanting an n-type impurity in an nMOS transistor formation region on the substrate 1; and activating the impurity in the gate electrode by a heat treatment. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dual-gate CMOS transistor using a p-type polysilicon film for a gate electrode of a pMOS transistor and an n-type polysilicon film for a gate electrode of an nMOS transistor.
[0002]
[Prior art]
The dual gate type CMOS transistor is used as a circuit element of a semiconductor integrated circuit having a sub-micron size or less, since the pMOS transistor and the nMOS transistor are both surface channel types, so that a short channel effect hardly occurs. However, when the CMOS transistor is further miniaturized, there arises a problem that it becomes difficult to obtain a sufficient on-current due to depletion of a gate electrode formed of a polysilicon film. This is because heat treatment for activating impurities in the gate electrode cannot be performed sufficiently.
[0003]
To manufacture a dual gate type CMOS transistor, a non-doped polysilicon film is usually deposited on a gate oxide film and patterned into a gate electrode shape, and then a p-type impurity such as boron (B) and an nMOS transistor are formed in a pMOS transistor region. A method is used in which an n-type impurity such as phosphorus (P) is ion-implanted into the region, and then heat treatment is performed to activate the impurity in the gate electrode. When the CMOS transistor is miniaturized, a high-temperature and short-time heat treatment must be performed so that the impurities implanted in the source / drain regions are not diffused more than necessary. However, under such heat treatment conditions, the impurities in the gate electrode are removed by the gate oxide film. It does not diffuse and activate sufficiently to the interface, which leads to depletion of the gate electrode.
[0004]
Therefore, a method has been proposed in which polysilicon doped with impurities is deposited on a gate oxide film without using ion implantation to form a gate electrode.
FIG. 3 is a process sectional view for explaining a conventional example of a dual gate type CMOS transistor (Japanese Patent Application Laid-Open No. Hei 8-204028). As shown in FIG. 1A, after an element isolation region 12 is formed in a p-type silicon substrate 11, an N well layer 13 is provided in a pMOS transistor region, and a gate oxide film 14 is formed on the entire surface. Then, a polysilicon film 15 doped with phosphorus is deposited on the entire surface by a CVD method. Next, as shown in FIG. 2B, the polysilicon film 15 in the pMOS transistor region is selectively removed by etching while leaving the polysilicon film 15 only in the nMOS transistor region, and then polysilicon doped with boron is formed thereon. A film 16 is deposited on the entire surface by a CVD method.
[0005]
Then, as shown in FIG. 3C, the pMOS transistor region is masked with a photoresist 17 and phosphorus is selectively ion-implanted into the nMOS transistor region to convert the polysilicon film 16 in the nMOS transistor region into n-type. .
Thereafter, p-type gate electrodes and n-type gate electrodes are formed in the pMOS transistor region and the nMOS transistor region by patterning the polysilicon films 15 and 16, respectively, and a heat treatment for activating impurities is performed.
[0006]
According to the above configuration, the polysilicon film 16 doped with boron is used as the p-type gate electrode, and the polysilicon film 15 doped with phosphorus is used as the n-type gate electrode. No damage is caused by ion implantation into the gate electrode, and impurities are supplied to the vicinity of the gate oxide film interface in advance, so that the gate electrode can be activated by heat treatment at high temperature for a short time to prevent depletion thereof. However, there is a problem that the gate oxide film 14 is damaged by etching in the step of etching and removing the polysilicon film 15 in the pMOS transistor region, thereby deteriorating the characteristics of the gate oxide film 14.
[0007]
FIG. 4 is a process sectional view for explaining another conventional example in which a gate electrode of a dual gate type CMOS transistor is manufactured using a polysilicon film doped with an impurity, and those having the same functions are denoted by the same reference numerals. (JP-A-5-13697). As shown in FIG. 1A, after a gate oxide film 14 is formed on a p-type silicon substrate 11, a polysilicon film 18 doped with boron is deposited on the entire surface by a CVD method. Next, as shown in FIG. 3B, the polysilicon film 18 in the nMOS transistor region is changed from p-type to n-type by masking the pMOS transistor region with the oxide film 19 and thermally diffusing phosphorus to substitute boron. Convert. Thereafter, a p-type gate electrode and an n-type gate electrode are formed in the pMOS transistor region and the nMOS transistor region by patterning the polysilicon film 18, respectively. In the above configuration, since the ion implantation step is not included, damage to the gate oxide film due to ion implantation is suppressed.
[0008]
[Problems to be solved by the invention]
In the process of manufacturing the CMOS transistor described with reference to FIG. 4, the p-type gate electrode is formed of a boron-doped polysilicon film, while the n-type gate electrode is formed from the surface of the boron-doped polysilicon film. The phosphorus is thermally diffused to replace boron and convert to n-type. In order to suppress the depletion by replacing boron in the entire gate electrode with phosphorus as in this method, a high-temperature and long-time heat treatment is required. As a result, channel impurities implanted in the substrate and impurities in the source / drain regions are removed. The distribution collapses, and it becomes difficult to manufacture a fine CMOS transistor.
[0009]
Therefore, an object of the present invention is to obtain a sufficient ON current by suppressing depletion of a gate electrode.
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, in a method for manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor on the same substrate, a step of forming a gate insulating film on the substrate and a step of forming a first polysilicon film doped with a p-type impurity are performed. Depositing over the entire surface, depositing a non-doped second polysilicon film over the entire surface, patterning the first and second polysilicon films into a gate electrode shape, and forming a pMOS transistor on the substrate Selectively ion-implanting a p-type impurity into a region, selectively ion-implanting an n-type impurity into an nMOS transistor formation region on the substrate, and activating the impurity in the gate electrode by a heat treatment. A p-type gate electrode is formed in the transistor formation region, and an n-type gate electrode is formed in the nMOS transistor formation region. It is achieved by the method for manufacturing a semiconductor device characterized by comprising the step.
[0011]
According to the present invention, since the gate electrode has a two-layer structure of the first polysilicon film and the second polysilicon film, the first polysilicon film is made thinner and the second polysilicon film is formed instead. By increasing the thickness, the thickness of the entire gate electrode can be set to a predetermined value. In this case, in the nMOS transistor region, the n-type impurity implanted in the second polysilicon film quickly diffuses through the thin first polysilicon film and reaches the gate insulating film interface. Can be easily converted from the p-type to the n-type, and the depletion of the n-type gate electrode can be suppressed under the heat treatment condition which is less relaxed than the conventional one. In addition, as a result of relaxing the heat treatment conditions, a change in the impurity distribution in the source / drain regions is suppressed, and desired transistor characteristics can be easily obtained.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a process sectional view showing an embodiment of the present invention. As shown in FIG. 1A, after an element isolation region 2 made of an oxide film is formed on a p-type silicon substrate 1, an N well layer 3 is formed.
Thereafter, the surface of the silicon substrate 1 is thermally oxidized to form a gate oxide film 4 having a thickness of about 3 nm. The region where the N well layer 3 is formed on the silicon substrate 1 is a pMOS transistor formation region, and the other region is an nMOS transistor formation region.
[0013]
Next, a polysilicon film 5 doped with boron is deposited on the entire surface by using the CVD method. The boron concentration of the polysilicon film 5 was 1 × 10 ²⁰ cm ⁻³ , and the film thickness was 20 nm. Subsequently, a non-doped polysilicon film 6 is deposited on the entire surface by using the CVD method. The non-doped polysilicon film 6 has a thickness enough to form a gate electrode together with the boron-doped polysilicon film 5, for example, 100 nm.
[0014]
Then, the polysilicon films 5 and 6 are patterned by using a photolithography technique, and as shown in FIG. 1B, gate electrodes 7 and 8 are formed in a pMOS transistor region and an nMOS transistor region, respectively. Side walls 9 and 10 are provided on the side walls of the electrodes 7 and 8. Then, the nMOS transistor formation region is masked with the photoresist 11 and boron is selectively ion-implanted into the pMOS transistor region to form the source / drain region 12. As an ion implantation condition at this time, an acceleration voltage of 1 to 10 keV and a dose of 2 × 10 ¹⁴ to 8 × 10 ¹⁵ cm ⁻² can be used.
[0015]
Then, as shown in FIG. 1C, the source / drain region 14 was formed by selectively implanting phosphorus into the nMOS transistor region while masking the pMOS transistor formation region with the photoresist 13. As an ion implantation condition at this time, an acceleration voltage of 1 to 10 keV and a dose of 2 × 10 ¹⁴ to 8 × 10 ¹⁵ cm ⁻² can be used. Finally, heat treatment for activating impurities in the gate electrodes 7 and 8 and the source / drain regions 12 and 14 is performed. As the heat treatment conditions, a temperature of 900 to 1100 ° C. and a heat treatment time of 1 to 10 seconds can be used.
[0016]
FIGS. 2A and 2B show the CV characteristics of the gate electrodes of the nMOS transistor and the pMOS transistor manufactured by the above steps, respectively. FIG. 3 also shows, for comparison, the CV characteristics of the gate electrodes of the nMOS transistor and the pMOS transistor manufactured using the normal ion implantation method, and the heat treatment conditions are the same.
[0017]
As shown in the figure, when the gate voltage is applied in the reverse direction, no change is observed in the gate capacitance in the gate electrode according to the present invention, whereas the gate capacitance decreases in the conventional gate electrode. I understand that it goes.
In the present invention, the polysilicon film in the portion of the gate electrode that is in contact with the gate oxide film is thinned, so that the activation of impurities is facilitated and the depletion of the gate electrode is suppressed. This indicates that the activation of impurities at the film interface is not sufficient under the above-mentioned heat treatment conditions and depletion of the gate electrode occurs. To prevent this, heat treatment at a higher temperature and longer time is required.
[0018]
In the above-described embodiment, the polysilicon film 5 doped with boron is deposited as the first polysilicon film by the CVD method. Also, damage to the gate oxide film due to ion implantation can be suppressed, and the same effect as that of the embodiment can be obtained.
Further, as a p-type impurity doped into the polysilicon film, an element such as indium (In) or gallium (Ga) can be used in addition to boron.
[0019]
【The invention's effect】
As described above, according to the present invention, the heat treatment conditions for activating the impurities in the gate electrode can be relaxed, which is advantageous in improving the characteristics of the dual-gate CMOS transistor.
[Brief description of the drawings]
FIG. 1 is a process sectional view showing an embodiment of the present invention.
FIG. 2 is a diagram showing CV characteristics of a gate electrode.
FIG. 3 is a process sectional view (part 1) for explaining a conventional example.
FIG. 4 is a process cross-sectional view illustrating a conventional example (part 2).
[Explanation of symbols]
Reference Signs List 1, 11 p-type silicon substrate 7 p-type gate electrode 2, 12 element isolation region 8 n-type gate electrode 3, 13 N-well layer 9, 10 sidewall 4, 14 gate oxide film 11, 13 photoresist 5 first poly Silicon film 12, 14 Source / drain region 6 Second polysilicon film

Claims (1)

In a method of manufacturing a semiconductor device having a pMOS transistor and an nMOS transistor on the same substrate,
Forming a gate insulating film on the substrate;
depositing a first polysilicon film doped with a p-type impurity over the entire surface;
Depositing a non-doped second polysilicon film over the entire surface;
Patterning the first and second polysilicon films into a gate electrode shape;
Selectively ion-implanting a p-type impurity into a pMOS transistor formation region on the substrate;
Selectively ion-implanting an n-type impurity into an nMOS transistor formation region on the substrate;
A method of manufacturing a semiconductor device, comprising: activating impurities in the gate electrode by heat treatment to form a p-type gate electrode in the pMOS transistor formation region and an n-type gate electrode in the nMOS transistor formation region.

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