JP2004087895A - Package component and its manufacturing method - Google Patents

Package component and its manufacturing method Download PDF

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Publication number
JP2004087895A
JP2004087895A JP2002248284A JP2002248284A JP2004087895A JP 2004087895 A JP2004087895 A JP 2004087895A JP 2002248284 A JP2002248284 A JP 2002248284A JP 2002248284 A JP2002248284 A JP 2002248284A JP 2004087895 A JP2004087895 A JP 2004087895A
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package
component
chip
terminal
manufacturing
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Katsuo Kawaguchi
川口　克雄
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package component which is easily manufactured, provided with a very flat surface, and compact, and to provide its manufacturing method. <P>SOLUTION: First, IC chips 11 and a copper foil 13 are prepared. The IC chips 11 and the copper foil 13 are arranged as the surfaces of the IC chips 11 where terminals 18 are formed are confronted with the copper foil 13 (A). At this point, all the IC chips 11 are arranged on the same surface of the copper foil 13. Then, the IC chips 11 are mounted on the copper foil 13 (B). Next, the IC chips 11 are sealed up with a resin 12 (C). Pads 14 are formed by patterning the copper foil 13 (D). Lastly, the sealing resin 12 is cut (E). By this setup, an IC package 10 including the IC chip 11 covered with the sealing resin 12 can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は，電子部品が樹脂でモールドされたパッケージ部品とその製造方法に関する。さらに詳細には，製造が容易であって，コンパクトなパッケージ部品およびその製造方法に関するものである。
【０００２】
【従来の技術】
従来，ＩＣパッケージ３０は，図９に示すようにＩＣチップ３１の全体がモールド樹脂３２によって覆われた構造をしている。また，ＩＣパッケージ３０はリード３３を有している。そして，リード３３の一端はモールド樹脂３２内でＩＣチップ３１の端子３８と接し，他端はＩＣパッケージ３０の側面から外部に突出している。
【０００３】
このようなＩＣパッケージ３０は，図１０に示すような工程により製造される。まず，ＩＣチップ３１を用意する（図１０（Ａ））。次に，当該ＩＣチップ３１用に形成されたリード３３上にＩＣチップ３１を配置し，リード３３とＩＣチップ３１の端子３８とを接合する（図１０（Ｂ））。次に，ＩＣチップ３１を樹脂３２でモールドする（図１０（Ｃ））。これにより，ＩＣチップ３１の全体が樹脂３２で覆われる。このときリード３３の一端は，ＩＣチップ３１への入出力を可能にするために外部に突出させる。その後，リード３０を図示のように折り曲げることにより，ＩＣパッケージ３０が製造される（図１０（Ｄ））。
【０００４】
【発明が解決しようとする課題】
しかしながら，前記した従来の技術には次のような問題があった。すなわち，リード３３は非常に細く薄膜の部品であって機械的強度が非常に低い。従って，ＩＣチップ３１の端子３８の位置にリード３３を正しく合わせることは容易でない。また，リード３３が側面から突出しているため，ＩＣパッケージ３０の全体として幅方向のサイズが大きい。また，端子３８およびリード３３を覆う樹脂の厚みが６００〜１０００μｍ程度あり，厚さ方向のサイズも大きい。また，そのことを機器側の設計でも考慮しなければならず，ＩＣパッケージ３０を組み込んだ製品のサイズも大きくなる。また，樹脂でモールドされたＩＣパッケージ３０は，２０〜１００μｍ程度の凹凸があり平坦性が低い。また，１回の製造サイクルでは１個もしくは多くても２，３個のＩＣパッケージ３０を製造することしかできない。従って，生産性が非常に低い。
【０００５】
本発明は，前記した従来の技術が有する問題点を解決するためになされたものである。すなわちその課題とするところは，製造が容易であって，表面の平坦性が高く，コンパクトなパッケージ部品およびその製造方法を提供することにある。
【０００６】
【課題を解決するための手段】
この課題の解決を目的としてなされたパッケージ部品は，一面に端子を有する電子部品をパッケージしてなるパッケージ部品であって，電子部品の端子に接合されたパターン層を有し，パターン層は，電子部品の端子の直上にパターンが存在するように導体箔をパターニングしたものであり，電子部品は樹脂でモールドされ，電子部品の端子面上をモールドする樹脂の厚さは，電子部品の端子の高さ以下であるものである。
【０００７】
本発明のパッケージ部品は，電子部品の端子の直上に導体箔をパターニングしたパターン層を有している。そして，当該パターン層を介して電子部品の端子にアクセスできるようになっている。すなわち，本発明のパッケージ部品はリードを設ける必要がない。従って，従来のパッケージ部品と比較して幅方向にコンパクトである。また，電子部品の端子面上の樹脂の厚さは，当該電子部品の端子の高さ以下である。従って，従来のパッケージ部品と比較して厚さ方向にもコンパクトである。また，表面のパターン層を，元々１枚の導体箔から形成することとすれば，その厚みが均一である。従って，パッケージ部品の表面の平坦性が高い。
【０００８】
また，本発明のパッケージ部品は，複数の電子部品を含み，各電子部品ともその端子が前記パターン層に接合されているものであってもよい。このパッケージ部品では，電子部品と他の電子部品の少なくとも１つとを，パターン層を介して電気的に接続することができる。従って，複数の電子部品の機能を組み合わせてモジュール化したパッケージ部品が提供されている。
【０００９】
また，本発明のパッケージ部品は，パターン層上に，絶縁層と配線層とを交互に積層してなるとともに層間接続構造を含む積み上げ層を有し，積み上げ層の最上層に，電子部品の端子にアクセスするパッドを有するものであってもよい。すなわち，このパッケージ部品では，積み上げ層の部分に多彩な回路を内蔵させることができる。
【００１０】
また，本発明のパッケージ部品の製造方法は，一面に端子を有する電子部品をパッケージしてなるパッケージ部品の製造方法であって，導体箔の一方の面上に電子部品を，その端子面が導体箔と向き合うように載置し，電子部品の端子と導体箔とを接合する第１工程と，第１工程にて導体箔に接合された電子部品を樹脂でモールドする第２工程と，第２工程後に，導体箔を，電子部品の端子の直上にパターンが存在するようにパターニングする第３工程とを含んでいる。
【００１１】
本発明のパッケージ部品の製造方法では，まず，導体箔の一方の面上に電子部品の端子を接合している。次に，接合された電子部品を樹脂でモールドしている。そして，電子部品の端子の直上にパターンが存在するように導体箔をパターニングしている。この製造方法では，導体箔をパターニングする時には，樹脂がモールドされているためある程度の機械的強度がある。従って，位置合わせを容易に行うことができる。
【００１２】
また，本発明のパッケージ部品の製造方法は，第１工程にて，複数個のパッケージ部品に相当する電子部品を導体箔に接合し，第３工程後に，第２工程にてモールドした樹脂をカットして個別のパッケージ部品を得るようにしてもよい。これにより，１回の製造サイクルで複数のパッケージ部品を製造することができる。従って，本発明のパッケージ部品の製造方法は生産性が高い。
【００１３】
また，本発明のパッケージ部品の製造方法は，第１工程にて複数個の電子部品を導体箔に接合し，複数個の電子部品を含むパッケージ部品を得るようにしてもよい。これにより，複数個の電子部品を内蔵した機能的なパッケージ部品を製造することができる。
【００１４】
【発明の実施の形態】
以下，本発明を具体化した実施の形態について，添付図面を参照しつつ詳細に説明する。なお，以下の形態では，ＩＣ部品を有するＩＣパッケージおよびその製造方法として本発明を適用する。
【００１５】
［第１の形態］
第１の形態のＩＣパッケージ１０は，図１に示すようにＩＣチップ１１と，ＩＣチップ１１を覆うモールド樹脂１２と，ＩＣチップ１１の図１中の下面に設けられたパッド１４とを備えている。
【００１６】
そして，ＩＣチップ１１の図１中の下面には，図２に示すようにＩＣチップ１１の端子１８が設けられており，当該端子の直上（図１では直下）にパッド１４が形成されている。そして，ＩＣチップ１１とパッド１４との間にもモールド樹脂１２が充填されている。なお，このＩＣチップ１１とパッド１４との間隔は，端子１８の高さ（１０〜５０μｍ程度）とほぼ同等である。なお，図２以外の図では，端子１８の部分や，ＩＣチップ１１とパッド１４との間のモールド樹脂を省略している。
【００１７】
ＩＣパッケージ１０は，図３に示す手順により製造される。まず，ＩＣチップ１１と銅箔１３とを用意する。そして，ＩＣチップ１１の端子１８を有する面（以下，「端子面」とする）と銅箔１３とが向き合うように載置する（図３（Ａ））。このとき，用意したすべてのＩＣチップ１１を銅箔１３の同一の面上に載置する。なお，本形態では銅箔を使用しているが，銅以外にも鉄やアルミニウム等でもよい。また，銅箔１３の厚さは９〜３５μｍ程度である。次に，ＩＣチップ１１を銅箔１３上に実装する（図３（Ｂ））。ここでいう実装とは，端子面に設けられている端子１８と銅箔１３とが接合され，電気的につながった状態にすることをいう。この実装工程は，例えば，金属接合，圧接工法，ＡＣＦ／ＡＣＰ接続，超音波接合，樹脂バンプ接合，導電性ペースト接合等により行えばよい。また，銅箔１３上には図４に示すように，複数のＩＣチップ１１を格子状に並べて実装する。なお，実際には，ＩＣチップ１１と銅箔１３との間に端子１８の高さと同等の隙間がある（図２参照）。
【００１８】
次に，ＩＣチップ１１を樹脂１２でモールドする（図３（Ｃ））。樹脂１２としては，エポキシ樹脂等の熱硬化性樹脂や，ＬＣＰ等の熱可塑性樹脂が使用可能である。なお，実際には，ＩＣチップ１１と銅箔１３との間も樹脂で充填される（図２参照）。
【００１９】
次に，銅箔１３をパターニングすることによりパッド１４を形成する（図３（Ｄ））。このパッド１４はＩＣチップ１１の端子１８の直上（図３中では直下）に形成される。また，もともとは銅箔１３であるため，表面の凹凸が５〜１０μｍ程度である。そのため，従来のＩＣパッケージと比較してその表面の平坦性は高い。また，ＩＣチップ１１は樹脂１２によりモールドされているため，パターニング時のエッチング液等の影響を受けない。また，ハンドリング時の物理的衝撃が緩和される。
【００２０】
最後に，モールド樹脂１２をカットする（図３（Ｅ））。このカットでは，ＩＣチップ１１と他のＩＣチップ１１との隙間部分のモールド樹脂１２が厚さ方向（図３中の上下）に切断される。これにより，ＩＣチップ１１がモールド樹脂１２で覆われたＩＣパッケージ１０が製造される。さらには，複数のＩＣパッケージ１０が１回の製造サイクルで製造される。
【００２１】
また，ＩＣパッケージ１０では，前述したように均一の厚さのパッド１４がＩＣチップ１１の端子面上に形成されている。そこで，パッド１４の形成（図３（Ｄ））後に，さらに絶縁層および導体層を積層し加工することで，図５に示すように回路を有するＩＣパッケージ１００を形成することもできる。このＩＣパッケージ１００は，最上層であるパターン層１９にＩＣチップ１１の端子１８にアクセスするためのパッドが設けられている。また，他の導体層についても配線パターンが形成されており，積み上げられた絶縁層および導体層にて回路が構成されている。
【００２２】
以上詳細に説明したように本形態のＩＣパッケージ１０の製造方法では，まず，銅箔１３の同一面上に複数のＩＣチップ１１を実装することとしている。そして，ＩＣチップ１１を樹脂１２でモールドすることとしている。次に，銅箔１３をパターニングし，ＩＣチップ１１の端子上にパッド１４を形成することとしている。最後に，モールド樹脂１２をカットすることでＩＣパッケージ１０が製造される。このＩＣパッケージ１０では，従来のＩＣパッケージに必要であったリードの代わりにパッド１４を設けることとしている。そして，銅箔１３をパターニングすることでパッド１４を形成している。パッド１４は元々が１枚の銅箔１３のため，その厚みがほぼ均一であり表面の平坦性が高い。パターニングする時には樹脂１２がモールドされており，ある程度の機械的強度がある。従って，容易に位置合わせを行うことができる。また，ＩＣチップ１１は樹脂１２で覆われているため，パターニング時のエッチング等の影響を受けない。これにより，製造が容易なパッケージ部品およびその製造方法が実現されている。
【００２３】
また，リードが側面から突出していないためＩＣパッケージ１０自体がコンパクトである。そしてそのことを機器側の設計にも反映できる。また，ＩＣチップ１１とパッド１４との間を充填するモールド樹脂１２の厚さは，端子１８の高さと同程度である。このためＩＣパッケージ１０は，ＩＣチップの全体が厚いモールド樹脂で覆われたＩＣパッケージと比較して薄くてコンパクトである。
【００２４】
また，複数のＩＣチップ１１を格子状に並べて実装することとしている。このため，１０数個〜数１００個程度のＩＣパッケージ１０を１回の製造サイクルで製造することができる。従って，パッケージ部品１０の生産性は高い。
【００２５】
また，パッド１４上に絶縁層および導体層を積層することができる。そして，そのようなパッケージ部品の場合には，最上層であるパターン層１９にＩＣチップ１１の端子１８にアクセスするためのパッドを形成することとしている。また，各導体層には配線パターンを形成することとしている。これにより，多彩な回路が内蔵されたパッケージ部品が提供されている。
【００２６】
［第２の形態］
第２の形態のＩＣパッケージ２０は，図６に示すようにＩＣチップ２１と，チップ部品２５と，ＩＣチップ２１およびチップ部品２５の一部を覆うモールド樹脂２２と，ＩＣチップ２１およびチップ部品２５の端子面上に設けられたパターン層２４とを備えている。また，ＩＣチップ２１およびチップ部品２５のそれぞれの端子は，すべてパターン層２４に接合されている。ここでいうチップ部品２５としては，コンデンサ，インダクタ，レジスタ等が該当する。なお，実際には，図２に示すようにＩＣチップ２１等とパターン層２４との間にはＩＣチップ２１等の端子があり，その間はモールド樹脂２２にて充填されている。本形態のＩＣパッケージ２０は，１つのＩＣパッケージの中に複数個の電子部品を有しているところが第１の形態と異なる。
【００２７】
ＩＣパッケージ２０は，図７に示す手順により製造される。まず，ＩＣチップ２１と，チップ部品２５と，銅箔２３とを用意する。そして，ＩＣチップ２１およびチップ部品２５を銅箔２３上に実装する（図７（Ａ））。このとき，すべてのＩＣチップ２１およびチップ部品２５を銅箔２３の同一の面上に実装する。そのため，銅箔２３上には図８に示すように，複数のＩＣチップ２１と複数のチップ部品２５とが混在した状態で実装される。そして，各部品は１製品分（本形態ではＩＣチップ２０）ごとにまとめられている。
【００２８】
次に，実装されたＩＣチップ２１およびチップ部品２５を樹脂２２でモールドする（図７（Ｂ））。次に，銅箔２３をパターニングすることによりパターン層２４を形成する（図７（Ｃ））。このパターン層２４にて，ＩＣチップ２１とチップ部品２５とが電気的に接続された状態を保持する。次に，モールド樹脂２２をカットする。これにより，ＩＣチップ２１およびチップ部品２５を有するＩＣパッケージ２０が製造される。また，複数のＩＣパッケージ２０が１回の製造サイクルで製造される。なお，パターン層２４の形成後に，さらに絶縁層および導体層を積層し加工することで，回路を内蔵するＩＣパッケージを形成することもできる。
【００２９】
以上詳細に説明したように本形態のＩＣパッケージ２０の製造方法では，まず，銅箔２３の同一面上に，ＩＣチップ２１とともに複数のチップ部品２５を実装することとしている。そして，ＩＣチップ２１およびチップ部品２５を樹脂２２でモールドし，その後に銅箔２３をパターニングすることとしている。最後に，モールド樹脂２２を製品ごとにカットすることでＩＣパッケージ２０が製造される。これにより，複数個の電子部品により構成されたＩＣパッケージ２０が製造される。また，１回の製造サイクルで複数個のＩＣパッケージ２０が製造できる。また，製造されたＩＣパッケージ２０はリードを有しておらずコンパクトである。これにより，コンパクトであって，複数個の電子部品を有する機能的なパッケージ部品およびその製造方法が実現されている。
【００３０】
なお，本実施の形態は単なる例示にすぎず，本発明を何ら限定するものではない。したがって本発明は当然に，その要旨を逸脱しない範囲内で種々の改良，変形が可能である。例えば，第２の形態のＩＣパッケージは，ＩＣチップと複数のチップ部品とが混在したものであるが，同種の電子部品を含むものであってもよい。また，ＩＣチップは，ＩＣそのものであってもよいし，既にパッケージ済みのものであってもよい。
【００３１】
【発明の効果】
以上の説明から明らかなように本発明によれば，製造が容易であって，表面の平坦性が高く，コンパクトなパッケージ部品およびその製造方法が提供されている。
【図面の簡単な説明】
【図１】第１の形態に係るＩＣパッケージを示す図である。
【図２】ＩＣパッケージの端子部分を示す拡大図である。
【図３】第１の形態に係るＩＣパッケージの製造工程を示す図である。
【図４】ＩＣパッケージを実装した状態を示す図（第１の形態）である。
【図５】ＩＣチップの下面にパターン層を有するＩＣパッケージを示す断面図である。
【図６】第２の形態に係るＩＣパッケージを示す図である。
【図７】第２の形態に係るＩＣパッケージの製造工程を示す図である。
【図８】ＩＣパッケージを実装した状態を示す図（第２の形態）である。
【図９】従来の形態に係るＩＣパッケージを示す図である。
【図１０】従来の形態に係るＩＣパッケージの製造工程を示す図である。
【符号の説明】
１０，２０　　ＩＣパッケージ
１１，２１　　ＩＣチップ
１２，２２　　樹脂（モールド樹脂）
１３，２３　　銅箔
１４　　　　　パッド
２４　　　　　パターン層
２５　　　　　チップ部品[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a package component in which an electronic component is molded with a resin and a method for manufacturing the same. More particularly, the present invention relates to a compact package component which is easy to manufacture and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, the IC package 30 has a structure in which the entire IC chip 31 is covered with a mold resin 32 as shown in FIG. The IC package 30 has leads 33. One end of the lead 33 contacts the terminal 38 of the IC chip 31 in the mold resin 32, and the other end protrudes outside from the side surface of the IC package 30.
[0003]
Such an IC package 30 is manufactured by a process as shown in FIG. First, an IC chip 31 is prepared (FIG. 10A). Next, the IC chip 31 is arranged on the lead 33 formed for the IC chip 31, and the lead 33 and the terminal 38 of the IC chip 31 are joined (FIG. 10B). Next, the IC chip 31 is molded with the resin 32 (FIG. 10C). Thereby, the entire IC chip 31 is covered with the resin 32. At this time, one end of the lead 33 protrudes outside to enable input / output to / from the IC chip 31. Thereafter, the IC package 30 is manufactured by bending the leads 30 as shown (FIG. 10D).
[0004]
[Problems to be solved by the invention]
However, the conventional technique described above has the following problems. That is, the leads 33 are extremely thin and thin-film components, and have very low mechanical strength. Therefore, it is not easy to correctly align the leads 33 with the positions of the terminals 38 of the IC chip 31. Further, since the leads 33 protrude from the side surface, the size of the IC package 30 as a whole in the width direction is large. The thickness of the resin covering the terminals 38 and the leads 33 is about 600 to 1000 μm, and the size in the thickness direction is large. In addition, this must be considered in the design of the device, and the size of the product in which the IC package 30 is incorporated increases. Further, the IC package 30 molded with resin has irregularities of about 20 to 100 μm and has low flatness. Further, one or at most a few IC packages 30 can be manufactured in one manufacturing cycle. Therefore, productivity is very low.
[0005]
The present invention has been made in order to solve the problems of the above-described conventional technology. That is, an object of the present invention is to provide a compact package component which is easy to manufacture, has high surface flatness, and has a compact manufacturing method.
[0006]
[Means for Solving the Problems]
A package component made for the purpose of solving this problem is a package component in which an electronic component having terminals on one side is packaged, and has a pattern layer bonded to the terminal of the electronic component. The conductive foil is patterned so that the pattern exists directly above the terminal of the component. The electronic component is molded with resin, and the thickness of the resin molded on the terminal surface of the electronic component is the height of the terminal of the electronic component. Less than.
[0007]
The package component of the present invention has a pattern layer in which a conductive foil is patterned just above the terminals of the electronic component. The terminal of the electronic component can be accessed via the pattern layer. That is, the package component of the present invention does not need to be provided with a lead. Therefore, it is more compact in the width direction than the conventional package parts. The thickness of the resin on the terminal surface of the electronic component is equal to or less than the height of the terminal of the electronic component. Therefore, it is more compact in the thickness direction than the conventional package parts. If the pattern layer on the surface is originally formed from one conductive foil, the thickness is uniform. Therefore, the flatness of the surface of the package component is high.
[0008]
Further, the package component of the present invention may include a plurality of electronic components, and each of the electronic components may have a terminal joined to the pattern layer. In this package component, the electronic component and at least one of the other electronic components can be electrically connected via the pattern layer. Accordingly, there has been provided a package component that is modularized by combining the functions of a plurality of electronic components.
[0009]
Also, the package component of the present invention has a stacking layer including an interlayer connection structure in which insulating layers and wiring layers are alternately stacked on a pattern layer, and a terminal of the electronic component is provided on the uppermost layer of the stacking layer. May be provided with a pad for accessing the device. That is, in this package component, various circuits can be built in the stacked layer portion.
[0010]
Further, the method for manufacturing a package component according to the present invention is a method for manufacturing a package component in which an electronic component having terminals on one surface is packaged. A first step of placing the electronic component and the conductor foil together so as to face the foil, and a second step of molding the electronic component joined to the conductor foil in the first step with a resin; After the step, a third step of patterning the conductive foil so that the pattern is present immediately above the terminal of the electronic component.
[0011]
In the method for manufacturing a package component according to the present invention, first, terminals of the electronic component are joined to one surface of the conductive foil. Next, the joined electronic components are molded with resin. Then, the conductor foil is patterned so that the pattern exists directly above the terminals of the electronic component. In this manufacturing method, when the conductor foil is patterned, the resin has a certain mechanical strength because it is molded. Therefore, alignment can be easily performed.
[0012]
In the method for manufacturing a package component according to the present invention, in a first step, electronic components corresponding to a plurality of package parts are joined to a conductor foil, and after a third step, the resin molded in the second step is cut. Alternatively, individual package components may be obtained. Thereby, a plurality of package components can be manufactured in one manufacturing cycle. Therefore, the manufacturing method of the package component of the present invention has high productivity.
[0013]
In the method of manufacturing a package component according to the present invention, a plurality of electronic components may be joined to the conductive foil in the first step to obtain a package component including the plurality of electronic components. As a result, a functional package component containing a plurality of electronic components can be manufactured.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiment, the present invention is applied to an IC package having an IC component and a method of manufacturing the same.
[0015]
[First form]
As shown in FIG. 1, an IC package 10 of the first embodiment includes an IC chip 11, a mold resin 12 covering the IC chip 11, and pads 14 provided on the lower surface of the IC chip 11 in FIG. I have.
[0016]
On the lower surface of the IC chip 11 in FIG. 1, terminals 18 of the IC chip 11 are provided as shown in FIG. 2, and pads 14 are formed immediately above the terminals (in FIG. 1 directly below). . The space between the IC chip 11 and the pad 14 is also filled with the mold resin 12. The distance between the IC chip 11 and the pad 14 is almost equal to the height of the terminal 18 (about 10 to 50 μm). Note that, in the drawings other than FIG. 2, the portion of the terminal 18 and the mold resin between the IC chip 11 and the pad 14 are omitted.
[0017]
The IC package 10 is manufactured according to the procedure shown in FIG. First, an IC chip 11 and a copper foil 13 are prepared. Then, the IC chip 11 is placed so that the surface having the terminals 18 (hereinafter referred to as “terminal surface”) and the copper foil 13 face each other (FIG. 3A). At this time, all the prepared IC chips 11 are placed on the same surface of the copper foil 13. In this embodiment, copper foil is used, but iron or aluminum may be used instead of copper. The thickness of the copper foil 13 is about 9 to 35 μm. Next, the IC chip 11 is mounted on the copper foil 13 (FIG. 3B). The term “mounting” as used herein means that the terminal 18 provided on the terminal surface and the copper foil 13 are joined to be electrically connected. This mounting step may be performed by, for example, metal bonding, pressure welding, ACF / ACP connection, ultrasonic bonding, resin bump bonding, conductive paste bonding, or the like. As shown in FIG. 4, a plurality of IC chips 11 are mounted on the copper foil 13 in a grid pattern. Actually, there is a gap between the IC chip 11 and the copper foil 13 equivalent to the height of the terminal 18 (see FIG. 2).
[0018]
Next, the IC chip 11 is molded with the resin 12 (FIG. 3C). As the resin 12, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as LCP can be used. Actually, the space between the IC chip 11 and the copper foil 13 is also filled with the resin (see FIG. 2).
[0019]
Next, the pads 14 are formed by patterning the copper foil 13 (FIG. 3D). The pad 14 is formed immediately above the terminal 18 of the IC chip 11 (directly below in FIG. 3). Also, since it is originally a copper foil 13, the surface irregularities are about 5 to 10 μm. Therefore, the surface flatness is higher than that of the conventional IC package. Further, since the IC chip 11 is molded with the resin 12, it is not affected by an etching solution or the like at the time of patterning. In addition, physical impact during handling is reduced.
[0020]
Finally, the mold resin 12 is cut (FIG. 3E). In this cut, the mold resin 12 in the gap between the IC chip 11 and another IC chip 11 is cut in the thickness direction (up and down in FIG. 3). Thereby, the IC package 10 in which the IC chip 11 is covered with the mold resin 12 is manufactured. Further, a plurality of IC packages 10 are manufactured in one manufacturing cycle.
[0021]
Further, in the IC package 10, the pads 14 having a uniform thickness are formed on the terminal surfaces of the IC chip 11 as described above. Therefore, after forming the pads 14 (FIG. 3D), by further laminating and processing the insulating layer and the conductor layer, the IC package 100 having a circuit as shown in FIG. 5 can be formed. In the IC package 100, pads for accessing the terminals 18 of the IC chip 11 are provided on the pattern layer 19, which is the uppermost layer. Also, wiring patterns are formed on other conductor layers, and a circuit is formed by the stacked insulating layers and conductor layers.
[0022]
As described in detail above, in the method of manufacturing the IC package 10 of the present embodiment, first, a plurality of IC chips 11 are mounted on the same surface of the copper foil 13. Then, the IC chip 11 is molded with the resin 12. Next, the copper foil 13 is patterned to form pads 14 on the terminals of the IC chip 11. Finally, the IC package 10 is manufactured by cutting the mold resin 12. In this IC package 10, pads 14 are provided instead of the leads required for the conventional IC package. The pads 14 are formed by patterning the copper foil 13. Since the pad 14 is originally a single piece of copper foil 13, the thickness thereof is substantially uniform and the surface flatness is high. At the time of patterning, the resin 12 is molded and has some mechanical strength. Therefore, alignment can be easily performed. Further, since the IC chip 11 is covered with the resin 12, it is not affected by etching or the like at the time of patterning. As a result, a package component that can be easily manufactured and a manufacturing method thereof are realized.
[0023]
Further, since the leads do not protrude from the side, the IC package 10 itself is compact. This can be reflected in the design of the device. The thickness of the mold resin 12 filling the space between the IC chip 11 and the pad 14 is substantially equal to the height of the terminal 18. Therefore, the IC package 10 is thinner and more compact than an IC package in which the entire IC chip is covered with a thick mold resin.
[0024]
Further, a plurality of IC chips 11 are arranged in a grid and mounted. Therefore, about ten to several hundred IC packages 10 can be manufactured in one manufacturing cycle. Therefore, the productivity of the package component 10 is high.
[0025]
Further, an insulating layer and a conductor layer can be stacked on the pad 14. In the case of such a package component, a pad for accessing the terminal 18 of the IC chip 11 is formed on the pattern layer 19 which is the uppermost layer. Also, a wiring pattern is formed on each conductor layer. As a result, package components incorporating various circuits are provided.
[0026]
[Second embodiment]
As shown in FIG. 6, the IC package 20 of the second embodiment includes an IC chip 21, a chip component 25, a mold resin 22 which covers a part of the IC chip 21 and the chip component 25, an IC chip 21 and a chip component 25. And a pattern layer 24 provided on the terminal surface of the above. All terminals of the IC chip 21 and the chip component 25 are all joined to the pattern layer 24. As the chip component 25 here, a capacitor, an inductor, a resistor and the like correspond. Actually, as shown in FIG. 2, there are terminals of the IC chip 21 and the like between the IC chip 21 and the pattern layer 24, and the space between them is filled with the mold resin 22. The IC package 20 of the present embodiment differs from the first embodiment in that a plurality of electronic components are provided in one IC package.
[0027]
The IC package 20 is manufactured according to the procedure shown in FIG. First, an IC chip 21, a chip component 25, and a copper foil 23 are prepared. Then, the IC chip 21 and the chip component 25 are mounted on the copper foil 23 (FIG. 7A). At this time, all the IC chips 21 and the chip components 25 are mounted on the same surface of the copper foil 23. Therefore, as shown in FIG. 8, a plurality of IC chips 21 and a plurality of chip components 25 are mounted on the copper foil 23 in a mixed state. The components are grouped for each product (IC chip 20 in this embodiment).
[0028]
Next, the mounted IC chip 21 and chip component 25 are molded with the resin 22 (FIG. 7B). Next, a pattern layer 24 is formed by patterning the copper foil 23 (FIG. 7C). In this pattern layer 24, the state where the IC chip 21 and the chip component 25 are electrically connected is maintained. Next, the mold resin 22 is cut. Thus, the IC package 20 having the IC chip 21 and the chip component 25 is manufactured. Also, a plurality of IC packages 20 are manufactured in one manufacturing cycle. Note that, after the formation of the pattern layer 24, an insulating layer and a conductor layer are further laminated and processed to form an IC package having a built-in circuit.
[0029]
As described above in detail, in the method of manufacturing the IC package 20 according to the present embodiment, first, a plurality of chip components 25 are mounted together with the IC chip 21 on the same surface of the copper foil 23. Then, the IC chip 21 and the chip component 25 are molded with the resin 22, and thereafter, the copper foil 23 is patterned. Finally, the IC package 20 is manufactured by cutting the mold resin 22 for each product. Thus, an IC package 20 including a plurality of electronic components is manufactured. Also, a plurality of IC packages 20 can be manufactured in one manufacturing cycle. The manufactured IC package 20 has no leads and is compact. As a result, a compact and functional package component having a plurality of electronic components and a method of manufacturing the same are realized.
[0030]
Note that the present embodiment is merely an example, and does not limit the present invention in any way. Therefore, naturally, the present invention can be variously modified and modified without departing from the gist thereof. For example, the IC package of the second embodiment is a package in which an IC chip and a plurality of chip components are mixed, but may include electronic components of the same type. Further, the IC chip may be the IC itself, or may be an already packaged one.
[0031]
【The invention's effect】
As is apparent from the above description, according to the present invention, there is provided a compact package component which is easy to manufacture, has high surface flatness, and a method of manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a diagram showing an IC package according to a first embodiment.
FIG. 2 is an enlarged view showing a terminal portion of an IC package.
FIG. 3 is a diagram showing a manufacturing process of the IC package according to the first embodiment.
FIG. 4 is a diagram showing a state in which an IC package is mounted (first embodiment);
FIG. 5 is a sectional view showing an IC package having a pattern layer on a lower surface of an IC chip.
FIG. 6 is a diagram showing an IC package according to a second embodiment.
FIG. 7 is a diagram showing a manufacturing process of the IC package according to the second embodiment.
FIG. 8 is a diagram (second embodiment) showing a state in which an IC package is mounted.
FIG. 9 is a view showing an IC package according to a conventional mode.
FIG. 10 is a diagram showing a manufacturing process of an IC package according to a conventional mode.
[Explanation of symbols]
10,20 IC package 11,21 IC chip 12,22 Resin (mold resin)
13, 23 Copper foil 14 Pad 24 Pattern layer 25 Chip component

Claims (6)

一面に端子を有する電子部品をパッケージしてなるパッケージ部品において，
前記電子部品の端子に接合されたパターン層を有し，
前記パターン層は，前記電子部品の端子の直上にパターンが存在するように導体箔をパターニングしたものであり，
前記電子部品は樹脂でモールドされ，
前記電子部品の端子面上をモールドする樹脂の厚さは，前記電子部品の端子の高さ以下であることを特徴とするパッケージ部品。In a package component that is a package of electronic components that have terminals on one side,
A pattern layer joined to a terminal of the electronic component;
The pattern layer is formed by patterning a conductive foil so that a pattern exists immediately above a terminal of the electronic component;
The electronic component is molded with resin,
A package component, wherein a thickness of a resin for molding a terminal surface of the electronic component is not more than a height of a terminal of the electronic component. 請求項１に記載するパッケージ部品において，
複数の電子部品を含み，各電子部品ともその端子が前記パターン層に接合されていることを特徴とするパッケージ部品。The package component according to claim 1,
A package component comprising a plurality of electronic components, and each electronic component has its terminal bonded to the pattern layer. 請求項１に記載するパッケージ部品において，
前記パターン層上に，絶縁層と配線層とを交互に積層してなるとともに層間接続構造を含む積み上げ層を有し，
前記積み上げ層の最上層に，前記電子部品の端子にアクセスするパッドを有することを特徴とするパッケージ部品。The package component according to claim 1,
An insulating layer and a wiring layer are alternately laminated on the pattern layer, and a stacked layer including an interlayer connection structure is provided.
A package component having a pad for accessing a terminal of the electronic component on an uppermost layer of the stacking layer. 一面に端子を有する電子部品をパッケージしてなるパッケージ部品の製造方法において，
導体箔の一方の面上に電子部品を，その端子面が導体箔と向き合うように載置し，電子部品の端子と導体箔とを接合する第１工程と，
前記第１工程にて前記導体箔に接合された電子部品を樹脂でモールドする第２工程と，
前記第２工程後に，前記導体箔を，電子部品の端子の直上にパターンが存在するようにパターニングする第３工程とを含むことを特徴とするパッケージ部品の製造方法。In a method of manufacturing a package component in which an electronic component having terminals on one side is packaged,
A first step of placing an electronic component on one surface of the conductive foil with its terminal surface facing the conductive foil and joining the terminal of the electronic component to the conductive foil;
A second step of molding the electronic component bonded to the conductive foil in the first step with a resin;
After the second step, a third step of patterning the conductive foil so that a pattern is present immediately above the terminal of the electronic component. 請求項４に記載するパッケージ部品の製造方法において，
前記第１工程にて，複数個のパッケージ部品に相当する電子部品を導体箔に接合し，
前記第３工程後に，前記第２工程にてモールドした樹脂をカットして個別のパッケージ部品を得ることを特徴とするパッケージ部品の製造方法。The method for manufacturing a package component according to claim 4,
In the first step, electronic components corresponding to a plurality of package components are joined to a conductive foil,
After the third step, a method for manufacturing a package component, wherein the resin molded in the second step is cut to obtain individual package components. 請求項４に記載するパッケージ部品の製造方法において，
前記第１工程にて複数個の電子部品を導体箔に接合し，
複数個の電子部品を含むパッケージ部品を得ることを特徴とするパッケージ部品の製造方法。The method for manufacturing a package component according to claim 4,
In the first step, a plurality of electronic components are joined to a conductive foil,
A method for manufacturing a package component, comprising obtaining a package component including a plurality of electronic components.
JP2002248284A 2002-08-28 2002-08-28 Package component and its manufacturing method Pending JP2004087895A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101507A (en) * 2003-08-21 2005-04-14 Seiko Epson Corp Method of manufacturing electronic component package and method of manufacturing electrooptic device
CN103745958A (en) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 Packaging structure
CN103915355A (en) * 2013-12-05 2014-07-09 南通富士通微电子股份有限公司 Package structure forming method
JPWO2016039387A1 (en) * 2014-09-10 2017-04-27 株式会社東芝 Winding type electrode group, electrode group and non-aqueous electrolyte battery

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221422A (en) * 1994-01-31 1995-08-18 Mitsui Mining & Smelting Co Ltd Printed circuit board and production thereof
JPH11345840A (en) * 1998-06-01 1999-12-14 Mitsui Mining & Smelting Co Ltd Film carrier tape for mounting electronic parts
JP2001250887A (en) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd Manufacturing method of circuit device
JP2001332654A (en) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd Module provided with built-in electric element and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221422A (en) * 1994-01-31 1995-08-18 Mitsui Mining & Smelting Co Ltd Printed circuit board and production thereof
JPH11345840A (en) * 1998-06-01 1999-12-14 Mitsui Mining & Smelting Co Ltd Film carrier tape for mounting electronic parts
JP2001250887A (en) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd Manufacturing method of circuit device
JP2001332654A (en) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd Module provided with built-in electric element and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101507A (en) * 2003-08-21 2005-04-14 Seiko Epson Corp Method of manufacturing electronic component package and method of manufacturing electrooptic device
CN103745958A (en) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 Packaging structure
CN103915355A (en) * 2013-12-05 2014-07-09 南通富士通微电子股份有限公司 Package structure forming method
US9397070B2 (en) 2013-12-05 2016-07-19 Nantong Fujitsu Microelectronics Co., Ltd. Method for forming package structure
US9485868B2 (en) 2013-12-05 2016-11-01 Nantong Fujitsu Microelectronics Co., Ltd. Package structure
JPWO2016039387A1 (en) * 2014-09-10 2017-04-27 株式会社東芝 Winding type electrode group, electrode group and non-aqueous electrolyte battery
US10505233B2 (en) 2014-09-10 2019-12-10 Kabushiki Kaisha Toshiba Wound electrode group, electrode group, and nonaqueous electrolyte battery

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