JP2004080928A

JP2004080928A - Gate drive circuit for voltage drive type semiconductor device

Info

Publication number: JP2004080928A
Application number: JP2002239055A
Authority: JP
Inventors: Koji Maruyama; 丸山　宏二; Kiyoaki Sasagawa; 笹川　清明
Original assignee: Fuji Electric Holdings Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-08-20
Filing date: 2002-08-20
Publication date: 2004-03-11
Anticipated expiration: 2022-08-20
Also published as: JP4099703B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate drive circuit that suppresses application of an overvoltage caused by the imbalance of a shared voltage, arising from the difference in the turn-off timing of each device or the like, when constituting an arm of a power converter by series-connecting the arm to a voltage drive type semiconductor device, prevents the element from causing device breakage, and prevents accidents caused by short circuit breakage from expanding to a sound device. <P>SOLUTION: In the gate drive circuit of the voltage drive type semiconductor device, a monitoring period is set for monitoring the on/off-signal, which is indicated to the gate drive circuit from the outside, from the time the signal is turned to off-signal. When an overvoltage determining circuit OV determines overvoltage during the monitoring period, an IGBT is on-operated again in an active region, by controlling the VGE of the IGBT to a voltage near a threshold by using the gate voltage control circuit VG. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は、各アームに電圧駆動型半導体素子を直列接続してなる電力変換装置における電圧駆動型半導体素子のゲート駆動回路に関する。
【０００２】
【従来の技術】
図４は、電圧変換装置で高電圧化を図るために、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）を各アームに直列接続した場合の従来例で、ＩＧＢＴを直列接続したインバータ１相分の回路を示す。
【０００３】
図示のように、この回路はＩＧＢＴＱ１，Ｑ２（上アーム）とＱ３，Ｑ４（下アーム）、電圧Ｅｄの直流電源、検出抵抗Ｒｂ１〜Ｒｂ４などから構成される。
【０００４】
また、ＧＤＵ１〜ＧＤＵ４はＱ１〜Ｑ４のゲート駆動回路で、具体的には例えば図５に示すように、ＩＧＢＴをオン，オフさせるための駆動回路としてのトランジスタＴＲ１，ＴＲ２、ゲート抵抗Ｒｇ（ｏｎ），Ｒｇ（ｏｆｆ）およびゲート電圧制御回路ＶＧ、過電圧判別回路ＯＶなどから構成される。
【０００５】
一般的に、図６の動作波形図に示すようにＱ１がターンオフ動作を開始してから、時間Δｔだけ遅れてＱ２がターンオフ動作を開始した場合、すなわち、ＩＧＢＴを直列接続して運転するときに、例えば図６に示すように、ゲート電圧ＶＧＥのタイミングばらつき等により、ＩＧＢＴのターンオフタイミングに違いが生じると、各ＩＧＢＴの電圧分担にアンバランスが発生する。これは、Ｑ１が早くオフしてしまうと、Ｑ２はオンしているため、Ｑ１だけに電圧が印加されてしまうためである。
【０００６】
図７は、上述の電圧分担のアンバランスを解消することができる図４，図５に示した回路における動作波形図である。
【０００７】
いま、Ｑ１が先にターンオフすると、Ｑ１のコレクタ−エミッタ間電圧ＶＣＥが上昇を始め、検出抵抗Ｒｂ１によって検出された電圧が過電圧レベルに達すると、過電圧判別回路ＯＶにてＱ１のコレクタ−エミッタ間電圧ＶＣＥが過電圧と判断される。これにより、ゲート電圧制御回路ＶＧが動作し、ゲート駆動回路ＧＤＵ１の出力すなわちゲート−エミッタ間電圧ＶＧＥをＩＧＢＴのしきい値付近の電圧に制御することで、Ｑ１を活性領域で再オンさせる。Ｑ１が再オンするとＱ１のコレクタ−エミッタ間電圧ＶＣＥが下降し、Ｑ１に過電圧が印加されるのを防止することができる。なお、外部から指令されるオン・オフ信号に基づくＩＧＢＴの通常のオン動作の際には、ゲート電圧制御回路ＶＧからのゲート電圧指令値により、ゲート駆動回路ＧＤＵ１の出力すなわちゲート−エミッタ間電圧ＶＧＥを、例えば図５に示すように＋１５ボルト（Ｐ１５）付近の電圧にすることで、Ｑ１を飽和領域でオンさせる。
【０００８】
【発明が解決しようとする課題】
ＩＧＢＴを直列接続して用いる場合、上述の如くゲート−エミッタ間電圧ＶＧＥを制御することにより、ターンオフタイミングがずれたときの電圧分担のアンバランスによる過電圧印加やそれに伴う素子破壊を防ぐことが可能である。
【０００９】
しかしながら、直列接続された各ＩＧＢＴのうち、いずれか１個のＩＧＢＴが何らかの要因で素子破壊（短絡破壊）を起こした場合には、他の健全なＩＧＢＴにおいて、上述の如くゲート−エミッタ間電圧ＶＧＥの制御により再オン動作が継続して行われるという問題がある。
【００１０】
図８は、図４に示した従来の回路におけるＱ１〜Ｑ４のうち、Ｑ１が短絡破壊を起こしたときの動作波形例を示している。
【００１１】
Ｑ１，Ｑ２のターンオフ時、Ｑ１に短絡破壊が発生すると、直流電源の電圧Ｅｄが全てＱ２に印加される。これにより、過電圧判別回路ＯＶにてＱ２のコレクタ−エミッタ間電圧ＶＣＥが過電圧と判断され、ゲート電圧制御回路ＶＧによりゲート−エミッタ間電圧ＶＧＥをＩＧＢＴのしきい値付近の電圧に制御することで、Ｑ１を活性領域で再オンさせる。この再オン動作は継続して行われるため、Ｑ２に過大な損失責務が発生し、Ｑ２も素子破壊する可能性がある。また、Ｑ２の再オン動作継続中に、下アームのＱ３，Ｑ４がオンになった時点でアーム短絡に陥るなど、Ｑ１の素子破壊に伴う事故が拡大する恐れがある。この問題点は、素子破壊時の保護を高速に行うことが困難であるために生ずる問題点である。
【００１２】
従って、この発明の課題は上述の問題点を解決し、この種の電圧駆動型半導体素子の保護と素子破壊に伴う事故の拡大を防止する該素子のゲート駆動回路を提供することにある。
【００１３】
【課題を解決するための手段】
このような課題を解決するために、この発明では、各アームに電圧駆動型半導体素子を直列接続してなる電力変換装置において、各電圧駆動型半導体を飽和領域または活性領域でオンさせる、若しくはオフさせるゲート電圧指令値を生成するゲート電圧制御回路と、当該電圧駆動型半導体素子に前記それぞれのゲート電圧指令値に基づくゲート電圧を供給する駆動回路と、この電圧駆動型半導体素子に印加される電圧を検出し過電圧か否かを判断する過電圧判別回路と、予め定める監視期間を設定する期間設定回路とを設け、通常は外部から指令されるオン・オフ信号がオン信号のときには当該電圧駆動型半導体素子を飽和領域でオン動作をさせ、前記オン・オフ信号がオン信号からオフ信号に替ったときから前記監視期間中にこの電圧駆動型半導体素子に過電圧が印加されたときには該電圧駆動型半導体素子を活性領域で再オン動作をさせることで、直列接続されたいずれかの電圧駆動型半導体素子に素子破壊（短絡破壊）が発生した場合、他の健全な電圧駆動型半導体素子の再オン動作の継続およびそれに伴う素子破壊を防止するようにしている。
【００１４】
【発明の実施の形態】
図１は、この発明の実施の形態を示す電力変換装置の回路構成図であり、図４に示した従来例構成と同一機能を有するものには同一符号を付している。
【００１５】
すなわち、図１の回路構成が図４の回路構成と異なる点はゲート駆動回路ＧＤＵ１〜ＧＤＵ４に代えて、この発明のゲート駆動回路ＧＤＵ１ａ〜ＧＤＵ４ａを備えていることである。
【００１６】
図２は、図１に示したゲート駆動回路ＧＤＵ１ａ〜ＧＤＵ４ａの詳細回路構成図であり、ＧＤＵ１〜ＧＤＵ４と同一機能であるＩＧＢＴをオン，オフさせるための駆動回路としてのトランジスタＴＲ１，ＴＲ２、ゲート抵抗Ｒｇ（ｏｎ），Ｒｇ（ｏｆｆ）およびゲート電圧制御回路ＶＧ、過電圧判別回路ＯＶの他に、タイマ，アンド素子から構成される期間設定回路が付加されている。
【００１７】
図３は、図１，図２に示した回路における動作波形図である。
【００１８】
先ず、Ｑ１，Ｑ２に外部から指令されるオン・オフ信号がオン信号からオフ信号に変化すると、前記タイマ出力は論理「Ｈ」レベルとなり、この論理「Ｈ」レベルは所定の監視期間ΔＴ_０の間継続する。ここで、先述の図８に示した動作波形図と同様に、Ｑ１に短絡破壊が発生すると、直流電源の電圧ＥｄがＱ２に印加され、これにより、検出抵抗Ｒｂ２を介した過電圧判別回路ＯＶにてＱ２のコレクタ−エミッタ間電圧ＶＣＥが過電圧と判断され、ゲート電圧制御回路ＶＧによりゲート−エミッタ間電圧ＶＧＥをＩＧＢＴのしきい値付近の電圧に制御することで、Ｑ１を活性領域で再オンさせる。しかし、前記タイマ出力は所定の監視期間（ΔＴ_０）を経過後に、論理「Ｌ」レベルとなり、前記アンド素子出力も論理「Ｌ」レベルとなって、Ｑ２の再オン動作を停止することができる。この後、全てのＩＧＢＴをオフする保護動作を行えばよく、高速保護動作が困難な期間の過電圧判別回路ＯＶおよびゲート電圧制御回路ＶＧによる再オン継続動作および下アームＩＧＢＴＱ３，Ｑ４のオンによるアーム短絡等の事故の拡大を防止することができる。
【００１９】
なお、図２に示したこの発明のゲート駆動回路は、通常動作時においても過電圧判別回路ＯＶおよびゲート電圧制御回路ＶＧによる再オン動作期間を限定するものであるが、前記タイマの監視期間（ΔＴ_０）を、例えば１０マイクロ秒程度に設定することにより、先述のターンオフタイミング差による各ＩＧＢＴの電圧分担アンバランスに対して、問題なく過電圧の抑制を行うことが可能である。
【００２０】
また、各アームのＩＧＢＴの直列数が３以上でも、１個のＩＧＢＴの短絡破壊により、他の健全なＩＧＢＴが継続して再オン動作をする可能性があるが、この発明のゲート駆動回路では、前記期間設定回路により再オン継続動作およびアーム短絡を防止することができる。
【００２１】
【発明の効果】
この発明によれば、各アームに電圧駆動型半導体素子が直列接続される電力変換装置で、これらの電圧駆動型半導体素子の過電圧発生時には該素子のゲート電圧をしきい値付近の活性領域の電圧にすることにより、この過電圧抑制を行い、且つ、素子故障時にはこれに伴う事故の拡大を防止することができる。
【図面の簡単な説明】
【図１】この発明の実施の形態を示す電力変換装置の回路構成図
【図２】図１の部分詳細回路構成図
【図３】図１，図２の回路の動作を説明する波形図
【図４】従来例を示す電力変換装置の回路構成図
【図５】図４の部分詳細回路構成図
【図６】図４，図５の回路の動作を説明する波形図
【図７】図４，図５の回路の動作を説明する波形図
【図８】図４，図５の回路の動作を説明する波形図
【符号の説明】
Ｑ１〜Ｑ４…ＩＧＢＴ、Ｒｂ１〜Ｒｂ４…検出抵抗、Ｅｄ…直流電源の電圧、ＧＤＵ１〜ＧＤＵ４…ゲート駆動回路、ＧＤＵ１ａ〜ＧＤＵ４ａ…ゲート駆動回路、ＯＶ…過電圧判別回路、ＶＧ…ゲート電圧制御回路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a gate drive circuit for a voltage-driven semiconductor device in a power converter in which a voltage-driven semiconductor device is connected to each arm in series.
[0002]
[Prior art]
FIG. 4 shows a conventional example in which an IGBT (insulated gate bipolar transistor) is connected in series to each arm in order to increase the voltage in the voltage converter, and shows a circuit for one phase of an inverter in which IGBTs are connected in series.
[0003]
As shown, this circuit includes IGBTs Q1, Q2 (upper arm) and Q3, Q4 (lower arm), a DC power supply of voltage Ed, detection resistors Rb1 to Rb4, and the like.
[0004]
GDU1 to GDU4 are gate drive circuits for Q1 to Q4. Specifically, for example, as shown in FIG. 5, transistors TR1 and TR2 as drive circuits for turning on and off the IGBT, and a gate resistor Rg (on) , Rg (off), a gate voltage control circuit VG, an overvoltage determination circuit OV, and the like.
[0005]
Generally, as shown in the operation waveform diagram of FIG. 6, when Q2 starts turn-off operation with a delay of time Δt after Q1 starts turn-off operation, ie, when IGBTs are connected in series and operated. For example, as shown in FIG. 6, when a difference in the turn-off timing of the IGBT occurs due to a timing variation of the gate voltage VGE or the like, an imbalance occurs in the voltage sharing of each IGBT. This is because if Q1 is turned off earlier, Q2 is turned on, so that a voltage is applied only to Q1.
[0006]
FIG. 7 is an operation waveform diagram in the circuits shown in FIGS. 4 and 5 which can eliminate the above-described imbalance in voltage sharing.
[0007]
Now, when Q1 turns off first, the collector-emitter voltage VCE of Q1 starts to rise, and when the voltage detected by the detection resistor Rb1 reaches the overvoltage level, the collector-emitter voltage of Q1 is detected by the overvoltage determination circuit OV. VCE is determined to be overvoltage. As a result, the gate voltage control circuit VG operates to control the output of the gate drive circuit GDU1, that is, the gate-emitter voltage VGE to a voltage near the threshold value of the IGBT, thereby turning on Q1 again in the active region. When Q1 is turned on again, the collector-emitter voltage VCE of Q1 decreases, and it is possible to prevent an overvoltage from being applied to Q1. Note that, during a normal ON operation of the IGBT based on an ON / OFF signal commanded from the outside, the output of the gate drive circuit GDU1, that is, the gate-emitter voltage VGE is supplied by the gate voltage command value from the gate voltage control circuit VG. To a voltage near +15 volts (P15) as shown in FIG. 5, for example, to turn on Q1 in the saturation region.
[0008]
[Problems to be solved by the invention]
When the IGBTs are connected in series, by controlling the gate-emitter voltage VGE as described above, it is possible to prevent overvoltage application due to imbalance in voltage sharing when the turn-off timing is shifted and element destruction accompanying the overvoltage. is there.
[0009]
However, if any one of the IGBTs connected in series causes element destruction (short-circuit destruction) due to some cause, the gate-emitter voltage VGE in the other healthy IGBTs as described above. There is a problem that the re-ON operation is continuously performed by the control of.
[0010]
FIG. 8 shows an example of an operation waveform when Q1 of Q1 to Q4 in the conventional circuit shown in FIG. 4 causes short-circuit breakdown.
[0011]
When short-circuit breakdown occurs in Q1 when Q1 and Q2 are turned off, the voltage Ed of the DC power supply is all applied to Q2. As a result, the collector-emitter voltage VCE of Q2 is determined as an overvoltage by the overvoltage determination circuit OV, and the gate-emitter voltage VGE is controlled to a voltage near the threshold of the IGBT by the gate voltage control circuit VG. Q1 is turned on again in the active region. Since this re-ON operation is performed continuously, an excessive loss obligation occurs in Q2, and there is a possibility that Q2 may be destroyed. Further, while the restart operation of Q2 is continued, the short circuit of the arm occurs when Q3 and Q4 of the lower arm are turned on. This problem arises because it is difficult to perform high-speed protection when the element is destroyed.
[0012]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a gate drive circuit for such a voltage-driven semiconductor device, which protects the device and prevents an increase in accidents due to device destruction.
[0013]
[Means for Solving the Problems]
In order to solve such a problem, according to the present invention, in a power converter in which a voltage-driven semiconductor element is connected in series to each arm, each voltage-driven semiconductor is turned on or off in a saturation region or an active region. A gate voltage control circuit that generates a gate voltage command value to be driven, a drive circuit that supplies a gate voltage based on the respective gate voltage command values to the voltage driven semiconductor element, and a voltage applied to the voltage driven semiconductor element. And a period setting circuit for setting a predetermined monitoring period. Usually, when an on / off signal commanded from the outside is an on signal, the voltage-driven semiconductor is provided. The element is turned on in a saturation region, and the voltage drive is performed during the monitoring period from when the on / off signal is changed from an on signal to an off signal. When an overvoltage is applied to a semiconductor element, the voltage-driven semiconductor element is turned on again in the active region, thereby causing an element destruction (short-circuit destruction) in one of the series-connected voltage-driven semiconductor elements. Further, the continuation of the re-ON operation of another sound voltage-driven semiconductor device and the accompanying destruction of the device are prevented.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit configuration diagram of a power conversion device according to an embodiment of the present invention. Components having the same functions as those of the conventional configuration shown in FIG. 4 are denoted by the same reference numerals.
[0015]
That is, the circuit configuration of FIG. 1 is different from the circuit configuration of FIG. 4 in that gate drive circuits GDU1a to GDU4a of the present invention are provided instead of the gate drive circuits GDU1 to GDU4.
[0016]
FIG. 2 is a detailed circuit configuration diagram of the gate drive circuits GDU1a to GDU4a shown in FIG. 1, and includes transistors TR1 and TR2 as drive circuits for turning on and off an IGBT having the same function as the GDU1 to GDU4, and a gate resistor. In addition to Rg (on), Rg (off), the gate voltage control circuit VG, and the overvoltage determination circuit OV, a period setting circuit including a timer and an AND element is added.
[0017]
FIG. 3 is an operation waveform diagram in the circuits shown in FIGS.
[0018]
First, on-off signal is commanded from the outside to the Q1, Q2 is the change from the ON signal to the OFF signal, the timer output is a logic "H" level, the logic "H" level of the predetermined monitoring period [Delta] T ₀ Continue for a while. Here, similarly to the operation waveform diagram shown in FIG. 8 described above, when a short-circuit breakdown occurs in Q1, the voltage Ed of the DC power supply is applied to Q2, whereby the overvoltage determination circuit OV via the detection resistor Rb2 is applied. As a result, the collector-emitter voltage VCE of Q2 is determined to be an overvoltage, and the gate-emitter voltage VGE is controlled to a voltage near the threshold of the IGBT by the gate voltage control circuit VG, thereby turning on Q1 again in the active region. . However, after a predetermined monitoring period (ΔT ₀ ) has elapsed, the timer output goes to the logic “L” level, and the AND element output also goes to the logic “L” level, so that the restart operation of Q2 can be stopped. . Thereafter, a protection operation for turning off all the IGBTs may be performed, and a re-continuation operation by the overvoltage determination circuit OV and the gate voltage control circuit VG during a period during which the high-speed protection operation is difficult, and an arm short circuit due to the ON of the lower arms IGBTs Q3 and Q4. It is possible to prevent the accident from spreading.
[0019]
The gate drive circuit of the present invention shown in FIG. 2 limits the restart operation period by the overvoltage determination circuit OV and the gate voltage control circuit VG even during the normal operation, but the monitoring period (ΔT By setting ₀ ) to, for example, about 10 microseconds, overvoltage can be suppressed without any problem with respect to the voltage sharing imbalance of each IGBT due to the aforementioned turn-off timing difference.
[0020]
Further, even if the number of series IGBTs in each arm is 3 or more, there is a possibility that another healthy IGBT will continue to turn on again due to short-circuit breakdown of one IGBT. However, in the gate drive circuit of the present invention, The period setting circuit can prevent the re-continuation operation and the arm short circuit.
[0021]
【The invention's effect】
According to the present invention, in a power converter in which voltage-driven semiconductor elements are connected in series to each arm, when an overvoltage occurs in these voltage-driven semiconductor elements, the gate voltage of the elements is changed to a voltage in an active region near a threshold. By doing so, it is possible to suppress the overvoltage and prevent the occurrence of an accident accompanying the failure in the event of an element failure.
[Brief description of the drawings]
1 is a circuit configuration diagram of a power converter showing an embodiment of the present invention; FIG. 2 is a partial detailed circuit configuration diagram of FIG. 1; FIG. 3 is a waveform diagram illustrating the operation of the circuits of FIGS. FIG. 4 is a circuit configuration diagram of a power converter showing a conventional example. FIG. 5 is a partial detailed circuit configuration diagram of FIG. 4. FIG. 6 is a waveform diagram illustrating the operation of the circuits of FIG. 4 and FIG. 8 is a waveform diagram for explaining the operation of the circuit of FIG. 5, and FIG. 8 is a waveform diagram for explaining the operation of the circuit of FIGS.
Q1 to Q4: IGBT, Rb1 to Rb4: detection resistor, Ed: DC power supply voltage, GDU1 to GDU4: gate drive circuit, GDU1a to GDU4a: gate drive circuit, OV: overvoltage discrimination circuit, VG: gate voltage control circuit.

Claims

In a power conversion device having a voltage-driven semiconductor element connected in series to each arm,
A gate voltage control circuit that generates a gate voltage command value for turning on or off each voltage-driven semiconductor in a saturation region or an active region, and applying a gate voltage based on the respective gate voltage command values to the voltage-driven semiconductor device. A drive circuit to be supplied, an overvoltage determination circuit that detects a voltage applied to the voltage-driven semiconductor element and determines whether the voltage is an overvoltage, and a period setting circuit that sets a predetermined monitoring period,
Normally, when the on / off signal commanded from the outside is an on signal, the voltage-driven semiconductor device is turned on in a saturation region, and the monitoring is performed when the on / off signal is changed from an on signal to an off signal. A gate drive circuit for a voltage-driven semiconductor device, wherein when an overvoltage is applied to the voltage-driven semiconductor device during a period, the voltage-driven semiconductor device is turned on again in an active region.