JP2004079685A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2004079685A
JP2004079685A JP2002236036A JP2002236036A JP2004079685A JP 2004079685 A JP2004079685 A JP 2004079685A JP 2002236036 A JP2002236036 A JP 2002236036A JP 2002236036 A JP2002236036 A JP 2002236036A JP 2004079685 A JP2004079685 A JP 2004079685A
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metal
chip
wafer
child
chips
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JP4009505B2 (en
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Kazutaka Shibata
柴田　和孝
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2002236036A priority Critical patent/JP4009505B2/en
Priority to US10/629,904 priority patent/US6835593B2/en
Priority to CNB031525091A priority patent/CN100356530C/en
Publication of JP2004079685A publication Critical patent/JP2004079685A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is high in productivity and capable of joining a plurality of semiconductor chips together as the semiconductor chips are made to get less out of position. <P>SOLUTION: First, in Figure (a), a wafer W is placed on a mounting pad 11 as its active surface Wa is kept facing upward. Metal projections 4 each having a tin layer on their tips are formed on the active surface Wa of the wafer W, and a flux 22 is applied on each tip of the metal projections 4. The wafer W contains a plurality of unit regions U corresponding to master chips. In succession, a slave chip 2 equipped with metal projections 5 formed on its active surface 2a is placed on the wafer W by a collet as its active surface 2a is kept facing downward. By this setup, in Figure (b), the metal projections 4 and 5 are temporarily fixed together through the flux 22. The same as mentioned above, the slave chips 2 and 3 are temporarily fixed in the whole unit regions U on the wafer W, and then the wafer W and the slave chips 2 and 3 are heated for a prescribed time at temperatures higher than the melting point of tin. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップの上に別の半導体チップを接合したチップ・オン・チップ構造を有する半導体装置の製造方法に関する。
【０００２】
【従来の技術】
いわゆるマルチ・チップ型半導体装置の一形態として、複数個の半導体チップを重ね合わせたチップ・オン・チップ構造がある。チップ・オン・チップ構造の半導体装置では、外部接続される親チップの表面に、この親チップよりも小さな子チップが接合されている。１つの親チップの表面に複数個の子チップが接合されたものもある。
【０００３】
親チップおよび子チップは、それぞれ機能素子や配線が形成された活性面に複数の金属突起（バンプ）を備えている。これらの金属突起は、主として金（Ａｕ）などの高融点金属からなり、親チップの金属突起および子チップの金属突起の双方または一方には、先端に錫（Ｓｎ）などの低融点金属からなる層が形成されている。
チップ・オン・チップ構造の半導体装置の製造工程において、親チップの活性面と子チップの活性面とが対向させられ、親チップの金属突起と子チップの金属突起とが押しつけられるように、親チップおよび子チップに荷重がかけられる。この状態で、親チップおよび子チップが低融点金属の融点（固相線温度）以上の温度に加熱される。これにより、金属突起の先端に形成された低融点金属からなる層は溶融する。
【０００４】
その後、親チップおよび子チップの温度が、低融点金属の融点以下に下げられる。これにより、低融点金属は固化して親チップの金属突起と子チップの金属突起とが、低融点金属を介して電気的および機械的に接合される。親チップの金属突起や子チップの金属突起の表面に酸化膜が形成されている場合でも、親チップの金属突起と子チップの金属突起とが押しつけられることにより、酸化膜が破られて、第１および第２の金属突起は低融点金属により良好に接合される。
【０００５】
上記の接合は、親チップを切り出す前のウエハの状態で行われることもある。この場合、半導体ウエハと子チップとの接合後、半導体ウエハが切断されて、チップ・オン・チップ構造を有する半導体チップの個片にされる。
【０００６】
【発明が解決しようとする課題】
ところが、半導体ウエハは多数（たとえば、数千個）の親チップに相当する領域を有しており、すべての親チップに相当する領域に、子チップを同時に押しつけて加熱することはできない。このため、吸着コレットにより、半導体ウエハ上の所定の位置に子チップを運び、この子チップに荷重をかけながら昇温および降温するという工程を子チップの数だけ繰り返さねばならず、生産性が悪かった。
【０００７】
また、親チップと子チップとの接合を行う際、親チップの金属突起と子チップの金属突起とを正確に位置合わせしなければならないが、昇温および降温に伴う熱履歴により、接合に用いる装置に狂いが生じるため、位置合わせの精度を高くすることができなかった。
さらに、親チップと子チップとの接合時に、たとえば、子チップが帯電している場合、親チップの金属突起と子チップの金属突起との接触時に、親チップに形成された機能素子が、子チップからの放電により静電破壊される。このような事態を回避するため、親チップには、金属突起に接続された保護ダイオードが設けられている。しかし、保護ダイオードは本来不要なものであり、保護ダイオードを設けると他の機能素子を形成する領域が少なくなる。
【０００８】
そこで、この発明の目的は、生産性が高い半導体装置の製造方法を提供することである。
この発明の他の目的は、位置ずれを少なくして複数の半導体基板を接合できる半導体装置の製造方法を提供することである。
この発明のさらに他の目的は、複数の半導体基板を接合する際の静電破壊を防止するための保護ダイオードを半導体基板に設ける必要がない半導体装置の製造方法を提供することである。
【０００９】
【課題を解決するための手段および発明の効果】
上記の課題を解決するための請求項１記載の発明は、第１の半導体基板の一方表面に形成された第１の金属突起と、第２の半導体基板の一方表面に形成された第２の金属突起とを接合して構成される半導体装置の製造方法であって、上記第１および第２の金属突起のうちの少なくとも一方の先端に低融点金属からなる層を形成する工程と、上記第１および第２の金属突起のうちの少なくとも一方の先端にフラックスを塗布するフラックス塗布工程と、このフラックス塗布工程の後、上記第１の半導体基板の上記一方表面と上記第２の半導体基板の上記一方表面とを対向させ、上記第１の金属突起と上記第２の金属突起とを、上記フラックスで仮固定する仮固定工程と、この仮固定工程の後、上記第１および第２の半導体基板を、上記低融点金属からなる層の固相線温度以上の温度に加熱する加熱工程とを含むことを特徴とする半導体装置の製造方法である。
【００１０】
この発明によれば、第１の金属突起と第２の金属突起とは、絶縁体であるフラックスを介して仮固定される。このため、第１および第２の半導体基板の一方が帯電している場合でも、この仮固定時には放電が起こらないから、他方の半導体基板に形成された機能素子が静電破壊されることがない。したがって、第１および第２の半導体基板には、これらの接合時の静電破壊を防止するための保護ダイオードを設ける必要がない。
【００１１】
仮固定の後、第１および第２の半導体基板を、低融点金属の固相線温度以上にすることにより、低融点金属の融液が生じる。その後、第１および第２の半導体基板を、低融点金属の固相線温度以下にすることにより、第１の金属突起と第２の金属突起とは、低融点金属の層を介して電気的および機械的に接合される。この際、第１の金属突起や第２の金属突起の表面に酸化膜が形成されている場合でも、フラックスの作用により酸化膜は除去され、低融点金属の融液は第１および第２の金属突起に対して良好な濡れ性を有することができる。したがって、第１および第２の金属突起は、低融点金属の層により良好に接合される。
【００１２】
第１および第２の金属突起は、たとえば、金からなるものであってもよく、低融点金属からなる層は、たとえば、錫からなるものであってもよい。
請求項２記載の発明は、上記加熱工程が、上記第１および第２の半導体基板に対して、それらを押し付け合う荷重をかけることのない実質的な無荷重状態で行われることを特徴とする請求項１記載の半導体装置の製造方法である。
この発明によれば、第１および第２の半導体基板は、実質的に無荷重の状態、たとえば、第１および第２の半導体基板のうち一方の半導体基板が水平に置かれ、その上に他方の半導体基板が載置されて加熱される。この状態では、第１および第２の半導体基板は、上方の半導体基板が自重のみで下方の半導体基板に押し付けられており、外部荷重によって互いに強制的に押しつけられていないので、相対的に移動することができる。このため、仮固定工程により、第１の金属突起と第２の金属突起とが、多少ずれて仮固定されていた場合でも、加熱工程により低融点金属の融液が生じると、低融点金属の融液の表面張力により、第１の金属突起と第２の金属突起とは、ずれが少なくなるように移動（セルフアライン）する。これにより、第１の半導体基板と第２の半導体基板とを位置ずれを少なくして接合できる。
【００１３】
また、第１および第２の半導体基板に荷重をかける工程を省くことができるので、生産性がよい。
請求項３記載の発明は、上記仮固定工程が、上記第２の半導体基板の上記一方表面上に複数の上記第１の半導体基板を仮固定する工程を含むことを特徴とする請求項１または２記載の半導体装置の製造方法である。
この発明によれば、第２の半導体基板上に複数の第１の半導体基板が仮固定された状態とした後に、第１および第２の半導体基板を一括して加熱することができる。すなわち、子チップの数だけ昇温および降温を繰り返す必要がない。これにより、第２の半導体基板と複数の第１の半導体基板とを、一括して接合することができるので、生産性がよい。
【００１４】
第１の半導体基板は、たとえば、半導体チップであってもよく、第２の半導体基板は、たとえば、半導体ウエハであってもよい。これらの場合、接合後、第２の半導体基板を切断して、チップ・オン・チップ構造を有する半導体チップの個片に切り出すことができる。
【００１５】
【発明の実施の形態】
以下では、添付図面を参照して、本発明の実施の形態について詳細に説明する。
図１は、本発明の一実施形態に係る製造方法により得られる半導体装置の図解的な断面図である。
この半導体装置は、第１の半導体基板としての子チップ２および子チップ３と、第２の半導体基板としての親チップ１とを、重ね合わせて接合した、いわゆるチップ・オン・チップ（Ｃｈｉｐ−Ｏｎ−Ｃｈｉｐ）構造を有している。子チップ２，３は、親チップ１より小さい。
【００１６】
親チップ１および子チップ２，３の互いに対向する表面は、それぞれ、機能素子や配線などが形成された活性面１ａ，２ａ，３ａとなっている。親チップ１の活性面１ａには、複数の金属突起（バンプ）４が設けられている。金属突起４は金（Ａｕ）からなる。活性面１ａの周縁部近傍で、活性面２ａ，３ａが対向していない部分には、外部取出用電極７が設けられている。
子チップ２，３の活性面２ａ，３ａには、金属突起４に対応する位置に金属突起５，６が設けられている。金属突起５，６は金（Ａｕ）からなる。金属突起４と金属突起５，６との間には、錫（Ｓｎ）からなる薄い層（図示せず。）が存在しており、金属突起４と金属突起５，６とは、この錫の層を介して接合されている。
【００１７】
親チップ１および子チップ２，３には、親チップ１と子チップ２，３との接合時に、親チップ１や子チップ２，３に形成された素子を静電破壊から保護するため保護ダイオード（金属突起４，５，６に接続されたダイオード）は形成されていない。このため、親チップ１および子チップ２，３は、このような保護ダイオードが形成された半導体チップと比べて、他の機能素子を多く形成できる。
親チップ１の活性面１ａとは反対側の面は、リードフレーム９の支持部（アイランド）９ａに接合されている。支持部９ａの側方には、支持部９ａと間隔をあけて、側方へ延びるリードフレーム９のリード端子部９ｂが配されている。外部取出用電極７とリード端子部９ｂとは、ボンディングワイヤ８により接続されている。親チップ１、子チップ２，３、支持部９ａ、ボンディングワイヤ８、およびボンディングワイヤ８とリード端子部９ｂとの接続部を含む領域は、封止樹脂１０で保護されている。
【００１８】
図２は、図１の半導体装置の製造方法を説明するための図解的な断面図であり、図３は、その金属突起４，５近傍の拡大図である。図３（ａ）は図２（ａ）に対応しており、図３（ｂ）は図２（ｂ）に対応しており、図３（ｃ）は図２（ｃ）に対応している。
半導体装置の製造に用いる半導体ウエハ（以下、単に「ウエハ」という。）Ｗは、親チップ１に対応する単位領域Ｕを多数（たとえば数千個）含んでいる（隣接する単位領域Ｕの境界を図２（ａ）（ｂ）に破線で示す。）。ウエハＷの活性面Ｗａは、親チップ１の活性面１ａに対応している。活性面Ｗａには金属突起４が形成されている。金属突起４の先端はほぼ平坦な面となっており、その面には錫からなる層（錫層）２０が予め形成されている（図３（ａ）参照）。
【００１９】
先ず、ウエハＷの活性面Ｗａに形成された金属突起４の先端に、ディッピング、転写等によりフラックス２２が塗布される。次に、ウエハＷが、活性面Ｗａが上方に向けられて、ほぼ水平に載置台１１の上に載置される。載置台１１の内部にはヒータ１２および温度センサ１３が設けられており、載置台１１の上に載置されたウエハＷを、温度センサ１３の出力に基づいて所定の温度に加熱可能である。
【００２０】
続いて、図２（ａ）に示すように、子チップ２が吸着コレット１４により、活性面２ａの反対側の面が吸着され、活性面２ａを下方に向けられてほぼ水平な状態でウエハＷに対向される。金属突起５の先端は、ほぼ平坦な面になっている。金属突起５の表面には、錫からなる層は形成されていない（図３（ａ）参照）。吸着コレット１４は、たとえば、真空吸着により子チップ２を吸着可能なものとすることができる。
【００２１】
この状態で、子チップ２の金属突起５と、対応するウエハＷの金属突起４とが位置合わせされ、吸着コレット１４が下降される。この際、金属突起４と金属突起５とは、図３（ａ）に示すように多少位置がずれていてもよい。金属突起４と金属突起５とが、ある程度近接されると、子チップ２の下降速度は小さくされる。
そして、金属突起５の下端が、フラックス２２の表面に接した後、錫層２０の表面に接触する前に、子チップの下降は停止され（図２（ｂ）および図３（ｂ）参照）、子チップ２は吸着コレット１４から離され、ウエハＷの上に載置される。これにより、金属突起５は、フラックス２２で金属突起４に仮固定された状態となる。
【００２２】
このように、吸着コレット１４により子チップ４がウエハＷに押しつけられないようにし、ウエハＷや子チップ２に荷重がかからないようにすることが好ましい。これにより、ウエハＷや子チップ２が破損することを回避することができる。ウエハＷや子チップ２に多少の荷重がかかっても問題はない
以上の工程において、たとえば、仮固定する前の子チップ２が帯電している場合がある。しかし、仮固定された状態で金属突起４と金属突起５とは、絶縁体であるフラックス２２により電気的に絶縁されているので、子チップ２からウエハＷへの放電は生じない。したがって、ウエハＷ（親チップ１）の金属突起４および子チップ２の金属突起５に接続された保護ダイオードが形成されていなくても、ウエハＷ（親チップ１）に形成された機能素子が静電破壊されることはない。
【００２３】
その後、子チップ２と同様にして、子チップ３がウエハＷに仮固定される。子チップ３の金属突起６は、子チップ２の金属突起５と同様、先端がほぼ平坦になっており、その表面には錫からなる層は形成されていない。
このようにして、１つの単位領域Ｕに、子チップ２，３が仮固定されたウエハＷが得られる。同様にして、ウエハＷのすべての単位領域Ｕに、子チップ２，３が仮固定される。この状態で、ウエハＷには、子チップ２，３の重量による荷重のみがかかっており、ウエハＷおよび子チップ２，３は実質的に無荷重である。以上の工程は、常温で行われる。
【００２４】
次に、載置台１１に設けられたヒータ１２により、ウエハＷが所定時間錫の融点以上の温度（たとえば、２４０℃以上）に加熱される。これにより、錫層２０は溶融、固化し、すべての子チップ２，３の金属突起５，６は、錫層２０を介してウエハＷの金属突起４に接合される。この際、金属突起４，５，６の表面などに酸化膜が形成されている場合でも、フラックス２２の作用により、酸化膜は除去され、金属突起４，５，６の表面は錫の融液に対する濡れ性が十分高くなり、金属突起４と金属突起５，６とは、錫層２０により良好に接合される。
【００２５】
さらに、ウエハＷおよび子チップ２，３は実質的に無荷重であるので、子チップ２，３はウエハＷに対して位置を変えることができる。このため、金属突起４に対して金属突起５，６がずれていた場合、錫の融液の表面張力により、金属突起４と金属突起５，６とは、ずれが少なくなるように移動（セルフアライン）する（図３（ｃ）参照）。すなわち、ウエハＷ（親チップ１）と子チップ２，３とを位置ずれを少なくして接合できる。
【００２６】
この後、ウエハＷは洗浄され、フラックス２２の残渣が除去される。続いて、図２（ｃ）に示すように、隣接した単位領域Ｕの境界に沿って、ウエハＷがダイシングソー２１で切断されることにより、子チップ２，３が接合された親チップ１が、ウエハＷから切り出される。さらに、親チップ１の活性面１ａとは反対側の面が支持部９ａに接合され、外部取出用電極７とリード端子部９ｂとが、ボンディングワイヤ８により接続された後、親チップ１、子チップ２，３などのまわりに封止樹脂１０がモールド成形されて、図１に示す半導体装置が得られる。
【００２７】
以上の半導体装置の製造方法において、親チップ１と子チップ２，３との接合は、すべての単位領域Ｕに子チップ２，３が仮固定されたウエハＷが加熱されることにより、一括して行われるので生産性がよい。また、従来の製造方法では、子チップの数だけウエハに対して加重および加熱が繰り返されるので、ウエハ等が破損しやすいが、以上の製造方法ではこのような問題は生じない。
この発明の一実施形態の説明は、以上の通りであるが、この発明は他の形態で実施することもできる。たとえば、ウエハＷおよび子チップ２，３を厳密に温度調整する必要がない場合は、温風を吹きつけることによりウエハＷおよび子チップ２，３を加熱してもよい。
【００２８】
錫層２０は、親チップ１の金属突起４に形成されておらず、子チップ２，３の金属突起５，６に形成されていてもよい。また、金属突起４および金属突起５，６の双方に錫層２０が形成されていてもよい。フラックス２２は、親チップ１の金属突起４に塗布されず、子チップ２，３の金属突起５，６に塗布されてもよい。また、金属突起４および金属突起５，６の双方にフラックス２２が塗布されてもよい。
【００２９】
フラックス２２は、金属突起５の一部および金属突起６の一部に塗布され、かつ、フラックス２２が塗布されていない金属突起５，６に対応する金属突起４に塗布されてもよい。
半導体装置は、１つの親チップ１の上に、１つの子チップ２（３）のみが接合されたものであってもよく、３つ以上の子チップが接合されたものであってもよい。さらに、子チップ２（３）の上に別の子チップが接合されたものであってもよい。
【００３０】
また、子チップ２，３の接合前にウエハＷを切断し、親チップ１に子チップ２，３を接合するようにしてもよい。
錫層２０の代わりに、他の低融点金属またはその合金（半田）、たとえば、インジウム（Ｉｎ）や、錫−鉛（Ｐｂ）系の合金、錫−銀（Ａｇ）−銅（Ｃｕ）系の合金などからなる層が形成されていてもよい。合金の場合は、親チップ１（ウエハＷ）および子チップ２，３の加熱温度は、その合金の固相線温度以上とすることができる。
【００３１】
子チップ２，３の接合の順序は、ウエハＷのすべての単位領域Ｕに子チップ２を接合した後、ウエハＷのすべての単位領域Ｕに子チップ３を接合することとしてもよい。
その他、特許請求の範囲に記載された事項の範囲で種々の変更を施すことが可能である。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る製造方法により得られる半導体装置の図解的な断面図である。
【図２】図１の半導体装置の製造方法を説明するための図解的な断面図である。
【図３】図２の金属突起４，５近傍の拡大図である。
【符号の説明】
１　　親チップ
２，３　　子チップ
４，５，６　　金属突起
１２　　ヒータ
２０　　錫層
２２　　フラックス
Ｗ　　ウエハ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a chip-on-chip structure in which another semiconductor chip is bonded onto a semiconductor chip.
[0002]
[Prior art]
As one mode of a so-called multi-chip semiconductor device, there is a chip-on-chip structure in which a plurality of semiconductor chips are stacked. In a semiconductor device having a chip-on-chip structure, a child chip smaller than the parent chip is bonded to the surface of the parent chip to be externally connected. In some cases, a plurality of child chips are joined to the surface of one parent chip.
[0003]
Each of the parent chip and the child chip has a plurality of metal protrusions (bumps) on an active surface on which functional elements and wirings are formed. These metal projections are mainly made of a high melting point metal such as gold (Au), and both or one of the metal projections of the parent chip and the child chip are made of a low melting point metal such as tin (Sn) at the tip. A layer is formed.
In the manufacturing process of the semiconductor device having a chip-on-chip structure, the active surface of the parent chip and the active surface of the child chip are opposed to each other so that the metal projection of the parent chip and the metal projection of the child chip are pressed. A load is applied to the tip and the child tip. In this state, the parent chip and the child chip are heated to a temperature equal to or higher than the melting point (solidus temperature) of the low melting point metal. Thereby, the layer made of the low melting point metal formed at the tip of the metal projection is melted.
[0004]
After that, the temperatures of the parent chip and the child chip are lowered to the melting point of the low melting point metal or lower. As a result, the low-melting metal is solidified, and the metal projection of the parent chip and the metal projection of the child chip are electrically and mechanically joined via the low-melting metal. Even when an oxide film is formed on the surface of the metal protrusion of the parent chip or the metal protrusion of the child chip, the oxide film is broken by pressing the metal protrusion of the parent chip and the metal protrusion of the child chip. The first and second metal projections are better joined by the low melting point metal.
[0005]
The bonding may be performed in a state of the wafer before cutting out the parent chip. In this case, after joining the semiconductor wafer and the child chip, the semiconductor wafer is cut into individual semiconductor chips having a chip-on-chip structure.
[0006]
[Problems to be solved by the invention]
However, the semiconductor wafer has a large number (for example, thousands) of regions corresponding to the parent chips, and it is impossible to simultaneously press the sub chips against the regions corresponding to all the parent chips and heat them. For this reason, the process of carrying the child chip to a predetermined position on the semiconductor wafer by the suction collet, and raising and lowering the temperature while applying a load to this child chip must be repeated by the number of the child chips, resulting in poor productivity. Was.
[0007]
Also, when joining the parent chip and the child chip, the metal projection of the parent chip and the metal projection of the child chip must be accurately aligned. Because of the inconsistency of the device, the accuracy of positioning could not be increased.
Furthermore, when the parent chip and the child chip are joined, for example, when the child chip is charged, when the metal projection of the parent chip contacts the metal projection of the child chip, the functional element formed on the parent chip is replaced with the child element. Electrostatic damage is caused by discharge from the chip. To avoid such a situation, the parent chip is provided with a protection diode connected to the metal protrusion. However, the protection diode is essentially unnecessary, and the provision of the protection diode reduces the area for forming other functional elements.
[0008]
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device having high productivity.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of bonding a plurality of semiconductor substrates with a small displacement.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device which does not need to provide a protection diode on a semiconductor substrate for preventing electrostatic breakdown when a plurality of semiconductor substrates are joined.
[0009]
Means for Solving the Problems and Effects of the Invention
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first metal projection formed on one surface of a first semiconductor substrate; and a second metal projection formed on one surface of a second semiconductor substrate. A method of manufacturing a semiconductor device formed by bonding a metal projection to a semiconductor device, the method comprising: forming a layer made of a low-melting-point metal on at least one end of the first and second metal projections; A flux application step of applying a flux to at least one end of the first and second metal protrusions; and, after the flux application step, the one surface of the first semiconductor substrate and the flux of the second semiconductor substrate. A temporary fixing step of temporarily fixing the first metal projection and the second metal projection with the flux while facing the one surface, and, after the temporary fixing step, the first and second semiconductor substrates. The above low melting point gold Comprise a heating step of heating the solidus temperature above the temperature of the layer made of a method of manufacturing a semiconductor device according to claim.
[0010]
According to the present invention, the first metal projection and the second metal projection are temporarily fixed via the flux which is an insulator. For this reason, even if one of the first and second semiconductor substrates is charged, no discharge occurs at the time of the temporary fixing, so that the functional element formed on the other semiconductor substrate is not electrostatically damaged. . Therefore, it is not necessary to provide the first and second semiconductor substrates with a protection diode for preventing electrostatic breakdown at the time of joining them.
[0011]
After the temporary fixing, the first and second semiconductor substrates are heated to a solidus temperature or higher of the low melting point metal, whereby a melt of the low melting point metal is generated. Thereafter, the first and second semiconductor substrates are set to a temperature equal to or lower than the solidus temperature of the low melting point metal, so that the first metal protrusion and the second metal protrusion are electrically connected via the low melting point metal layer. And mechanically joined. At this time, even when an oxide film is formed on the surface of the first metal protrusion or the second metal protrusion, the oxide film is removed by the action of the flux, and the low-melting-point metal melt is removed from the first and second metal protrusions. Good wettability with respect to metal projections can be obtained. Therefore, the first and second metal protrusions are better joined to the low melting point metal layer.
[0012]
The first and second metal protrusions may be made of, for example, gold, and the layer made of the low melting point metal may be made of, for example, tin.
The invention according to claim 2 is characterized in that the heating step is performed in a substantially no-load state without applying a load pressing the first and second semiconductor substrates against each other. A method of manufacturing a semiconductor device according to claim 1.
According to the present invention, the first and second semiconductor substrates are substantially in a state of no load, for example, one of the first and second semiconductor substrates is placed horizontally, and the other is placed thereon. Is placed and heated. In this state, the first and second semiconductor substrates move relatively because the upper semiconductor substrate is pressed against the lower semiconductor substrate only by its own weight and is not forcibly pressed against each other by an external load. be able to. For this reason, even if the first metal projection and the second metal projection are temporarily fixed with a slight deviation in the temporary fixing step, if the low-melting-point metal melt is generated in the heating step, the low-melting-point metal is not fixed. Due to the surface tension of the melt, the first metal protrusion and the second metal protrusion move (self-align) so as to reduce the deviation. Thus, the first semiconductor substrate and the second semiconductor substrate can be joined with less displacement.
[0013]
Further, since a step of applying a load to the first and second semiconductor substrates can be omitted, productivity is high.
The invention according to claim 3 is characterized in that the temporary fixing step includes a step of temporarily fixing the plurality of first semiconductor substrates on the one surface of the second semiconductor substrate. 3. A method for manufacturing a semiconductor device according to item 2.
According to this invention, after the plurality of first semiconductor substrates are temporarily fixed on the second semiconductor substrate, the first and second semiconductor substrates can be heated collectively. That is, there is no need to repeat the temperature increase and decrease by the number of child chips. Thus, the second semiconductor substrate and the plurality of first semiconductor substrates can be joined together at a time, so that productivity is high.
[0014]
The first semiconductor substrate may be, for example, a semiconductor chip, and the second semiconductor substrate may be, for example, a semiconductor wafer. In these cases, after bonding, the second semiconductor substrate can be cut and cut into individual semiconductor chips having a chip-on-chip structure.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view of a semiconductor device obtained by a manufacturing method according to one embodiment of the present invention.
This semiconductor device has a so-called chip-on-chip (Chip-On) in which a child chip 2 and a child chip 3 as a first semiconductor substrate and a parent chip 1 as a second semiconductor substrate are overlapped and joined. -Chip) structure. The child chips 2 and 3 are smaller than the parent chip 1.
[0016]
Opposite surfaces of the parent chip 1 and the child chips 2 and 3 are active surfaces 1a, 2a and 3a on which functional elements and wirings are formed, respectively. A plurality of metal projections (bumps) 4 are provided on the active surface 1 a of the parent chip 1. The metal projection 4 is made of gold (Au). An external extraction electrode 7 is provided in a portion near the periphery of the active surface 1a and where the active surfaces 2a and 3a do not face each other.
On the active surfaces 2a, 3a of the daughter chips 2, 3, metal projections 5, 6 are provided at positions corresponding to the metal projections 4. The metal projections 5 and 6 are made of gold (Au). A thin layer (not shown) made of tin (Sn) exists between the metal protrusion 4 and the metal protrusions 5 and 6, and the metal protrusion 4 and the metal protrusions 5 and 6 They are joined through layers.
[0017]
Protection diodes for protecting the elements formed on the parent chip 1 and the child chips 2 and 3 from electrostatic damage when the parent chip 1 and the child chips 2 and 3 are joined. (Diodes connected to metal protrusions 4, 5, 6) are not formed. For this reason, the parent chip 1 and the child chips 2 and 3 can form more other functional elements than the semiconductor chip on which such a protection diode is formed.
The surface of the parent chip 1 opposite to the active surface 1a is joined to the support (island) 9a of the lead frame 9. A lead terminal portion 9b of the lead frame 9 extending laterally is arranged on the side of the support portion 9a with an interval from the support portion 9a. The external extraction electrode 7 and the lead terminal portion 9b are connected by a bonding wire 8. A region including the parent chip 1, the child chips 2 and 3, the support portion 9a, the bonding wire 8, and the connection portion between the bonding wire 8 and the lead terminal portion 9b is protected by the sealing resin 10.
[0018]
FIG. 2 is an illustrative sectional view for explaining a method of manufacturing the semiconductor device of FIG. 1, and FIG. 3 is an enlarged view of the vicinity of the metal projections 4 and 5. 3 (a) corresponds to FIG. 2 (a), FIG. 3 (b) corresponds to FIG. 2 (b), and FIG. 3 (c) corresponds to FIG. 2 (c). .
A semiconductor wafer (hereinafter, simply referred to as a “wafer”) W used for manufacturing a semiconductor device includes a large number (for example, thousands) of unit regions U corresponding to the parent chip 1 (a boundary between adjacent unit regions U is defined as a boundary). 2 (a) and 2 (b) show by broken lines.) The active surface Wa of the wafer W corresponds to the active surface 1a of the parent chip 1. The metal projection 4 is formed on the active surface Wa. The tip of the metal projection 4 is a substantially flat surface, on which a layer (tin layer) 20 made of tin is formed in advance (see FIG. 3A).
[0019]
First, the flux 22 is applied to the tip of the metal protrusion 4 formed on the active surface Wa of the wafer W by dipping, transfer, or the like. Next, the wafer W is mounted on the mounting table 11 substantially horizontally with the active surface Wa facing upward. A heater 12 and a temperature sensor 13 are provided inside the mounting table 11, and the wafer W mounted on the mounting table 11 can be heated to a predetermined temperature based on an output of the temperature sensor 13.
[0020]
Subsequently, as shown in FIG. 2A, the child chip 2 is sucked by the suction collet 14 on the surface opposite to the active surface 2a, and the active surface 2a is directed downward so that the wafer W is substantially horizontal. Is opposed to. The tip of the metal projection 5 has a substantially flat surface. No layer made of tin is formed on the surface of the metal projection 5 (see FIG. 3A). The suction collet 14 can be made to be capable of sucking the child chip 2 by vacuum suction, for example.
[0021]
In this state, the metal protrusion 5 of the child chip 2 and the corresponding metal protrusion 4 of the wafer W are aligned, and the suction collet 14 is lowered. At this time, the positions of the metal protrusions 4 and the metal protrusions 5 may be slightly shifted as shown in FIG. When the metal protrusions 4 and the metal protrusions 5 are approached to some extent, the descending speed of the child chip 2 is reduced.
Then, after the lower end of the metal projection 5 comes into contact with the surface of the flux 22 and before it comes into contact with the surface of the tin layer 20, the lowering of the child chip is stopped (see FIGS. 2B and 3B). The child chip 2 is separated from the suction collet 14 and placed on the wafer W. As a result, the metal projection 5 is temporarily fixed to the metal projection 4 by the flux 22.
[0022]
As described above, it is preferable that the child chip 4 is not pressed against the wafer W by the suction collet 14 so that no load is applied to the wafer W and the child chip 2. Thereby, it is possible to prevent the wafer W and the sub chip 2 from being damaged. In the above process, there is no problem even if a slight load is applied to the wafer W or the sub chip 2, for example, the sub chip 2 before being temporarily fixed may be charged. However, since the metal protrusions 4 and 5 are electrically insulated by the flux 22 which is an insulator in the temporarily fixed state, no discharge occurs from the daughter chips 2 to the wafer W. Therefore, even if the protection diode connected to the metal projection 4 of the wafer W (parent chip 1) and the metal projection 5 of the child chip 2 is not formed, the functional elements formed on the wafer W (parent chip 1) are static. It is not destroyed by electricity.
[0023]
Thereafter, the child chip 3 is temporarily fixed to the wafer W in the same manner as the child chip 2. Like the metal projections 5 of the child chip 2, the metal projections 6 of the child chip 3 have substantially flat ends, and no tin layer is formed on the surface thereof.
In this way, a wafer W on which the sub chips 2 and 3 are temporarily fixed in one unit area U is obtained. Similarly, child chips 2 and 3 are temporarily fixed to all unit areas U of wafer W. In this state, only the load due to the weight of the child chips 2 and 3 is applied to the wafer W, and the wafer W and the child chips 2 and 3 are substantially unloaded. The above steps are performed at normal temperature.
[0024]
Next, the wafer W is heated to a temperature equal to or higher than the melting point of tin (for example, 240 ° C. or higher) for a predetermined time by the heater 12 provided on the mounting table 11. As a result, the tin layer 20 is melted and solidified, and the metal projections 5 and 6 of all the sub chips 2 and 3 are joined to the metal projections 4 of the wafer W via the tin layer 20. At this time, even when an oxide film is formed on the surface of the metal projections 4, 5, 6, etc., the oxide film is removed by the action of the flux 22, and the surface of the metal projections 4, 5, 6 is melted with tin. The metal projections 4 and the metal projections 5 and 6 are sufficiently bonded to the tin layer 20.
[0025]
Further, since the wafer W and the sub chips 2 and 3 are substantially free from a load, the sub chips 2 and 3 can change positions with respect to the wafer W. For this reason, when the metal projections 5 and 6 are shifted from the metal projection 4, the metal projections 4 and the metal projections 5 and 6 move so as to reduce the shift (self-alignment) due to the surface tension of the tin melt. (See FIG. 3C). That is, the wafer W (parent chip 1) and the child chips 2 and 3 can be joined with less displacement.
[0026]
Thereafter, the wafer W is cleaned, and the residue of the flux 22 is removed. Subsequently, as shown in FIG. 2C, the wafer W is cut by the dicing saw 21 along the boundary of the adjacent unit area U, so that the parent chip 1 to which the child chips 2 and 3 are joined is formed. , From the wafer W. Further, the surface of the parent chip 1 opposite to the active surface 1a is joined to the support portion 9a, and after the external extraction electrode 7 and the lead terminal portion 9b are connected by the bonding wire 8, the parent chip 1 and the child The sealing resin 10 is molded around the chips 2, 3 and the like to obtain the semiconductor device shown in FIG.
[0027]
In the above-described method for manufacturing a semiconductor device, the bonding of the parent chip 1 and the child chips 2 and 3 is performed by heating the wafer W on which the child chips 2 and 3 are temporarily fixed in all the unit areas U. The productivity is good. In addition, in the conventional manufacturing method, the weight and the heating are repeated on the wafer by the number of the child chips, so that the wafer or the like is easily damaged. However, such a problem does not occur in the above manufacturing method.
Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms. For example, when it is not necessary to strictly control the temperature of the wafer W and the child chips 2 and 3, the wafer W and the child chips 2 and 3 may be heated by blowing hot air.
[0028]
The tin layer 20 may not be formed on the metal projections 4 of the parent chip 1 but may be formed on the metal projections 5 and 6 of the child chips 2 and 3. Further, the tin layer 20 may be formed on both the metal protrusion 4 and the metal protrusions 5 and 6. The flux 22 may not be applied to the metal projections 4 of the parent chip 1 but may be applied to the metal projections 5 and 6 of the child chips 2 and 3. Further, the flux 22 may be applied to both the metal protrusions 4 and the metal protrusions 5 and 6.
[0029]
The flux 22 may be applied to a part of the metal projection 5 and a part of the metal projection 6, and may be applied to the metal projection 4 corresponding to the metal projection 5, 6 to which the flux 22 is not applied.
The semiconductor device may be one in which only one child chip 2 (3) is joined on one parent chip 1, or one in which three or more child chips are joined. Further, another child chip may be joined to the child chip 2 (3).
[0030]
Further, the wafer W may be cut before the child chips 2 and 3 are joined, and the child chips 2 and 3 may be joined to the parent chip 1.
Instead of the tin layer 20, another low melting point metal or its alloy (solder), for example, indium (In), tin-lead (Pb) -based alloy, tin-silver (Ag) -copper (Cu) -based A layer made of an alloy or the like may be formed. In the case of an alloy, the heating temperature of the parent chip 1 (wafer W) and the child chips 2 and 3 can be equal to or higher than the solidus temperature of the alloy.
[0031]
The bonding order of the child chips 2 and 3 may be such that after bonding the child chips 2 to all the unit regions U of the wafer W, the child chips 3 are bonded to all the unit regions U of the wafer W.
In addition, various changes can be made within the scope of the matters described in the claims.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a semiconductor device obtained by a manufacturing method according to an embodiment of the present invention.
FIG. 2 is an illustrative sectional view for explaining the method for manufacturing the semiconductor device in FIG. 1;
FIG. 3 is an enlarged view of the vicinity of metal protrusions 4 and 5 in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Parent chip 2, 3 Child chip 4, 5, 6 Metal protrusion 12 Heater 20 Tin layer 22 Flux W wafer

Claims (3)

第１の半導体基板の一方表面に形成された第１の金属突起と、第２の半導体基板の一方表面に形成された第２の金属突起とを接合して構成される半導体装置の製造方法であって、
上記第１および第２の金属突起のうちの少なくとも一方の先端に低融点金属からなる層を形成する工程と、
上記第１および第２の金属突起のうちの少なくとも一方の先端にフラックスを塗布するフラックス塗布工程と、
このフラックス塗布工程の後、上記第１の半導体基板の上記一方表面と上記第２の半導体基板の上記一方表面とを対向させ、上記第１の金属突起と上記第２の金属突起とを、上記フラックスで仮固定する仮固定工程と、
この仮固定工程の後、上記第１および第２の半導体基板を、上記低融点金属からなる層の固相線温度以上の温度に加熱する加熱工程とを含むことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device configured by joining a first metal protrusion formed on one surface of a first semiconductor substrate and a second metal protrusion formed on one surface of a second semiconductor substrate. So,
Forming a layer made of a low melting point metal on at least one end of the first and second metal protrusions;
A flux applying step of applying a flux to at least one end of the first and second metal protrusions;
After this flux application step, the one surface of the first semiconductor substrate and the one surface of the second semiconductor substrate are opposed to each other, and the first metal protrusion and the second metal protrusion are A temporary fixing step of temporarily fixing with a flux,
Heating the first and second semiconductor substrates to a temperature equal to or higher than the solidus temperature of the layer made of the low-melting-point metal after the temporary fixing step. Method. 上記加熱工程が、上記第１および第２の半導体基板に対して、それらを押し付け合う荷重をかけることのない実質的な無荷重状態で行われることを特徴とする請求項１記載の半導体装置の製造方法。2. The semiconductor device according to claim 1, wherein the heating step is performed with substantially no load applied to the first and second semiconductor substrates without applying a load for pressing them. Production method. 上記仮固定工程が、上記第２の半導体基板の上記一方表面上に複数の上記第１の半導体基板を仮固定する工程を含むことを特徴とする請求項１または２記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein said temporarily fixing step includes a step of temporarily fixing a plurality of said first semiconductor substrates on said one surface of said second semiconductor substrate. .
JP2002236036A 2002-08-01 2002-08-13 Manufacturing method of semiconductor device Expired - Lifetime JP4009505B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006016449A1 (en) * 2004-08-11 2006-02-16 Rohm Co., Ltd. Electronic device, semiconductor device using same, and method for manufacturing semiconductor device
US7772032B2 (en) 2007-11-28 2010-08-10 Nec Electronics Corporation Manufacturing method for electronic devices
US7951699B2 (en) 2005-12-15 2011-05-31 Renesas Electronics Corporation Method of manufacturing semiconductor device
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006016449A1 (en) * 2004-08-11 2006-02-16 Rohm Co., Ltd. Electronic device, semiconductor device using same, and method for manufacturing semiconductor device
JP2006054311A (en) * 2004-08-11 2006-02-23 Rohm Co Ltd Electronic device, semiconductor device using the same, and method for manufacturing the semiconductor device
US7612456B2 (en) 2004-08-11 2009-11-03 Rohm Co., Ltd. Electronic device, semiconductor device using same, and method for manufacturing semiconductor device
KR101140481B1 (en) 2004-08-11 2012-04-30 로무 가부시키가이샤 Electronic device, semiconductor device using same, and method for manufacturing semiconductor device
US7951699B2 (en) 2005-12-15 2011-05-31 Renesas Electronics Corporation Method of manufacturing semiconductor device
US7772032B2 (en) 2007-11-28 2010-08-10 Nec Electronics Corporation Manufacturing method for electronic devices
US7977158B2 (en) 2007-11-28 2011-07-12 Renesas Electronics Corporation Manufacturing method for electronic devices
US8278143B2 (en) 2007-11-28 2012-10-02 Renesas Electronics Corporation Manufacturing method for electronic devices
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

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