JP2004077743A - Current sampling circuit and current output type drive circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a current sampling circuit and a current output type drive circuit which are suitable to a high-gradation organic EL display by writing the output of a D/A converting circuit to a plurality of current sampling circuits on a time-division basis and making it possible to lay out a multi-bit D/A converting circuit, and simplifying the distribution of a reference current in a chip and improving the accuracy of the current. <P>SOLUTION: A register array which holds input data, a current output type D/A converting circuit which outputs a current corresponding to the held data in the register array, and a current output circuit having a 1st group of current sampling circuits and a 2nd group of current sampling circuits which operate alternately in a current write mode and a current readout mode are provided. When a current is written, the output current of the D/A converting circuit is inputted to each of the current sampling circuits on a time-division basis and when a current is read out, a current equal to the current captured when a current is written is outputted, so that a highly accurate driving current can be supplied to a load circuit. <P>COPYRIGHT: (C)2004,JPO

Description

【００７０】
同様に、第２のＭＯＳトランジスタＭ２について、次式が得られる。
【００７１】
【数２】

【００７２】
式（１）と（２）において、Ｗ１とＷ２は、それぞれトランジスタＭ１とＭ２のチャネル幅を示し、ＬはトランジスタＭ１とＭ２のチャネル長を示す。Ｉ_ｍａｘは、電流出力型駆動回路の出力電流の最大値である。
【００７３】
式（１）と（２）におけるＶ_ｅｆｆ１とＶ_ｅｆｆ２は、ＭＯＳトランジスタＭ１とＭ２に電流を流すために必要な実効的な電圧と言える。この実効的な電圧が小さいと、ドレイン−ゲート間のカップリング容量の影響やスイッチング素子ＳＷ１、ＳＷ２のオン／オフ時の影響を受けやすくなる。
カスコードの構成をとるＭＯＳトランジスタＭ１とＭ２に印加される最大の電圧Ｖ_ｍａｘ　は、次式によって与えられる。
【００７４】
【数３】

【００７５】
式（３）において、定数αは、スイッチング素子ＳＷ３とＳＷ４を構成するＭＯＳトランジスタのドレイン−ソース間の電圧で、α＝Ｖ_ＤＳ≒０．２Ｖ程度である。ＤＡＣ出力との接続を考えると、最大電圧Ｖ_ｍａｘ　は、次式によって与えられる。
【００７６】
【数４】
Ｖ_ｍａｘ　≦（１／２）Ｖ_ＤＤ　　　　　　　…（４）
【００７７】
ここで、Ｖ_ｔｈ＝０．７５Ｖ、Ｖ_ＤＤ＝４．７５Ｖとすると、次の結果が得られる。
【００７８】
【数５】
Ｖ_ｅｆｆ１＋Ｖ_ｅｆｆ２＝０．６７５Ｖ　　　　　　　　…（５）
【００７９】
式（５）によると、Ｖ_ｅｆｆ１やＶ_ｅｆｆ２は、数百ｍＶというかなり小さな電圧をとることが分かる。サンプリングホールド時に発生する数ｍＶの誤差も問題になるため、回路設計においてもレイアウト設計においても十分な注意が必要である。
【００８０】
第４実施形態
図６〜図８は本発明に係るカレントサンプリング回路の第４の実施形態の各実施例を示す回路図である。
図６〜図８に示す実施例は、図１に示す本発明の第１の実施形態のカレントサンプリング回路とほぼ同じ構成を有する。ただし、それぞれの実施例において、ＭＯＳトランジスタＭ１とＭ２のチャネル長、バルクバイアスまたはしきい値電圧が上述した本発明の第１の実施形態と異なる。
【００８１】
まず、図６に示すカレントサンプリング回路の実施例では、ＭＯＳトランジスタＭ２のチャネル幅がＭＯＳトランジスタＭ１のチャネル幅より大きく形成されている。即ち、ここで、ＭＯＳトランジスタＭ１のチャネル幅をＷ１、ＭＯＳトランジスタＭ２のチャネル幅をＷ２とすると、Ｗ２＞Ｗ１である。
【００８２】
カレントサンプリング回路の電流読み出し時には、ＭＯＳトランジスタＭ２はカスコードのトランジスタの働きをし、ＭＯＳトランジスタＭ１側で出力電流が決まる。ＭＯＳトランジスタＭ１のゲート電圧がずれると、読み出し電流が目標の電流値よりずれてしまう。しかし、ＭＯＳトランジスタＭ２のゲート電圧が多少ずれてもカスコードの働きには問題がない。
このため、本実施形態のカレントサンプリング回路では、Ｖ_ｅｆｆ１＞Ｖ_ｅｆｆ２、即ち、Ｗ２＞Ｗ１の条件でＭＯＳトランジスタＭ１とＭ２のチャネル幅を設計することによって、電流読み出し時の出力電流の精度を改善できる。
【００８３】
次に、図７に示すカレントサンプリング回路の実施例では、ＭＯＳトランジスタＭ２のバルクバイアス電圧をそのソースからとる。即ち、図７に示すように、ＭＯＳトランジスタＭ２の基板（バルク）がそのソースに接続されている。これによって、ＭＯＳトランジスタＭ２のバルクバイアス電圧がそのソース電圧によって決まる。
【００８４】
ＭＯＳトランジスタＭ２の基板が電源電圧Ｖ_ＤＤに接続する場合、ソース電圧とバルク電圧に差があるため、基板バイアス効果により、式（３）の代わりに、次式が成り立つ。
【００８５】
【数６】

【００８６】
本実施例のカレントサンプリング回路において、ＭＯＳトランジスタＭ２のバルクをソースに接続することで、基板バイアス効果分ΔＶ_ｔｈだけ最大出力電流Ｉ_ｍａｘ　が大きくなる。
【００８７】
図８に示すカレントサンプリング回路の実施例では、ＭＯＳトランジスタＭ１とＭ２のしきい値電圧Ｖ_ｔｈは通常より低く形成されている。即ち、ＭＯＳトランジスタＭ１とＭ２は低しきい値電圧トランジスタからなる。
【００８８】
上述した式（３）によると、電圧Ｖ_ｍａｘ　はトランジスタＭ１とＭ２のしきい値電圧Ｖ_ｔｈに影響される。このため、本実施例のように、低しきい値電圧のＭＯＳトランジスタＭ１とＭ２を用いることにより、トランジスタＭ１とＭ２の実行的な電圧Ｖ_ｅｆｆ１とＶ_ｅｆｆ２を維持しつつ、電圧Ｖ_ｍａｘ　を低くすることができる。即ち電圧Ｖ_ｍａｘ　を低くしてもカレントサンプリング回路が正常に動作でき、低電源電圧での動作特性が改善される。
【００８９】
第５実施形態
図９〜図１０は本発明に係るカレントサンプリング回路の第５の実施形態の各実施例を示す回路図である。
図９に示す本実施形態のカレントサンプリング回路の実施例は、図５に示す本発明のカレントサンプリング回路の第３の実施形態の回路例とほぼ同じ構成を有する。ただし、本実施例のカレントサンプリング回路において、スイッチング素子ＳＷ１とＳＷ２は、それぞれｐＭＯＳトランジスタＭ３とＭ４によって構成され、かつ、トランジスタＭ４のチャネル幅がトランジスタＭ３のチャネル幅より大きく形成されている。
【００９０】
本実施例のカレントサンプリング回路において、スイッチング素子ＳＷ２を構成するＭＯＳトランジスタＭ４は、中間電圧付近で電流を流さなければならない。電源電圧が低下したときに、トランジスタの基板バイアス効果による影響で、電流を流しにくくなってしまう。そのため、スイッチング素子ＳＷ１を構成するＭＯＳトランジスタＭ３のチャネル幅Ｗ３よりもスイッチング素子ＳＷ２を構成するＭＯＳトランジスタＭ４のチャネル幅Ｗ４の方を大きく設計することにより、低電源電圧で動作するときにスイッチング素子ＳＷ２の電流を所定値に保持することができ、カレントサンプリング回路の動作特性が改善される。
【００９１】
図１０は、本実施形態のカレントサンプリング回路のもう一つの実施例を示す回路図である。
図示のように、本実施例のカレントサンプリング回路は、図９に示すカレントサンプリング回路の実施例とほぼ同じ構成を有するが、図９の実施例との相違点は、スイッチング素子ＳＷ２が並列に接続されているｐＭＯＳトランジスタＭ４とｎＭＯＳトランジスタＭ５によって構成されている。
【００９２】
上述したように、スイッチング素子ＳＷ２は、中間電圧付近で電流を流さなければならない。このため、本実施例のカレントサンプリング回路では、スイッチング素子ＳＷ２をｐＭＯＳトランジスタＭ４とｎＭＯＳトランジスタＭ５を並列に接続して構成している。これにより、中間電圧でも十分な電流を流せるようになり、カレントサンプリング回路の動作特性が改善される。
【００９３】
第６の実施形態
図１１〜１３は、本発明に係るカレントサンプリング回路の第６の実施形態の実施例を示す回路図である。
なお、本実施形態のカレントサンプリング回路は、その電流保持特性を改善するための工夫が施されている。
【００９４】
図１１に示すカレントサンプリング回路の実施例において、ホールド状態では、スイッチング素子ＳＷ１を構成するＭＯＳトランジスタＭ３、スイッチング素子ＳＷ２を構成するＭＯＳトランジスタＭ４、及びスイッチング素子ＳＷ３とＳＷ４を構成するＭＯＳトランジスタは何れもオフしている。
【００９５】
このため、ＭＯＳトランジスタＭ１のドレイン電圧とＭＯＳトランジスタＭ２のドレイン電圧は電源電圧Ｖ_ＤＤに等しくなる。したがって、容量素子Ｃ１に保持された電圧は、スイッチング素子ＳＷ１を構成するＭＯＳトランジスタＭ３のリーク電流によって次第に電源電圧Ｖ_ＤＤに向かって経時変化することになる。同様に、容量素子Ｃ２に保持された電圧は、スイッチング素子ＳＷ２を構成するＭＯＳトランジスタＭ４のリーク電流によって次第に電源電圧Ｖ_ＤＤに向かって経時変化することになる。
【００９６】
ＭＯＳトランジスタのリーク電流はゲート長がプロセスのバラツキによって短くなってしきい値電圧Ｖ_ｔｈが低下したときに急激に増加する。
本実施例のカレントサンプリング回路において、スイッチング素子ＳＷ１を構成するＭＯＳトランジスタＭ３とスイッチング素子ＳＷ２を構成するＭＯＳトランジスタＭ４のチャネル長の設計値を通常よりも大きめに設計する。即ち、図１１に示すように、ＭＯＳトランジスタＭ３とＭ４のチャネル長をＬ＋αとする。これによって、ホールド時にトランジスタＭ３とＭ４のリーク電流が低減するので、保持特性の劣化を防止できる。
【００９７】
図１２に示すカレントサンプリング回路の実施例において、他のカレントサンプリング回路の実施例に較べて、スイッチング素子ＳＷ７及びＭＯＳトランジスタＭ８を追加することにより、ホールド状態のとき、トランジスタＭ１とＭ２に電流経路を形成する。これによって、スイッチング素子ＳＷ１とＳＷ２の電圧差を低減させ、リーク電流の低減を図る。
【００９８】
図１２において、トランジスタＭ８はダイオード接続され、ダミーの負荷回路を形成している。ホールドのとき、スイッチング素子ＳＷ７がオンするので、カスコード接続されているトランジスタＭ１とＭ２にトランジスタＭ８からなるダミーの負荷回路が直列接続される。このため、電流書き込み時にキャパシタＣ１とＣ２に保持されている電圧により、トランジスタＭ１とＭ２がオン状態に保持されるので、電源電圧Ｖ_ＤＤから、トランジスタＭ８からなるダミーの負荷回路までに電流経路が形成され、電流が流れる。これにより、スイッチング素子ＳＷ１の両端の電圧差やスイッチング素子ＳＷ２の両端の電圧差が小さくなるので、これらのスイッチング素子ＳＷのリーク電流を小さくすることができる。
【００９９】
図１３は、図１２に示す本実施例のカレントサンプリング回路の動作を示すタイミングチャートである。
図１３に示すように、電流書き込みのとき、スイッチング素子ＳＷ１，ＳＷ２及びＳＷ３がオンし、その他のスイッチング素子がオフする。この状態において、入力端子Ｔ_ｉｎから入力される電流に応じて生じたトランジスタＭ１とＭ２のゲート電圧がそれぞれ容量素子Ｃ１とＣ２によって保持される。
【０１００】
次に、ホールドのとき、スイッチング素子ＳＷ５，ＳＷ６及びＳＷ７がオンし、他のスイッチング素子がオフする。この状態において、トランジスタＭ１とＭ２及びトランジスタＭ８が、電源電圧Ｖ_ＤＤと基準電位Ｖ_ＳＳの間で直列接続されるので、トランジスタＭ１とＭ２に、キャパシタＣ１とＣ２によって保持されているゲート電圧に応じた電流が流れる。
これによって、トランジスタＭ１とＭ２それぞれのゲート−ソース間電圧が低下する。即ち、オフ状態にあるスイッチング素子ＳＷ１とＳＷ２の両端の電圧が低下する。このため、スイッチング素子ＳＷ１とＳＷ２のリーク電流が低減され、カレントサンプリング回路の保持特性が改善される。
【０１０１】
次に、電流読み出しのとき、スイッチング素子ＳＷ４がオンし、それ以外のスイッチング素子がすべてオフする。このとき、キャパシタＣ１とＣ２に保持されている電圧により、トランジスタＭ１とＭ２それぞれのゲート電圧が決まり、それに応じた出力電圧Ｉ_ｏｕｔ　がスイッチング素子ＳＷ４を介して、負荷回路に出力される。
【０１０２】
上記の本実施形態の各実施例によれば、カレントサンプリング回路の電流保持特性を改善でき、例えば、数μｓｅｃ（マイクロ秒）〜数十μｓｅｃの間でホールドしても全く視認できないレベルに経時変化を抑えることができる。即ち、本実施形態の各実施例によれば、カレントサンプリング回路の電流保持特性を向上させることができ、これにより電流書き込み時に負荷回路に供給する出力電流を書き込み電流とほぼ一致させることでき、出力電流を高精度に制御することが可能である。
【０１０３】
以上、本発明のカレントサンプリング回路のそれぞれの実施形態を説明した。以下、本発明のカレントサンプリング回路を用いて構成された電流出力型駆動回路について説明する。
【０１０４】
第７の実施形態
図１４は、本発明に係る電流出力型駆動回路の一実施形態を示す構成図である。図示のように、本実施形態の電流出力型駆動回路は、テスト回路１０、制御回路２０、書き込み回路３０、基準電流源回路４０、フラグ用双方向シフトレジスタ５０、画像データ用レジスタアレイ６０、制御信号発生回路７０−１，７０−２、ＤＡＣ（電流出力型）８０−１，８０−２，…，８０−３，８０−４及び電流出力回路９０−１，９０−２，９０−３，９０−４により構成されている。
【０１０５】
テスト回路１０は、入力信号ＴＯＵＴ，ＴＭＯＤＥ及びＴＣＬＫに応じて、回路全体の動作をテストする。
制御回路２０は、方向制御信号ＤＩＲ、リセット信号ＲＥＳＥＴ、ロードパルスＬＯＡＤ、ラッチパルスＬＡＴＣＨ及びクロック信号ＭＣＬＫに応じて、書き込み回路３０、フラグ用双方向シフトレジスタ５０及び制御信号発生回路７０−１，７０−２にそれぞれ駆動クロック信号や制御信号を出力する。
書き込み回路３０は、制御回路２０からの駆動クロック信号や制御信号に基づき、入力されるｍビットの画像データＤ_ｉｎ０　，Ｄ_ｉｎ１　，…，Ｄ_{ｉｎｍ−１}　をラッチして、好適にはシリアル・パラレル変換により動作周波数を低くして、画像データ用レジスタアレイ６０に出力する。
【０１０６】
基準電流源回路４０は、例えば、ある１つのドライバＩＣ（電流出力型駆動回路）の基準電流発生回路の外部抵抗接続端子ＲＥＸＴとＧＮＤの間に抵抗を接続して、その抵抗値に応じて基準電流出力端子ＩＲＥＦＯＵＴにディスプレイパネル上のドライバＩＣに共通する基準電流を発生する。各ドライバＩＣは入力信号ＮＥＸＴＲＥＦの制御にしたがって基準電流入力端子ＩＲＥＦＩＮを通して基準電流をドライバＩＣ内部に取り込んで、必要な出力本数に増やされて、ＤＡＣ７０−１〜７０−４に出力する。
フラグ用双方向シフトレジスタ５０は、方向制御信号ＤＩＲや制御回路２０から入力される駆動クロック信号や制御信号にしたがって、シフトレジスタの両端からそれぞれ入力されるフラグ信号ＳＴＡＲＴ／ＮＥＸＴとＮＥＸＴ／ＳＴＡＲＴを左または右の何れかの方向にシフトし、シフトしたフラグ信号を画像データ用レジスタアレイ６０に供給して、書き込み回路３０から入力される画像データを書き込むレジスタアレイの位置（アドレス）を選択する。
画像データ用レジスタアレイ６０は、ダブルバッファ型のレジスタから構成されており、書き込み回路３０から入力される画像データを前段のレジスタで保持し、ＬＡＴＣＨ信号の入力に応じて保持した画像データを後段のレジスタに転送し、制御信号発生回路７０から入力されるチャネル選択信号に応じて、ＤＡＣ８０−１，８０−２，８０−３及び８０−４に順次出力する。
【０１０７】
ＤＡＣ８０−１，８０−２，８０−３及び８０−４は、電流出力型ディジタル／アナログ変換回路である。即ち、これらの変換回路は、画像データ用レジスタアレイ６０から順次入力される画像データに対応した電流信号を発生し、電流出力回路９０−１，９０−２，９０−３，９０−４に時分割で出力する。
電流出力回路９０−１，９０−２，９０−３，９０−４は、前述した本発明に係るカレントサンプリング回路及び高耐圧または中耐圧の電流出力トランジスタによって構成されている。これらの電流出力回路は、ＤＡＣ８０−１，８０−２，８０−３及び８０−４から入力される画像データに対応した変換電流をサンプリングして保持し、そして、保持した電流をＬＯＡＤ信号の入力に応じて複数の出力端子に出力する。
【０１０８】
本実施形態の電流出力型駆動回路は、外部から供給される制御信号に基づき、入力される画像データＤ_ｉｎ０　，Ｄ_ｉｎ１　，…，Ｄ_{ｉｎｍ−１}　を保持して、そして保持した画像データをチャネル選択信号に従って複数のＤＡＣ８０−１，８０−２，８０−３及び８０−４の何れかに出力する。
ＤＡＣ８０−１，８０−２，８０−３及び８０−４により、基準電流源回路４０から供給された基準電流及び入力される画像データに応じた電流が生成される。電流出力回路９０−１，９０−２，９０−３及び９０−４により、ＤＡＣ８０−１，８０−２，８０−３及び８０−４から供給された電流を保持して、そして保持した電流がＬＯＡＤ信号の入力に応じて複数の出力端子に出力される。
【０１０９】
図１５は、本実施形態の電流出力回路の一構成例を示す構成図である。
図示のように、電流出力回路９０は、それぞれ複数のカレントサンプリング回路からなる第１のバンク９１、第２のバンク９２及びディスプレイパネルを駆動するのに必要な電圧に足りる中耐圧または高耐圧の所定の耐圧を有する複数のトランジスタからなる電流出力トランジスタアレイ９３によって構成されている。
【０１１０】
図１５に示すように、第１のバンク９１と第２のバンク９２に、出力電流のチャネルの数だけそれぞれ複数のカレントサンプリング回路が配置されている。第１のバンク９１の各チャネルのカレントサンプリング回路は、第２のバンク９２のそれぞれのチャネルのカレントサンプリング回路に対応して配置されている。さらに、第１のバンク９１と第２のバンク９２の各チャネルのカレントサンプリング回路は、電流出力トランジスタアレイ９３の各チャネルの所定の耐圧を有するトランジスタに対応して配置されている。
【０１１１】
例えば、第１のバンク９１において、１チャネル目のカレントサンプリング回路９１−１と第２のバンク９２の１チャネル目のカレントサンプリング回路９２−１、並びに電流出力トランジスタアレイ９３における１チャネル目の所定の耐圧を有するトランジスタ９３−１に対応して配置されている。カレントサンプリング回路９１−１の電流出力端子ＩＯＵＴとカレントサンプリング回路９２−１の電流出力端子ＩＯＵＴが所定の耐圧を有するトランジスタ９３−１のソースに共通に接続されている。同様に、第１のバンク９１のｎチャネル目のカレントサンプリング回路９１−ｎと第２のバンク９２のｎチャネル目のカレントサンプリング回路９２−ｎ、並びに電流出力トランジスタアレイ９３におけるｎチャネル目の所定の耐圧を有するトランジスタ９３−ｎに対応して配置されている。カレントサンプリング回路９１−ｎの電流出力端子ＩＯＵＴとカレントサンプリング回路９２−ｎの電流出力端子ＩＯＵＴが所定の耐圧を有するトランジスタ９３−ｎのソースに共通に接続されている。電流出力トランジスタアレイ９３において、所定の耐圧を有するトランジスタ９３−１，９３−２，…，９３−ｎのドレインは、それぞれ出力パッド９４−１，９４−２，…，９４−ｎに接続されている。
【０１１２】
第１のバンク９１及び第２のバンク９２のすべてのカレントサンプリング回路の電流入力端子ＩＩＮは、図１５に示していない電流出力型ＤＡＣの電流出力端子に接続されている。第１のバンク９１のカレントサンプリング回路と第２のバンク９２のカレントサンプリング回路は、制御信号ＯＥ０、ＯＥ１に応じて交互に書き込みモードと、読み出しモードに制御される。これらのカレントサンプリング回路により、ＤＡＣの出力電流に応じた駆動電流を電流出力トランジスタ９３−１，９３−２，…，９３−ｎを介して負荷側に出力する。
【０１１３】
本実施形態の電流出力回路９０は、例えば、有機ＥＬ素子を駆動する場合、１０Ｖ〜２０Ｖ程度の電圧で、ＤＡＣの出力電流に応じた駆動電流を有機ＥＬ素子の供給する必要がある。このため、各出力チャネルごとに１個の中耐圧または高耐圧の所定の耐圧を有するトランジスタ９３−１〜９３−ｎを設けて、カレントサンプリング回路からの出力電流をパッド９４−１〜９４−ｎを介して、各チャネルの有機ＥＬ素子に出力することで高電圧に対応している。
【０１１４】
本実施形態のカレントサンプリング回路は、上述した本発明のカレントサンプリング回路の各実施形態及び実施例の回路に対応する。ここで、例えば、カレントサンプリング回路は、図５に示すカレントサンプリング回路の第３の実施形態によって構成される。
【０１１５】
本実施形態の各カレントサンプリング回路において、選択信号ＳＥＬと書き込みイネーブル信号ＷＥがアクティブ状態（例えば、ハイレベル）のとき、クロック信号ＣＫ１とＣＫ２により設定したタイミングでカレントサンプリング回路のキャパシタＣ１とＣ２にＤＡＣからの出力電流に応じたゲート電圧が取り込まれて、保持される。そして、読み出しイネーブル信号ＯＥがアクティブ状態（例えば、ハイレベル）のとき、キャパシタＣ１とＣ２に保持されているゲート電圧に応じた電流が出力される。このため、本実施形態の電流出力回路９０によって、各カレントサンプリング回路により、ＤＡＣの出力電流に基づき、高精度の駆動電流が各チャネルの有機ＥＬ素子に供給される。
【０１１６】
図１６は、本実施形態の電流出力型駆動回路の動作を示すタイミングチャートである。以下、図１５及び図１６を参照しつつ、本実施形態の動作について説明する。
図１５に示すように、第１のバンク９１と第２のバンク９２のカレントサンプリング回路は、交互にイネーブル信号ＯＥ０とＯＥ１により、書き込み動作と読み出し動作が制御される。即ち、第１のバンク９１の各カレントサンプリング回路の書き込みイネーブル信号ＷＥとして、イネーブル信号ＯＥ０が入力され、読み出しイネーブル信号ＯＥとして、イネーブル信号ＯＥ１が入力される。逆に、第２のバンク９２の各カレントサンプリング回路において、書き込みイネーブル信号ＷＥとして、イネーブル信号ＯＥ１が入力され、読み出しイネーブル信号ＯＥとして、イネーブル信号ＯＥ０が入力される。
【０１１７】
このため、第１のバンク９１のカレントサンプリング回路が書き込みのとき、第２のバンク９２のカレントサンプリング回路が電流を出力し、逆に、第２のバンク９２のカレントサンプリング回路が書き込みのとき、第１のバンク９１のカレントサンプリング回路が電流を出力する。即ち、第１のバンク９１のカレントサンプリング回路と第２のバンク９２のカレントサンプリング回路が交互に書き込みモードと読み出し（電流出力）モードに制御される。
【０１１８】
図１６に示すタイミングチャートに示すように、クロック信号ＣＫ１，ＣＫ２及びイネーブル信号ＯＥ０，ＯＥ１は、ラッチパルスＬＡＴＣＨに同期して生成される。なお、ラッチパルスＬＡＴＣＨは、システムによって生成され、制御信号発生回路７０−１，７０−２に供給される。これらの制御信号発生回路により、上述したクロック信号ＣＫ１，ＣＫ２、イネーブル信号ＯＥ０，ＯＥ１がそれぞれ生成され、電流出力回路９０に供給される。
【０１１９】
図示のように、ラッチパルスＬＡＴＣＨに同期して、クロック信号ＣＫ１，ＣＫ２及びイネーブル信号ＯＥ０，ＯＥ１が生成される。
ラッチパルスＬＡＴＣＨの各周期ごとに、イネーブル信号ＯＥ０とイネーブル信号ＯＥ１が交互にハイレベルとローレベルに保持される。
【０１２０】
イネーブル信号ＯＥ０がハイレベルのとき、第１のバンク９１のカレントサンプリング回路が書き込みを行う。このとき、第１のバンク９１のカレントサンプリング回路９１−１，９１−２，…，９１−ｎにおいて、クロック信号ＣＫ１とＣＫ２により設定したタイミングで、キャパシタＣ１とＣ２にトランジスタＭ１とＭ２のゲート電圧がそれぞれ印加され、保持される。
【０１２１】
次のラッチパルスＬＡＴＣＨの周期においてに、イネーブル信号ＯＥ０がローレベルに切り換わり、イネーブル信号ＯＥ１がハイレベルに切り換わる。このため、第２のバンク９２のカレントサンプリング回路が書き込みを行い、第１のバンク９１のカレントサンプリング回路が読み出し、即ち電流出力を行う。図１６のタイミングチャートに示すように、このとき、例えば、第１のバンク９１のカレントサンプリング回路９１−１の電流出力端子ＩＯＵＴから電流が出力される。
【０１２２】
上述したように、本実施形態の電流出力回路９０において、イネーブル信号ＯＥ０とＯＥ１に応じて、第１のバンク９１のカレントサンプリング回路と第２のバンク９２のカレントサンプリング回路が交互に書き込みモードと読み出しモードに制御され、書き込みモードのときカレントサンプリング回路はＤＡＣからの出力電流に応じて書き込みを行い、そして、読み出しモードのとき書き込みモード動作時に保持された電流を出力するので、ＤＡＣの出力電流に応じた電流を高精度で負荷側に供給する。
【０１２３】
図１７は、本実施形態の電流出力型駆動回路におけるレジスタアレイの一構成例を示す構成図である。なお、図１７に示す回路例は、図１４に示す本実施形態の電流出力型駆動回路におけるＤＡＣ１個分に対応するレジスタアレイの部分回路である。以下の説明では、便宜上この部分回路をレジスタアレイとし、符号６０を付して表記する。
【０１２４】
図示のように、レジスタアレイ６０を構成する単位セルは、例えば、トランスミッションゲートを持つＤ型ラッチ回路が２段接続したダブルバッファ型のラッチ回路６２−１，６２−２，…，６２−ｎ〜６３−１，６３−２，…，６３−ｎである。ラッチ回路は、ＤＡＣ１個の出力に接続するカレントサンプリング回路のチャンネル数ｎをワード数として、画像データのビット幅ｍをビット幅としたｎ×ｍのアレイを構成している。各ラッチ回路において、前段のラッチ回路のトランスミッションゲートは、フラグレジスタ５０−１，５０−２，…，５０−ｉの出力ＷＤ１，ＷＤ２，…，ＷＤｉによってオン／オフされる。
【０１２５】
本実施形態の電流出力型駆動回路において、例えば、スタートパルスＳＴＡＲＴがフラグレジスタ５０−１に入力される。また、画像データが書き込み回路を介して駆動回路内部のデータバスＤＸ０〜ＤＸｍ−１，ＤＹ０〜ＤＹｍ−１及びＤＺ０〜ＤＺｍ−１に出力される。スタートパルスがフラグレジスタ５０−１，５０−２，…，５０−ｉによって順次シフトされることにより、例えば、３チャネル分ずつ画像データが２段接続したダブルバッファ型のラッチ回路のうち、前段のラッチ回路に書き込まれる。
【０１２６】
画像データの書き込みが終わると、ラッチパルスＬＡＴＣＨの入力により、それぞれのダブルバッファ型のラッチ回路において、前段のラッチ回路に保持されている画像データが後段のラッチ回路に出力される。後段のラッチ回路の出力部分は選択回路になっていて、各選択回路の出力が共通のデータバス６６〜６７に接続されている。データバス６６〜６７がバッファ６４の入力側に接続されている。バッファ６４の出力端子がＤＡＣのデコーダの入力端子に接続されている。即ち、ダブルバッファ型のラッチ回路の出力がバッファ６４を介して、ＤＡＣのデコーダに入力される。
【０１２７】
ダブルバッファ型のラッチ回路６２−１，６２−２，…，６２−ｎ〜６３−１，６３−２，…，６３−ｎのうち、どのラッチ回路の出力がバッファ６４に出力されるかは、それぞれのダブルバッファ型ラッチ回路の後段の選択回路に入力される選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎによって制御される。図示のように、選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎがバッファ６５に入力され、バッファ６５によって保持された選択信号がそれぞれのダブルバッファ型ラッチ回路６２−１，６２−２，…，６２−ｎ〜６３−１，６３−２，…，６３−ｎに出力される。
【０１２８】
図１８は、本実施形態の電流出力型駆動回路を構成するレジスタアレイ６０、制御信号発生回路７０、ＤＡＣ８０及び電流出力回路９０を含む部分回路の構成を示すブロック図である。
本実施形態の電流出力型駆動回路において、時分割でレジスタアレイ６０からディジタルの画像データを読み出して、ＤＡＣ８０によって画像データに応じた電流が出力され、逐次電流出力回路９０に書き込むという一連の動作が行われる。制御信号発生回路７０は、この一連の動作を制御するための制御信号を発生し、電流出力型駆動回路の各構成部分に出力する。
【０１２９】
例えば、ＤＡＣ８０のデコーダの入力側には、ｎチャネル分のレジスタアレイ６２−１，６２−２，…，６２−ｎが選択回路及び出力バッファ６４を介して接続されている。ＤＡＣ８０の出力側には、ｎチャネル分の電流Ｉ_Ｏ１，Ｉ_Ｏ２，…，Ｉ_Ｏｎを出力する電流出力回路９０が接続されている。どのチャネルの画像データをレジスタアレイ６０から選択して、ＤＡＣ８０に出力するかは、制御信号発生回路７０によって生成した選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎによって制御される。選択されたチャネルの画像データがレジスタアレイ６０からＤＡＣ８０のデコーダに入力され、ＤＡＣ８０により電流出力に変換され、電流出力回路９０に書き込まれる。
【０１３０】
電流出力回路９０において、図示のように、第１のバンク９１のそれぞれのカレントサンプリング回路と第２のバンク９２のそれぞれのカレントサンプリング回路９２は、制御信号発生回路７０から入力される交互にハイレベルとローレベルで切り換わるイネーブル信号ＯＥ０とＯＥ１に応じて、書き込みモードと読み出しモードを繰り返し、ＤＡＣ８０から出力された電流を取り込み、さらに電流出力トランジスタを介して図示しない画像表示素子、例えば、有機ＥＬ素子に出力する。
【０１３１】
図１９は、図１８に示す本実施形態の電流出力型駆動回路の各構成部分の動作を示すタイミングチャートである。以下、図１８及び図１９を参照しつつ、この回路群の基本動作について説明する。
各動作周期において、ラッチパルスＬＡＴＣＨの入力により、制御信号発生回路７０がクリアされ、動作がスタートする。
【０１３２】
図１９に示すように、ラッチパルスＬＡＴＣＨに続いて、制御信号発生回路７０から選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎが順番に生成される。また、それぞれの選択信号とともに、各チャネルに供給されるクロック信号ＣＫ１１，ＣＫ１２，ＣＫ２１，ＣＫ２２，…，ＣＫ１ｎ，ＣＫ２ｎも順番に生成される。
【０１３３】
選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎがレジスタアレイ６０に供給され、これに応じてレジスタアレイ６０に保持されている各チャネルの画像データが順次読み出されてＤＡＣの８０のデコーダに入力される。
ＤＡＣ８０によって、入力される画像データが逐次電流出力に変換され、電流出力回路９０に出力される。電流出力回路９０において、第１のバンク９１と第２のバンク９２のうち、イネーブル信号ＯＥ０とＯＥ１により、一方が書き込みモードに制御され、他方が読み出しモードに制御される。ＤＡＣ８０から出力される電流が、チャネル選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎに応じて、書き込みモード側のバンクにある各カレントサンプリング回路に順番に書き込まれる。
【０１３４】
なお、カレントサンプリング回路には、チャネル選択信号と同時に、第１のスイッチ回路を先にオフさせるための第１のクロック信号群ＣＫ１１，ＣＫ１２，…，ＣＫ１ｎと、第１のスイッチ回路に遅れて第２のスイッチ回路をオフさせるための第２のクロック信号群ＣＫ２１，ＣＫ２２，…，ＣＫ２ｎが供給される。これらの選択信号は、チャネルごとに揃えないで、数種類の選択信号を組み合わせる形式で配線本数を減らしても良いし、また、クロック信号は、チャネルごとに揃えないで、２〜３組の信号を共用してもよい。
【０１３５】
図１９に示すように、外部からロードパルスＬＯＡＤが入力されると、書き込みモードと読み出しモードの切り換えを制御するＯＥ０とＯＥ１の信号が反転して、交互にローレベルとハイレベルで切り替わる。イネーブル信号ＯＥ０がローレベルでイネーブル信号ＯＥ１がハイレベルのときには、第１のバンク９１のカレントサンプリング回路が電流読み出しモードで動作し、電流の出力が行い、第２のバンク９２のカレントサンプリング回路が書き込みモードで動作し、ＤＡＣからの出力電流を取り込む。一方、イネーブル信号ＯＥ０がハイレベルでイネーブル信号ＯＥ１がローレベルのときは、第２のバンク９２のカレントサンプリング回路が読み出しモードで動作し、各カレントサンプリング回路からホールドした電流が出力され、第１のバンク９１のカレントサンプリング回路が書き込みモードで動作し、ＤＡＣからの出力電流を取り込む。
【０１３６】
第８の実施形態
図２０は、本発明に係る電流出力型駆動回路の第８の実施形態を示す構成図である。なお、本実施形態の電流出力型駆動回路は、電流出力回路を除いて、他の各部分は図１４に示す本発明の電流出力型駆動回路の実施形態とほぼ同じ構成を有する。図２０は、本実施形態における電流出力回路９０ａの構成を示している。以下の説明では、電流出力回路９０ａのみについて説明し、他の各構成部分については、上述した第７の実施形態の説明を参照されたい。
【０１３７】
図２０に示すように、本実施形態における電流出力回路９０ａは、第１のバンク９１、第２のバンク９２、電流出力トランジスタアレイ９３、及びダミーカレントサンプリング回路９４によって構成されている。このうち、ダミーカレントサンプリング回路９４は、本実施形態において新しく追加された部分であり、その他の各部分回路は、図１５に示した第７の実施形態の電流出力回路の対応する構成部分と同じである。
【０１３８】
図２０に示すように、ダミーカレントサンプリング回路９４において、電流入力端子ＩＩＮは、図示していないＤＡＣ８０の電流出力端子に接続されている。また、ダミーカレントサンプリング回路９４において、ダミー制御端子が設けられ、当該ダミー制御端子には、図示していない制御信号発生回路７０ａからのダミー選択信号ＤＵＭが入力される。
【０１３９】
図２１は、本実施形態の電流出力型駆動回路を構成するレジスタアレイ６０、制御信号発生回路７０ａ、ＤＡＣ８０及び電流出力回路９０ａを含む部分回路の構成を示すブロック図である。
なお、図２１に示す本実施形態の部分回路と図１８に示す本発明の第７の実施形態の部分回路との異なる点は、ＤＡＣ８０の電流出力端子にダミーカレントサンプリング回路９４が追加された点と、レジスタアレイ６０と電流出力回路９０におけるカレントサンプリング回路を選択するためのチャネル選択信号として、チャネル１とチャネルｎの選択信号がそれぞれＳＥＬＲ１，ＳＥＬＣ１とＳＥＬＲｎ，ＳＥＬＣｎが制御信号発生回路７０ａによって生成される点である。
【０１４０】
図２２は、図２１に示す本実施形態の電流出力型駆動回路の部分回路の動作を示すタイミングチャートである。以下、図２１及び図２２を参照しつつ、この部分回路の動作について説明する。
図２２に示すように、本実施形態において、ダミーサイクルが設けられている。ラッチパルスＬＡＴＣＨが入力されたあと、すぐにチャネル１のカレントサンプリング回路への書き込みが開始するのではなく、ダミーサイクルの間に、本当のチャネルへの電流の取り込みが行われず、ダミーカレントサンプリング回路９４に電流を流す。また、最後のチャネルへの電流の取り込みが終わったあとも、次のラッチパルスＬＡＴＣＨが入力されるまでレジスタアレイ６０側のチャネルが固定されている。
【０１４１】
本実施形態の電流出力型駆動回路において、ロードパルスＬＯＡＤ、ラッチパルスＬＡＴＣＨ及びスタートパルスＳＴＡＲＴが入力されるとき、駆動回路内部では多くの回路が同時に動作するので、回路間に互いに影響を及ぼすおそれがあり、これによってチャネル１のカレントサンプリング回路への電流の書き込みが入力される画像データに応じた本来の電流値からずれてしまうことがある。本実施形態において、ダミーサイクルを設けることにより、チャネル１の出力電流への影響を低減することができる。
【０１４２】
また、出力回路９０において、バンク切り換えが行われるあと、チャネル１にはすぐに電流の取り込みが行われ、チャネル２以降はすぐに行われない。このため、チャネル１のカレントサンプリング回路のトランジスタには、読み出し時のドレイン電圧が残り、チャネル２以降のカレントサンプリング回路のトランジスタでは、ドレイン電圧が電源電圧Ｖ_ＤＤに戻っている。この差により、チャネル１の書き込みのとき、カレントサンプリング回路に取り込まれた電流値が実際の電流値よりずれてしまう。
【０１４３】
この問題に対して、本実施形態ではダミーサイクルを設けて、まず、ラッチパルスＬＡＴＣＨが入力されたあと、制御信号発生回路７０ａにより、レジスタアレイ側のチャネル選択信号ＳＥＬＲ１がアクティブ状態（例えば、ハイレベル）に保持され、これを受けてレジスタアレイ６０において、チャネル１に対応する画像データが選択され、バッファ６４を介してＤＡＣ８０のデコーダに入力される。ＤＡＣ８０により、入力されるチャネル１の画像データに応じた電流が出力される。このとき、制御信号発生回路７０ａにより、ダミー選択信号ＤＵＭがアクティブ状態（ハイレベル）に保持されている。このため、ダミーカレントサンプリング回路９４が動作状態に制御され、ＤＡＣ８０から出力される変換電流がダミーカレントサンプリング回路９４により取り込まれる。
【０１４４】
次に、図２２に示すように、ダミー選択信号ＤＵＭが非アクティブ状態（ローレベル）に切り換えられ、これに伴って電流出力側の選択信号ＳＥＬＣ１がアクティブ状態（ハイレベル）に保持される。これに応じて、ダミーカレントサンプリング回路９４が非動作状態に制御される。このとき、電流出力回路９０ａにおいて、第１のバンクまたは第２のバンクのうち、イネーブル信号ＯＥ０とＯＥ１により選択されたバンクにおいて、チャネル１に対応するカレントサンプリング回路にＤＡＣ８０の出力電流が取り込まれる。
【０１４５】
制御信号発生回路７０ａにより、チャネルｎまでの各チャネルに対応する選択信号が順次生成され、レジスタアレイ６０及び電流出力回路９０ａに順次出力される。なお、チャネルｎにおいて、図２２に示すように、レジスタアレイ６０と電流出力回路９０ａのチャネル選択をそれぞれ制御する選択信号ＳＥＬＲｎとＳＥＬＣｎが生成される。
【０１４６】
レジスタアレイ６０において、選択信号ＳＥＬＲｎに応じて、ｎチャネル目の画像データが選択され、バッファ６４を介してＤＡＣ８０のデコーダに入力される。ＤＡＣ８０により、入力されるｎチャネル目の画像データに応じた電流が出力される。
一方、電流出力回路９０ａにおいて、選択信号ＳＥＬＣｎに応じて、チャネルｎに対応するカレントサンプリング回路が動作状態に制御され、ＤＡＣ８０から出力される電流が当該カレントサンプリング回路に取り込まれて、保持される。
【０１４７】
図２２に示すように、レジスタアレイ６０に出力される選択信号ＳＥＬＲｎは、次のラッチパルスＬＡＴＣＨが入力されるまでアクティブ状態（ハイレベル）に保持される。選択信号ＳＥＬＲｎがハイレベルに保持されている間、レジスタアレイ６０により、ｎチャネル目の画像データがＤＡＣ８０のデコーダに出力される。このため、ＤＡＣ８０において、最後に出力されるｎチャネル目の画像データに対応する電流が継続して出力される。
【０１４８】
制御信号発生回路７０ａにおいて、ｎチャネル値の選択信号ＳＥＬＣｎが非アクティブ状態（ローレベル）に切り換えたあと、ダミー選択信号ＤＵＭがアクティブ状態に保持される。このため、ＤＡＣ８０から出力されるｎチャネル目の画像データに応じた電流が電流出力回路９０ａのダミーカレントサンプリング回路９４に供給される。
【０１４９】
次のラッチパルスＬＡＴＣＨが入力されると、制御信号発生回路７０ａにより、ｎチャネル目の選択信号ＳＥＬＲｎが非アクティブ状態に切り換えられ、１チャネル目の選択信号ＳＥＬＲ１がアクティブ状態に切り換えられる。このため、レジスタアレイ６０において、チャネル１の画像データが選択され、ＤＡＣ８０のデコーダに出力される。ＤＡＣ８０により、入力されるチャネル１の画像データに応じた電流が出力される。なお、このとき、ダミー選択信号ＤＵＭがアクティブ状態に保持されたままなので、電流出力回路９０ａにおいて、ＤＡＣ８０からの出力電流がダミーカレントサンプリング回路９４に出力される。
【０１５０】
上述したように、本実施形態の電流出力型駆動回路において、ロードパルスＬＯＡＤ、ラッチパルスＬＡＴＣＨなどが入力されるとき、制御信号発生回路７０ａにより、ダミー選択信号ＤＵＭがアクティブ状態に保持される。これに応じて、電流出力回路９０ａにおいて、ＤＡＣ８０から出力される電流がダミーカレントサンプリング回路９４に出力される。このため、ロードパルスＬＯＡＤ、ラッチパルスＬＡＴＣＨなどが入力され、ＤＡＣ８０の出力電流に誤差が生じるおそれがあるとき、ＤＡＣ８０の出力をカレントサンプリング回路に取り込むことなく、ダミーカレントサンプリング回路に出力することで、負荷側に出力される電流の精度を改善できる。
【０１５１】
第９の実施形態
図２３は、本発明に係る電流出力型駆動回路の第９の実施形態を示す構成図である。なお、本実施形態の電流出力型駆動回路は、電流出力回路の部分を除いて、他の各部分は図１４に示す本発明の電流出力型駆動回路の実施形態とほぼ同じ構成を有する。図２３は、本実施形態における電流出力回路９０ｂの構成を示している。以下の説明では、本実施形態における電流出力回路９０ｂのみについて説明し、他の各構成部分については、上述した本発明の第７の実施形態の説明を参照されたい。
【０１５２】
図２３に示すように、本実施形態における電流出力回路９０ｂは、第１のバンク９１、第２のバンク９２、電流出力トランジスタアレイ９３、及び電流切り換えトランジスタ９５−１，９５−２によって構成されている。このうち、電流切り換えトランジスタ９５−１，９５−２は、本実施形態において新しく追加された部分であり、その他の各部分回路は、図１５に示した第７の実施形態の電流出力回路の対応する構成部分と同じである。
【０１５３】
図２３に示すように、電流切り換えトランジスタ９５−１は、ＤＡＣ８０の電流出力端子と第１のバンク９１の各カレントサンプリング回路の入力端子との間に接続されている。トランジスタ９５−１のゲートに、イネーブル信号ＯＥ０が印加される。一方、電流切り換えトランジスタ９５−２は、ＤＡＣ８０の電流出力端子と第２のバンク９２の各カレントサンプリング回路の入力端子との間に接続されている。トランジスタ９５−２のゲートに、イネーブル信号ＯＥ１が印加される。
【０１５４】
上述した構成を有する本実施形態の電流出力回路９０ｂにおいて、電流切り換えトランジスタ９５−１と９５−２は、イネーブル信号ＯＥ０，ＯＥ１に応じてオン／オフするスイッチとして動作する。例えば、イネーブル信号ＯＥ０のハイレベルのとき、電流切り換えスイッチ９５−１がオンする。このとき、第１のバンク９１が動作モードに制御されるので、ＤＡＣ８０により出力される電流が電流切り換えトランジスタ９５−１を介して、第１のバンク９１に供給される。第１のバンク９１において、選択信号ＳＥＬ１〜ＳＥＬｎに応じて、チャネル１〜チャネルｎに対応するカレントサンプリング回路が順次動作し、ＤＡＣ８０の出力電流をそれぞれのカレントサンプリング回路により取り込まれる。
【０１５５】
次に、イネーブル信号ＯＥ１がハイレベルにあるとき、電流切り換えトランジスタ９５−２がオンする。一方、このとき、イネーブル信号ＯＥ０がローレベルに保持されているので、電流切り換えトランジスタ９５−１がオフする。このとき、第２のバンク９２が動作モードに制御されるので、ＤＡＣ８０により出力される電流が電流切り換えトランジスタ９５−２を介して、第２のバンク９２に供給される。第２のバンク９２において、選択信号ＳＥＬ１〜ＳＥＬｎに応じて、チャネル１〜チャネルｎに対応するカレントサンプリング回路が順次動作し、ＤＡＣ８０の出力電流をそれぞれのカレントサンプリング回路により取り込まれる。
【０１５６】
上述したように、本実施形態における電流出力回路９０ｂにおいて、ＤＡＣ８０の電流出力端子と第１のバンク９１の間に電流切り換えトランジスタ９５−１が設けられ、ＤＡＣ８０の電流出力端子と第２のバンク９２の間に電流切り換えトランジスタ９５−２が設けられている。電流切り換えトランジスタ９５−１と９５−２は、イネーブル信号ＯＥ０とＯＥ１によりオン／オフが制御される。第１のバンク９１が動作モードにあるとき、電流切り換えトランジスタ９５−１がオン状態に制御され、ＤＡＣ８０の出力電流が第１のバンク９１のカレントサンプリング回路に供給され、第２のバンク９２が動作モードにあるとき、電流切り換えトランジスタ９５−２がオン状態に制御され、ＤＡＣ８０の出力電流が第２のバンク９２のカレントサンプリング回路に供給される。ＤＡＣ８０の電流出力側に電流切り換えトランジスタ９５−１と９５−２を設けることにより、ＤＡＣの出力側からみえる負荷容量が低減し、書き込みに必要な時間が短縮するので、より多くのチャネルを接続することが可能となる。
また、ＤＡＣ８０の出力電流を分岐させるには、チャネルの選択を複数の選択信号の論理積（ＡＮＤ）をとる形にして、イネーブル信号ＯＥ０やＯＥ１ではなく、その一部のチャネル選択信号で分岐させてもよい。
【０１５７】
第１０の実施形態
図２４は、本発明に係る電流出力型駆動回路の第１０の実施形態を示す構成図である。なお、本実施形態の電流出力型駆動回路は、電流出力回路の部分を除いて、他の各部分は図１４に示す本発明の電流出力型駆動回路の実施形態とほぼ同じ構成を有する。図２４は、本実施形態における電流出力回路９０ｃの構成のみを示している。以下の説明では、本実施形態における電流出力回路９０ｃのみについて説明し、他の各構成部分について省略する。
【０１５８】
図２４に示すように、本実施形態における電流出力回路９０ｃは、第１のバンク９１、第２のバンク９２、電流出力トランジスタアレイ９３、及びカレントミラー回路９６によって構成されている。このうち、カレントミラー回路９６は、本実施形態において新しく追加された部分であり、その他の各部分回路は、図１５に示した第７の実施形態の電流出力回路の対応する構成部分と同じである。
【０１５９】
本実施形態における電流出力回路９０ｃは、図２３に示した本発明の第９の実施形態における電流出力回路９０ｂと異なる点は、本実施形態の電流出力回路９０ｃにおいてＤＡＣの出力電流を電流切り換えトランジスタではなく、カレントミラー回路９６を用いて折り返して、第１のバンク９１及び第２のバンク９２の各カレントサンプリング回路に供給する点である。
【０１６０】
図２４に示すように、本実施形態の電流出力回路９０ｃにおいて、抵抗素子９６−１，９６−２，９６−３及びトランジスタ９６−４，９６−５，９６−６により、カレントミラー回路９６が構成されている。トランジスタ９６−４，９６−５，９６−６のゲートが共通に接続され、さらに、トランジスタ９６−４のソースに接続されている。トランジスタ９６−４，９６−５，９６−６のドレインと電源電圧Ｖ_ＤＤとの間に、それぞれ抵抗素子９６−１，９６−２，９６−３が接続されている。トランジスタ９６−４のソースに、図示していないＤＡＣ８０により、画像データに応じた変換電流が出力される。
【０１６１】
上述したカレントミラー回路９６において、ＤＡＣ８０の出力電流がそれぞれトランジスタ９６−５及び９６−６のソースに折り返される。即ち、トランジスタ９６−５と９６−６のソースから、ＤＡＣ８０の出力電流に応じた電流が出力される。トランジスタ９６−５の出力電流が第１のバンク９１の各チャネルのカレントサンプリング回路に供給され、トランジスタ９６−６の出力電流が第２のバンク９２の各チャネルのカレントサンプリング回路に供給される。
【０１６２】
上述したように、本実施形態の電流出力回路９０ｃにおいて、カレントミラー回路９６を用いてＤＡＣ８０の出力電流を第１のバンク９１と第２のバンク９２のカレントサンプリング回路に折り返して供給する。カレントミラー回路の出力ラインを複数設けることにより、ラインごとの負荷容量が低減し、カレントサンプリング回路への書き込みに必要な時間が短縮するので、より多くのチャネルを接続することが可能になる。実施例においてカレントミラー回路は抵抗素子とＭＯＳトランジスタで構成されたものを示したが、バイアス電圧が印加されるカスコード型など他の形態のカレントミラー回路でも構わないし、ＭＯＳトランジスタの代わりにバイポーラトランジスタを用いたものでも良い。好適には、ＤＡＣの出力負荷を低減して高速化するために、ＭＯＳトランジスタやバイポーラトランジスタをダイオード接続しないで、ソースフォロワ回路を介してゲート電圧やベース電圧を発生するものでも良い。
【０１６３】
第１１の実施形態
図２５は、本発明に係る電流出力型駆動回路の第１１の実施形態を示す構成図である。
図２５は、本発明の電流出力型駆動回路において、レジスタアレイ６０−１，６０−２、制御信号発生回路７０、ＤＡＣ８０−１，８０−２及び電流出力回路９０−１，９０−２を含む部分回路の構成を示している。
【０１６４】
本実施形態の部分回路において、制御信号発生回路７０は、隣り合った２つのグループのレジスタアレイ６０−１，６０−２、ＤＡＣ８０−１，８０−２及び電流出力回路９０−１，９０−２の制御を行う。即ち、制御信号発生回路７０は、チャネル選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎ、クロック信号ＣＫ１，ＣＫ２、イネーブル信号ＯＥ０，ＯＥ１などの制御信号を生成し、それぞれ２つのグループのレジスタアレイ、ＤＡＣ及び電流出力回路に出力する。
【０１６５】
本実施形態の部分回路に示すように、制御信号発生回路は、隣り合った２つのグループのレジスタアレイ、ＤＡＣ及び電流出力回路によって共有することにより、回路のレイアウト面積の低減を実現できる。また、制御信号発生回路自体が発生するディジタルノイズもいくらか低減できる。
【０１６６】
第１２の実施形態
図２６〜２８は、本発明に係る電流出力型駆動回路の第１２の実施形態を示す図である。
図２６は、電流出力型駆動回路の一構成部分である分周回路１００の構成を示す回路図であり、図２７は、図２６に示す分周回路の分周出力に応じて、チャネル選択信号、イネーブル信号ＯＥ０，ＯＥ１及びクロック信号ＣＫ１，ＣＫ２を生成する制御信号発生回路７０を示すブロック図である。さらに、図２８は、制御信号発生回路７０によって出力される制御信号の波形を示す波形図である。
【０１６７】
図２６に示すように、分周回路１００は、２分周器１０２，１０４、クロックイネーブル回路１０６、プログラマブル分周器１０８、及びｎ回カウンタ１１０によって構成されている。
分周回路１００には、図示のように、ロードパルスＬＯＡＤ、リセット信号ＲＥＳＥＴ、ラッチパルスＬＡＴＣＨ、基本クロック信号ＭＣＬＫ、分周比制御データＤＩＶ、半分周制御信号ＨＡＬＦが入力される。
【０１６８】
２分周器１０２は、ロードパルスＬＯＡＤを２分周し、分周信号をイネーブルクロック信号ＯＥＣＬＫとして出力する。
クロックイネーブル回路１０６は、ラッチパルスＬＡＴＣＨ及びｎ回カウンタ１１０の出力信号に応じて、カウンタクリア信号ＣＮＴＣＬＲを出力する。
なお、２分周器１０２及びクロックイネーブル回路１０６は、リセット信号ＲＥＳＥＴによりリセットされる。
【０１６９】
２分周器１０４は、基本クロックＭＣＬＫを２分周器、分周信号をプログラマブル分周器１０８に出力する。
プログラマブル分周器１０８は、分周器比制御データＤＩＶ及び半分周制御信号ＨＡＬＦに基づき、２分周器１０４から入力される分周クロック信号を所望の分周比で分周し、カウンタクロック信号ＣＮＴＣＬＫを出力する。
図２６に示すように、分周器比制御データＤＩＶは、ｉビットのデータＤＩＶ０，…，ＤＩＶｉ−１であり、プログラマブル分周器１０８の分周比を制御する。本実施例では細かい設定を可能にするため０．５分周ごとに設定可能なプログラマブル分周器としているが、通常の１分周ごとに設定可能なプログラマブル分周器でもかまわないし、最初の２分周器がない形態でも構わない。
【０１７０】
ｎ回カウンタ１１０は、プログラマブル分周器１０８から入力されるカウンタクロック信号ＣＮＴＣＬＫをカウントし、所定のカウント数ｎに達したことを示すフラグ信号をクロックイネーブル回路１０６に出力する。
図２６に示すように、２分周器１０４、プログラマブル分周器１０８及びｎ回カウンタ１１０は、クロックイネーブル回路１０６から出力されるカウンタクリア信号ＣＮＴＣＬＲにより、クリアされる。
【０１７１】
上述した構成を有する分周回路１００において、外部から入力されるロードパルスＬＯＡＤ、リセット信号ＲＥＳＥＴ、ラッチパルスＬＡＴＣＨ、基本クロック信号ＭＣＬＫに応じて、イネーブルクロックＯＥＣＬＫ、カウンタクリア信号ＣＮＴＣＬＲ及びカウンタクロック信号ＣＮＴＣＬＫを生成し、制御信号発生回路７０に供給する。そして、制御信号発生回路７０は、分周回路１００から入力される信号に応じて、レジスタアレイ、ＤＡＣ及び電流出力回路を制御するためのチャネル選択信号、出力イネーブル信号、クロック信号などを生成する。
【０１７２】
図２７は、制御信号発生回路７０の入力信号及び出力信号を示すブロック図である。図示のように、制御信号発生回路７０には、図２６に示す分周回路によって生成されるイネーブルクロックＯＥＣＬＫ、カウンタクリア信号ＣＮＴＣＬＲ及びカウンタクロック信号ＣＮＴＣＬＫが入力される。
【０１７３】
図２７に示すように、制御信号発生回路７０により、チャネル選択信号ＳＥＬ１〜ＳＥＬｎ、イネーブル信号ＯＥ０，ＯＥ１、クロック信号ＣＫ１，ＣＫ２がそれぞれ生成される。
【０１７４】
図２８は、本実施形態の分周回路１００及び制御信号発生回路７０の入力信号及び出力信号の一部分を示す波形図である。
図示のように、分周回路１００によって、ラッチパルスＬＡＴＣＨ及び基本クロック信号ＭＣＬＫに応じて、カウンタクロック信号ＣＮＴＣＬＫが生成される。カウンタクロック信号ＣＮＴＣＬＫが、図示しないイネーブルクロック信号ＯＥＣＬＫ、カウンタクリア信号ＣＮＴＣＬＲとともに、制御信号発生回路７０に出力される。制御信号発生回路７０により、チャネル選択信号ＳＥＬ１，ＳＥＬ２，…，ＳＥＬｎが生成される。図示のように、チャネル選択信号ＳＥＬ１〜ＳＥＬｎは、カウンタクロック信号ＣＮＴＣＬＫの各周期ごとに順次出力される。即ち、チャネルの選択信号ＳＥＬ１〜ＳＥＬｎのパルス間隔は、分周回路１００によって供給されるカウンタクロック信号ＣＮＴＣＬＫの周期によって決まる。このため、分周回路１００において、カウンタクロック信号ＣＮＴＣＬＫの周期を制御することにより、チャネル選択信号ＳＥＬ１〜ＳＥＬｎのパルス幅（サンプリング時間）を制御することができる。
【０１７５】
本実施形態の分周回路１００を用いることにより、生成されるプログラマブル分周器１０８に入力される分周比制御データＤＩＶを適宜設定することにより、プログラマブル分周器１０８から出力されるカウンタクロック信号ＣＮＴＣＬＫの周波数（周期）を制御し、サンプリング時間を制御することができる。
【０１７６】
電流出力型駆動回路によって駆動されるディスプレイパネルの画素数によって、１チャネルあたりに割り当てられるカレントサンプリング回路の書き込み時間が変わる。このため、駆動対象のディスプレイパネルの画素数に応じて、チャネル選択信号ＳＥＬ１〜ＳＥＬｎのサンプリング時間を制御する必要がある。本実施形態において、分周器１００にプログラマブル分周器１０８が設けられているので、ディスプレイパネルの画素数に応じて、適宜設定した分周比制御データＤＩＶをプログラマブル分周器１０８に入力することにより、出力されるカウンタクロック信号ＣＮＴＣＬＫの周期を制御できる。このため、制御信号発生回路７０により、カウンタクロック信号ＣＮＴＣＬＫに応じて生成される選択信号ＳＥＬ１〜ＳＥＬｎは、所望の画素数に最適なサンプリング時間を持つようになる。
【０１７７】
このように、本実施形態の分周回路１００を用いることにより、駆動対象となるディスプレイパネルの画素数に容易に対応することができ、電流出力側駆動回路の設計を容易にできる。
【０１７８】
第１３の実施形態
図２９は、本発明に係る電流出力型駆動回路の第１３の実施形態を示す図である。
図２９は、本発明の電流出力型駆動回路の電流出力回路を構成するカレントサンプリング回路の書き込み電流の入力ラインのシールド例を示す。
【０１７９】
カレントサンプリング回路の電流入力ラインは、図示しないＤＡＣ８０の電流出力ラインに接続されている。この入力ラインにより、ＤＡＣ８０の出力電流が第１のバンク９１及び第２のバンク９２の各カレントサンプリング回路に入力される。
入力ラインとディジタル信号配線の間にわずか数ｆＦのカップリング容量が存在するとしても、ディジタル信号配線の電圧変動により、電流入力ラインに数十ｍＶのクロストークが発生する。数５に示したようにカレントサンプリング回路の実効的なホールド電圧Ｖ_ｅｆｆ１やＶ_ｅｆｆ２は、数百ｍＶというかなり小さな電圧をとる。このため、数十ｍＶのクロストークといえども、カレントサンプリング回路のホールド電圧に大きな影響を与えることがある。
【０１８０】
本実施形態の電流出力型駆動回路において、電流出力回路の各カレントサンプリング回路のレイアウト領域において、電流入力ラインがディジタル信号配線、または出力ラインと交差する箇所、または並走する箇所に、電源電圧Ｖ_ＤＤにバイアスされる配線層でシールドする。
なお、本実施形態において、カレントサンプリング回路は、電源電圧Ｖ_ＤＤを基準にトランジスタのドレイン−ゲート間電圧をホールドし、ＤＡＣの出力電流の書き込みを行うので、電流入力ラインを電源電圧Ｖ_ＤＤにバイアスした導電層でシールドする。カレントサンプリング回路が、例えば、ＧＮＤ電位Ｖ_ＳＳを基準に電圧をホールドし、ＤＡＣの出力電流の書き込みを行う場合、電流入力ラインのシールド配線層をＧＮＤ電位Ｖ_ＳＳにバイアスする。
【０１８１】
本実施形態によれば、電流出力回路の各カレントサンプリング回路の電流入力ラインとディジタル信号配線の交差する箇所、または電流入力ラインと出力ラインの交差する箇所、あるいはこれらの信号線が並走する箇所に、電源電圧Ｖ_ＤＤまたＧＮＤ電位Ｖ_ＳＳにバイアスされた導電層でシールドすることにより、信号線の間の寄生容量によるカップリングを防止でき、クロストークによるカレントサンプリング回路のホールド電圧に与える影響を低減でき、電流書き込みの精度を改善できる。
【０１８２】
第１４の実施形態
図３０は、本発明に係る電流出力型駆動回路の第１４の実施形態を示す図である。
図３０は、本発明の電流出力型駆動回路の電流出力回路を構成するカレントサンプリング回路の書き込み電流の入力ラインの他のシールド例を示す。
【０１８３】
上述した第１３の実施形態において、カレントサンプリング回路の電流入力ラインと他のディジタル信号配線または出力ラインとの交差する箇所に、電源電圧Ｖ_ＤＤまたはＧＮＤ電位Ｖ_ＳＳにバイアスされた導電層でシールドを行っている。本実施形態では、この導電層をさらに立体的な構造にし、シールド効果の向上をはかる。
【０１８４】
本実施形態の電流出力型駆動回路を構成するカレントサンプリング回路において、トランジスタのしきい値電圧を差し引いた実行的なホールド電圧は、数百ｍＶであるので、電圧をホールドする容量素子の近くにディジタル信号線が配線されていると、クロストークが発生し、容量素子がホールドする電圧に影響を与えてしまうことがある。
【０１８５】
本実施形態において、図３０（ａ）〜（ｄ）に示すように、ホールドノード側の電極を、導電層及び当該導電層に接続された側壁によって構成された立体的なシールドで囲む。この導電層及び側壁が所定の電位にバイアスされる。なお、シールドを構成する導電層は、例えば、図示のように金属配線層から構成される。
【０１８６】
以上説明したように、本実施形態の電流出力型駆動回路によれば、カレントサンプリング回路において、トランジスタのゲート電圧をホールドする容量素子の電極を導電層及び側壁からなる立体的なシールドで囲み、導電層が所定の電圧にバイアスされる。このため、シールドの効果が向上し、容量素子とその近くにあるディジタル配線との間のクロストークによる影響を低減でき、カレントサンプリング回路のホールド電圧の精度が向上する。また、電流書き込み時に電源配線やＧＮＤ配線に流れる電流量と電流読み出し時に電源配線やＧＮＤ配線に流れる電流量が変化して各々のカレントサンプリング回路における電源電圧やＧＮＤ電圧が変動したとしても、ホールド電圧にその変動分が正しく加算されるのでＶＧＳが保持される。よって電流書き込みと読み出しの精度を改善でき、カレントサンプリング回路によって出力される駆動電流の高精度化を実現できる。
【０１８７】
【発明の効果】
以上説明したように、本発明によれば、十分な電流出力精度を有する電流サンプリング（カレントサンプリング）回路を用いて、カレントサンプリング回路に時分割で電流書き込みを制御する制御信号発生回路を設けて、さらに電流出力型のＤ／Ａ変換回路の出力電流を時分割で複数のカレントサンプリング回路に書き込む方式をとることで、Ｄ／Ａ変換回路の個数を低減し、多ビットのＤＡＣをレイアウトすることが可能となる。
また、本発明によれば、半導体チップ内の基準電流の分配が簡素化し、電流出力精度を低下させる要素を減らすことができ、高い階調の有機ＥＬディスプレイパネルに適した電流出力型駆動回路を実現できる利点がある。
【図面の簡単な説明】
【図１】本発明に係るカレントサンプリング回路の第１の実施形態を示す回路図である。
【図２】第１の実施形態のカレントサンプリング回路の動作を示すタイミングチャートである。
【図３】本発明に係るカレントサンプリング回路の第２の実施形態を示す回路図である。
【図４】第２の実施形態のカレントサンプリング回路の動作を示すタイミングチャートである。
【図５】本発明に係るカレントサンプリング回路の第３の実施形態を示す回路図である。
【図６】本発明に係るカレントサンプリング回路の第４の実施形態の一実施例を示す回路図である。
【図７】本発明に係るカレントサンプリング回路の第４の実施形態の他の実施例を示す回路図である。
【図８】本発明に係るカレントサンプリング回路の第４の実施形態の他の実施例を示す回路図である。
【図９】本発明に係るカレントサンプリング回路の第５の実施形態の一実施例を示す回路図である。
【図１０】本発明に係るカレントサンプリング回路の第５の実施形態の他の実施例を示す回路図である。
【図１１】本発明に係るカレントサンプリング回路の第６の実施形態の一実施例を示す回路図である。
【図１２】本発明に係るカレントサンプリング回路の第６の実施形態の他の実施例を示す回路図である。
【図１３】図１２に示すカレントサンプリング回路の動作を示すタイミングチャートである。
【図１４】本発明に係る電流出力型駆動回路の一実施形態を示す構成図である。
【図１５】本発明の電流出力型駆動回路を構成する電流出力回路の一構成例を示す回路図である。
【図１６】本実施形態の電流出力型駆動回路の動作を示すタイミングチャートである。
【図１７】本発明の電流出力型駆動回路を構成するレジスタアレイの一構成例を示す回路図である。
【図１８】本実施形態の電流出力型駆動回路を構成するレジスタアレイ、制御信号発生回路、ＤＡＣ及び電流出力回路を含む部分回路の構成を示すブロック図である。
【図１９】本実施形態の電流出力型駆動回路の部分回路の動作を示すタイミングチャートである。
【図２０】本発明に係る電流出力型駆動回路の他の実施形態を示す回路図である。
【図２１】本実施形態の電流出力型駆動回路を構成するレジスタアレイ、制御信号発生回路、ＤＡＣ及び電流出力回路を含む部分回路を示すブロック図である。
【図２２】本実施形態の電流出力型駆動回路を構成する部分回路の動作を示すタイミングチャートである。
【図２３】本発明に係る電流出力型駆動回路の他の実施形態を示す構成図である。
【図２４】本発明に係る電流出力型駆動回路の他の実施形態を示す構成図である。
【図２５】本発明に係る電流出力型駆動回路の他の実施形態を示す構成図である。
【図２６】本発明に係る電流出力型駆動回路のさらに他の実施形態を示す構成図であり、分周回路を含む部分回路の構成を示すブロック図である。
【図２７】本発明に係る電流出力型駆動回路において、制御信号発生回路とその入力信号と出力信号を示すブロック図である。
【図２８】本発明に係る電流出力型駆動回路における分周回路及び制御信号発生回路の入力信号と出力信号の一部分を示す波形図である。
【図２９】本発明の電流出力型駆動回路の電流出力回路を構成するカレントサンプリング回路の書き込み電流の入力ラインのシールド例を示す図である。
【図３０】本発明の電流出力型駆動回路の電流出力回路を構成するカレントサンプリング回路の書き込み電流の入力ラインの他のシールド例を示す図である。
【図３１】従来の電圧−電流変換回路を用いた電流出力型駆動回路の一構成例を示す回路図である。
【図３２】電圧−電流変換回路を用いた電流出力型駆動回路の一例を示す構成図である。
【図３３】カレントミラー回路と電流出力型ＤＡＣを組み合わせた電流出力回路の一構成例を示す回路図である。
【図３４】図３３に示す電流出力回路を複数用いた電流出力型駆動回路の構成を示すブロック図である。
【図３５】従来のカレントサンプリング回路の一構成例を示す回路図である。
【図３６】図３５に示すカレントサンプリング回路の基本動作を示すタイミングチャートである。
【符号の説明】
１０…テスト回路、２０…制御回路、３０…書き込み回路、４０…基準電流源回路、５０…フラグ用双方向シフトレジスタ、６０…画像データ用レジスタアレイ、７０…制御信号発生回路、８０…Ｄ／Ａ変換回路（ＤＡＣ）、９０…電流出力回路、９１…第１のバンク、９２…第２のバンク、９３…電流出力トランジスタアレイ、Ｖ_ＤＤ…電源電圧、Ｖ_ＳＳ…基準電位。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a current sampling circuit used in a drive circuit of a display device, for example, an organic EL display, and a current output type drive circuit using the same.
[0002]
[Prior art]
Thin display panels such as liquid crystal displays and PDPs (plasma display panels) have been commercialized. In recent years, however, since the elements themselves emit light, they have a bright contrast, a wide viewing angle, good responsiveness, and no need for a backlight. An organic EL display which is suitable for thinning is attracting attention. Organic EL displays have problems such as uneven brightness and difficulty in increasing the size of organic light-emitting elements, and are likely to cause deterioration of organic substances in the luminous body, making it difficult to produce bright red. Recently, prototype panels have been announced for the size of 13 to 15 inches due to advances in materials, manufacturing technology, and drive circuits.
[0003]
The organic EL element has a curvilinear current-voltage characteristic like a diode, and the luminance-current characteristic has a linear proportional relationship. As described above, the threshold voltage is present in the organic EL element and the TFT transistor, and the variation is large. For this reason, it has been proposed that in an organic EL display panel, a current control drive circuit having a proportional relationship with luminance is used instead of a voltage control drive circuit such as a liquid crystal display to reduce luminance unevenness of the display panel. ing.
[0004]
Liquid crystal panels for applications such as personal computers and TVs require multi-bit gradation display. Since it is difficult to create a complex circuit such as a DAC using only the low-temperature polysilicon TFT circuit formed on the panel, a voltage output driver IC that drives the vertical data lines is bonded to the periphery of the panel. It is being modularized. For this reason, a current output type driving circuit suitable for driving an organic EL element is desired also in an organic EL display panel.
[0005]
FIG. 31 illustrates a configuration example of a voltage-current conversion circuit. Here, the voltage-current conversion circuit outputs a current corresponding to the input voltage to a load side (for example, an organic EL element). As shown in FIG. 31, the voltage-current conversion circuit includes an operational amplifier OPA1, a resistor R1, and a transistor Q1. The input voltage V is applied to the positive input terminal of the operational amplifier OPA1._inIs applied, the base of the transistor Q1 is connected to the output terminal of the operational amplifier OPA1, and the emitter is connected to the power supply voltage V_DDIt is connected to the. The negative input terminal of the operational amplifier OPA1 is connected to the emitter of the transistor Q1.
[0006]
In the voltage-current conversion circuit configured as described above, the voltage at the connection point between the resistance element R1 and the transistor Q1 is equal to the input voltage V_inIs controlled to be equal to_DDAnd input voltage V_inAnd the current I according to the resistance value of the resistance element R1._outIs output.
In this voltage-current conversion circuit, in order to reduce the conversion error, it is necessary to reduce the variation in the resistance value of the resistance element R1, the offset voltage of the operational amplifier OPA1, and the variation in the threshold voltage of the transistor Q1.
[0007]
FIG. 32 shows an example of a current output type driving circuit using the voltage-current conversion circuit shown in FIG. 31 described above. As shown, in this drive circuit, a plurality of drive currents are output according to a plurality of input voltages by using a plurality of voltage-current conversion circuits shown in FIG. In order to form a plurality of voltage-current conversion circuits on a chip, for example, if the size of the chip in the longitudinal direction is about 20 mm (millimeter) that can be exposed by a normal semiconductor manufacturing apparatus, the number of pins for current output is 200 In the case of about pins, the interval between the pads for current output is about 75 μm (micrometer) or less. It is difficult to arrange the operational amplifiers in such a narrow pitch, and even if two pitches are used, it is difficult to perform a layout with a task for reducing the offset voltage. In addition, since the chip size is large, variations in the resistance elements dispersedly arranged from one end of the chip to the other end may occur by about several percent.
[0008]
Next, a current output type driving circuit using a current output type DAC (D / A converter) will be described. Current, unlike voltage, cannot be shared directly by multiple circuits. That is, the DAC circuit cannot be simplified by providing and sharing a plurality of reference voltages by resistance voltage division like a voltage output type DAC. Therefore, the circuit configuration is a combination of a current mirror circuit having a plurality of outputs and a current output type DAC as shown in FIG.
[0009]
FIG. 34 illustrates an example of a current output type driving circuit in which the current mirror circuit and the DAC illustrated in FIG. 33 are combined. As shown in the figure, a current mirror circuit, a current mirror circuit for current folding and a plurality of current output type DACs are arranged on the chip. In the current mirror circuit, the chip layout is designed by minimizing the distance between the resistive elements and the distance between the transistors in order to reduce the variation between the output currents. For this reason, the data is not distributed to all DACs at once, but is supplied in a tree structure by a folded current mirror circuit. However, if the number of times of folding is too large, errors increase. Further, in a current output type DAC, the current cannot be directly shared, so that only the number of output pads is required. As described above, a DAC of high gradation, that is, a multi-bit DAC must be laid out at pad intervals. This makes it difficult to design the layout of the chip.
[0010]
In the case of a current output type driving circuit, sample-and-hold circuits for a plurality of channels are provided on the output side of the DAC and sequentially written in a time-division manner, so that the number of DACs can be reduced and the DACs need not be laid out at pad intervals. There is a way. With such a configuration, the number of DACs is reduced, so that a multi-bit DAC for high gradation can be easily laid out, and the number of times of folding of the current mirror circuit can be reduced.
In the case of the voltage output type driving circuit, the voltage is held by the sample and hold circuit, whereas in the case of the current output type driving circuit, the current must be held. In an organic EL display, a current sampling (current sampling) circuit has already been proposed as a circuit for holding a current in a circuit on a display panel side.
[0011]
FIG. 35 shows a configuration example of a current sampling circuit used on the display panel side of the organic EL. As shown in the figure, the current sampling circuit has a drain connected to the power supply voltage V_DDMOS transistor M1, connected to the gate of the MOS transistor M1 and the power supply voltage V_DD, A switch SW1 provided between the drain and the gate of the MOS transistor M1, and an input terminal T._inA switch SW3 provided between the drain of the MOS transistor M1 and the output terminal T_outAnd a switch SW4 provided between the and the drain of the MOS transistor M1, and a switch SW7 provided in parallel with the capacitive element C1.
[0012]
FIG. 36 is a timing chart showing a basic operation of the current sampling circuit shown in FIG. At the time of current writing, the switches SW1 and SW3 are turned on, and the switch SW4 is turned off. That is, at the time of current writing, the MOS transistor M1 is in a diode-connected state, and the drain voltage, that is, the gate voltage at that time is applied to the electrode on the hold node side of the capacitive element C1 through the switch SW1. When shifting from writing to holding, the switch SW1 is turned off first to hold the voltage, and then the switch SW3 is turned off later. At the time of current reading, the switch SW4 is turned on while the switches SW1 and SW3 are turned off. Therefore, the MOS transistor M1 flows a saturation current determined by the gate voltage held by the capacitance element C1. The switch SW7 is a discharge switch for controlling the current flowing time to change the luminance of the display. The switch SW7 is normally kept off and is turned on when discharging.
[0013]
[Problems to be solved by the invention]
By the way, when a current output type driving circuit is formed using the above-mentioned conventional current sampling circuit, the capacitance value of the capacitance element C1 cannot be made too large. When a current sampling circuit is used as a driving circuit for a high-gradation display, there is a disadvantage that the voltage held in the capacitor C1 is visually recognized as a change in luminance even when the voltage changes by several mV (millivolt).
[0014]
In the MOS transistor M1, the drain voltage and the gate voltage are equal at the time of writing, but a difference occurs between the drain voltage and the gate voltage at the time of current reading. The drain voltage of the MOS transistor M1 is equal to the power supply voltage V during writing._DDThe output terminal T_outIt is determined by the load circuit on the side, ie, the circuit on the panel side, and is determined by the power supply voltage on the opposite side. For this reason, the drain voltage of the MOS transistor M1 may differ by several volts between the time of current writing and the time of current reading. Further, the voltage at the time of current reading may vary greatly depending on the variation of the TFT transistor on the panel side. Since the drain voltage of the MOS transistor M1 differs between the time of current writing and the time of current reading, the voltage held by the capacitance element C1 is affected by the inherent drain-gate capacitance of the MOS transistor M1 itself. In addition, the current at the time of writing differs from the current at the time of reading.
When an organic EL display panel is driven using such a current output type driving circuit, it is difficult to realize high-gradation image display.
[0015]
The present invention has been made in view of such circumstances, and an object of the present invention is to write the output current of a current output type D / A conversion circuit to a plurality of current sampling circuits in a time-division manner using a current sampling circuit. The number of D / A conversion circuits can be reduced to enable the layout of multi-bit D / A conversion circuits, and the distribution of reference current in the chip is simplified to improve the accuracy of the current, thereby achieving a high gradation organic EL display. An object of the present invention is to provide a suitable current sampling circuit and a current output type driving circuit.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a current sampling circuit according to the present invention comprises: a first MOS transistor having a source connected to a first power supply and a first switch circuit provided between a drain and a gate; A first capacitive element provided between the gate of the MOS transistor and the first power supply; a source connected to the drain of the first MOS transistor; and a second switch circuit provided between the drain and the gate. A second MOS transistor, a second capacitor provided between the gate of the second MOS transistor and the first power supply, and a second capacitor between the current input terminal and the drain of the second MOS transistor. Circuit having a third switch circuit, and a fourth switch circuit provided between the current output terminal and the drain of the second MOS transistor. The two partial circuits are alternately controlled to a current writing mode and a current reading mode. In the current writing mode, the first, second, and third switch circuits are controlled to be turned on. The fourth switch circuit is controlled to be turned off, and the gate voltage of the first MOS transistor is held in the first capacitance element in accordance with the input current from the current input terminal, and The gate voltage of the MOS transistor is held in the second capacitor, and the first, second, and third switch circuits are controlled to be turned off in the current read mode, and the fourth switch circuit Is turned on, and outputs a current according to an input current from the current input terminal from the current output terminal in the current writing mode.
[0017]
In the present invention, preferably, in the current writing mode, the first switch circuit, the second switch circuit, and the third switch circuit are turned off in this order.
[0018]
In the present invention, preferably, the drain and the source are connected to the gate of the first MOS transistor, and the on / off control is performed in reverse to the first switch circuit in accordance with a control signal applied to the gate. And a drain and a source connected to the gate of the second MOS transistor, and turned on in reverse to the second switch circuit in accordance with a control signal applied to the gate. And a sixth switch circuit including a MOS transistor that is controlled to be turned off.
[0019]
In the present invention, preferably, the first and second switch circuits are constituted by MOS transistors that are turned on / off in accordance with a control signal applied to a gate.
[0020]
In the present invention, preferably, the channel width of the MOS transistor forming the fifth switch circuit is formed to be approximately half the channel width of the MOS transistor forming the first or second switch circuit. .
[0021]
In the present invention, preferably, the channel width of the MOS transistor forming the sixth switch circuit is formed to be approximately half the channel width of the MOS transistor forming the first or second switch circuit. .
[0022]
In the present invention, preferably, the channel width of the second MOS transistor is formed larger than the channel width of the first MOS transistor.
[0023]
In the present invention, preferably, a bulk terminal of the second MOS transistor is connected to a source of the second MOS transistor.
[0024]
In the present invention, preferably, the threshold voltages of the first and second MOS transistors are formed lower than usual.
[0025]
In the present invention, preferably, the channel width of the MOS transistor forming the second switch circuit is larger than the channel width of the MOS transistor forming the first switch circuit.
[0026]
In the present invention, preferably, the second switch circuit includes an nMOS transistor and a pMOS transistor connected in parallel.
[0027]
In the present invention, preferably, the channel length of the MOS transistor forming the first switch circuit and the channel length of the MOS transistor forming the second switch circuit are the same as those of the MOS transistor forming the normal logic circuit. It is formed larger than the channel length of the transistor.
[0028]
Further, in the present invention, preferably, there is provided a seventh switch circuit provided between the drain of the second MOS transistor and the dummy load circuit, and the seventh switch circuit is provided with the current switch. It is controlled to be turned on until the write mode ends and the current read mode starts, and the output current from the drain of the second MOS transistor is output to the dummy load circuit.
[0029]
In the present invention, preferably, a current input line connected to the current input terminal intersects with the digital signal wiring, or a parallel running position, or a current input connected to the current input terminal. A line is provided between the current input line and the digital signal wiring at a position where the line intersects or runs in parallel with the current output line connected to the current output terminal, and is biased by the first power supply. Having a shield layer or shield wiring.
[0030]
In the present invention, preferably, a conductive layer biased to the first power supply voltage is formed around a voltage holding-side electrode of the first capacitance element or the second capacitance element.
[0031]
Further, in the present invention, it is preferably provided between an output terminal of a D / A conversion circuit for supplying a predetermined current and the current input terminal of one of the two partial circuits. A first current changeover switch circuit, and a second current changeover switch provided between the output terminal of the D / A conversion circuit and the current input terminal of the other of the two partial circuits. And a circuit.
[0032]
Further, in the present invention, preferably, there is provided a current mirror circuit for returning an output current of the D / A conversion circuit for supplying a predetermined current, and the current mirror circuit is provided for one of the two partial circuits. A current input terminal is connected to one current output terminal of the current mirror circuit, and the current input terminal of the other of the two partial circuits is connected to the other current output terminal of the current mirror circuit; I have.
[0033]
Further, the current output type driving circuit of the present invention is a current output type driving circuit which outputs a current of a plurality of channels in accordance with input data, wherein the register array holding the input data, and the data stored in the register array A current output type D / A conversion circuit that outputs a current corresponding to the current, and a first group of current sampling circuits that alternately operate in a current writing mode and a current reading mode in accordance with the output current of the D / A conversion circuit. And a current output circuit having a second group of current sampling circuits.
[0034]
In the present invention, preferably, the first group and the second group of current sampling circuits have a source connected to the first power supply, and a first switch circuit provided between the drain and the gate. One MOS transistor, a first capacitive element provided between the gate of the first MOS transistor and the first power supply, and a source connected to the drain of the first MOS transistor. A second MOS transistor provided with a second switch circuit, a second capacitor provided between a gate of the second MOS transistor and the first power supply, and a D / A conversion circuit. A third switch circuit provided between a current input terminal connected to a current output terminal of the second MOS transistor and a drain of the second MOS transistor; a current output terminal and a second switch connected to the second MOS transistor; Fourth partial circuit having a switch circuit is provided by the respective channels of the output current provided between the drain of the data.
[0035]
In the present invention, preferably, in the first group and the second group of current sampling circuits, when operating in the current writing mode, the plurality of partial circuits corresponding to the respective channels are sequentially arranged in the D / A mode. Current writing is performed according to the output current of the conversion circuit.
[0036]
In the present invention, preferably, in the current sampling circuits of the first group and the second group, the current output terminals of the respective partial circuits corresponding to the same channel are commonly connected, and correspond to the connection point. A current output transistor having a breakdown voltage corresponding to the voltage of the load circuit to be driven is provided between the current output pad and the channel.
[0037]
In the present invention, preferably, the control circuit sequentially outputs a channel selection signal corresponding to each of the channels according to a latch pulse supplied from the outside.
[0038]
In the present invention, preferably, the register array selects the input data corresponding to the channel selected by the channel selection signal according to the channel selection signal output by the control circuit, Output to the D / A conversion circuit.
[0039]
In the present invention, preferably, the control circuit outputs an enable signal that is held at a logic high level and a logic low level in each cycle of the latch pulse in response to a latch pulse supplied from the outside.
[0040]
In the present invention, preferably, the first group and the second group of current sampling circuits are controlled to a current write mode and a current read mode according to the enable signal, and the enable signal is set to the logical high level. At one time, the first group of current sampling circuits is controlled in a current write mode, the second group of current sampling circuits is controlled in a current read mode, and when the enable signal is at the logic low level, The group of current sampling circuits is controlled to a current writing mode, and the first group of current sampling circuits is controlled to a current reading mode.
[0041]
In the present invention, preferably, when the first group and the second group of current sampling circuits are controlled to the current writing mode in accordance with the enable signal, the output current of the D / A conversion circuit is preferably set. Is time-divisionally written to each of the partial circuits, and when the current read mode is controlled according to the enable signal, a current corresponding to the write current is simultaneously output from each of the partial circuits.
[0042]
In the present invention, preferably, a dummy current sampling circuit is provided on the current output side of the D / A conversion circuit, and the current output of the last channel among the plurality of channels from which current output is sequentially performed is provided. Is completed, and the output current of the D / A conversion circuit is output to the dummy current sampling circuit until the current output of the first channel starts next.
[0043]
In the present invention, preferably, one of the control circuits is provided for each of the plurality of adjacent D / A conversion circuits, and controls the operation of the plurality of D / A conversion circuits.
[0044]
Further, the present invention preferably has a frequency dividing circuit for dividing a system clock signal supplied from the outside and supplying the divided frequency to the control circuit.
[0045]
Further, in the present invention, preferably, a frequency divider that divides the externally supplied system clock signal by two, and a frequency divider that can set the output signal of the frequency divider by a factor of 0.5 A programmable frequency divider for dividing by a ratio, a counter for counting the output signal of the programmable frequency divider a predetermined number of times, and a clock enable circuit for stopping the output of the clock signal according to the output signal of the counter. And a clock signal generation circuit.
[0046]
Further, in the present invention, preferably, the control circuit is configured to control the register array, the D / A conversion circuit, and the output signal of the frequency divider, the clock enable circuit, and the programmable frequency divider. A control signal for controlling the operation of the current output circuit including the first group and the second group of current sampling circuits is generated.
[0047]
According to the present invention, in the current sampling circuit, there are provided two partial circuits which are alternately controlled to the current writing mode and the current reading mode. First and second MOS transistors connected in series to each partial circuit, and first and second MOS transistors provided between gates of the first and second MOS transistors and a first power supply voltage. , And first and second switch circuits provided between the gate and the drain of the first and second MOS transistors, and the third and fourth switch circuits are provided at the current input terminal and the output terminal, respectively. Are provided.
[0048]
In the current writing mode, the first, second, and third switch circuits are turned on, and the current output from the D / A conversion circuit is input to the first and second MOS transistors. Gate voltages generated in the first and second MOS transistors are held by the first and second capacitors, respectively. At the time of current reading, the first, second and third switch circuits are turned off, and the fourth switch circuit is turned on. Therefore, the voltage held in the first and second capacitance elements at the time of current writing is the first voltage. Is applied to the gate of the second MOS transistor, so that a current substantially the same as the current input at the time of writing is output from the current output terminal.
As described above, by using the current sampling circuit, the input current can be taken in with high accuracy at the time of current writing, and a current equal to the input current can be output at the time of current output.
[0049]
In the current output type driving circuit of the present invention, the current sampling circuits are provided for the channels of the current output. By using these current sampling circuits, the output current of the D / A conversion circuit is time-divided at the time of current writing. At the time of reading sequentially for each channel and reading the current, a current equal to the current taken into each channel at the time of writing the current is simultaneously output by the current sampling circuit corresponding to each channel and supplied to the load circuit.
[0050]
BEST MODE FOR CARRYING OUT THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a current sampling circuit (current sampling circuit) according to the present invention.
As shown, the current sampling circuit of the present embodiment has a source_DDA first MOS transistor M1 whose drain and gate are on / off controlled by a first switch circuit SW1, a gate of the first MOS transistor M1 and a power supply voltage V_DDA first capacitance element C1 provided therebetween, a second MOS transistor whose source is connected to the drain of the first MOS transistor M1 and whose drain-gate is on / off controlled by a second switch circuit SW2 M2, the gate of the second MOS transistor M2 and the power supply voltage V_DDA second capacitive element C2 provided therebetween and a current input terminal T_inA third switch circuit SW3 provided between the first MOS transistor M2 and the drain of the second MOS transistor M2;_outAnd a fourth switch circuit SW4 provided between the drain of the second MOS transistor M2.
[0051]
FIG. 2 is a timing chart showing the operation of the current sampling circuit of the present embodiment. Hereinafter, the operation of the current sampling circuit according to the present embodiment will be described with reference to FIGS.
[0052]
At the time of current writing (at the time of input), the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 are turned on with the fourth switch circuit SW4 turned off, and the first MOS transistor is turned on. M1 and the second MOS transistor M2 are in a diode-connected state, an input current (output current of the DAC) flows through each MOS transistor, and the drain voltage = gate voltage of each transistor is equal to the capacitance element C1 and the capacitance element C2. Is written to.
When shifting from the current writing to the hold state, the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 are turned off in this order with the fourth switch circuit SW4 turned off, and the first switch circuit SW4 is turned off. The drain voltage of the MOS transistor M1 = the gate voltage, and the drain voltage of the second MOS transistor M2 = the gate voltage.
[0053]
At the time of current reading (at the time of output), the fourth switch circuit SW4 is turned on while the first switch circuit SW1, the second switch circuit SW2, and the third switch circuit SW3 are turned off, and the output terminal T_outThe read current is output to (4).
The current sampling circuit of the present invention is different from the conventional current sampling circuit in that a second MOS transistor M2 is added to a connection point between the MOS transistor M1 and the switch circuits SW3 and SW4, and a capacitor for holding the gate voltage thereof. The point is that a switch circuit SW2 for controlling the element C2 and current writing is added.
[0054]
In the present embodiment, by adding the second MOS transistor M2, this transistor operates as a cascode circuit at the time of current reading, and changes in the drain voltage of the first MOS transistor between current writing and current reading. From about several volts to several hundred mV, which is about 1/10 (−20 dB). By suppressing the fluctuation of the drain voltage of the MOS transistor, the effect of changing the channel length is suppressed, and the influence of the gate-drain capacitance on the holding voltage is suppressed. Thus, the difference between the current value at the time of writing the current and the current value at the time of reading the current can be made very small. For this reason, the influence of the variation of the circuit on the load side is suppressed.
[0055]
Second embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the current sampling circuit according to the present invention.
As shown, the current sampling circuit of the present embodiment is different from the first current sampling circuit in that a switch circuit SW5 is added to the hold node side of the capacitance element C1 and a switch circuit is connected to the hold node side of the capacitance element C2. The point is that the circuit SW6 is added. As described above, when a semiconductor circuit is integrated on a chip, it is difficult to design a large value of the capacitance element C1 or the capacitance element C2, and the capacitance value becomes several pF at most. Therefore, the influence of the charge generated in the switching operation cannot be ignored.
[0056]
FIG. 4 is a timing chart showing the operation of the current sampling circuit of the present embodiment.
As shown in FIG. 4, the current sampling circuit of the present embodiment is different from the above-described second current sampling circuit of the present invention in that a switch circuit SW5 performs an operation opposite to SW1 and a switch circuit SW6 performs an operation opposite to SW2. This is the point where the operation is performed. As a result, the charge generated when the switch circuits SW1 and SW2 are turned on / off is canceled by the switch circuits SW5 and SW6, and the influence of the charge on the on / off of the switching elements can be reduced.
[0057]
Third embodiment
FIG. 5 is a circuit diagram showing a third embodiment of the current sampling circuit according to the present invention.
The current sampling circuit according to the present embodiment is a specific example of the current sampling circuit according to the second embodiment of the present invention shown in FIG.
[0058]
As shown in FIG. 5, in the current sampling circuit of this embodiment, the switching elements SW1 and SW5 are controlled by the output signal of the NAND gate NG1 and the inverter INV1, and the switching element SW2 is controlled by the output signal of the NAND gate NG2 and the inverter INV2. And SW6 are controlled. Further, the switching element SW3 is controlled by the output signal of the inverter INV3, and the switching element SW4 is controlled by the output signal of the inverter INV5.
[0059]
As shown in FIG. 5, in the current sampling circuit of the present embodiment, the switching elements SW1, SW2, SW5 and SW6 are formed by pMOS transistors, and the switching elements SW3 and SW4 are formed by nMOS transistors.
[0060]
The clock signal CK1 and the output signal of the inverter INV3 are input to the input terminals of the NAND gate NG1, respectively, and the clock signal CK2 and the output signal of the inverter INV3 are input to the input terminals of the NAND gate NG2, respectively.
The selection signal SEL and the write enable signal WE are applied to the input terminals of the NAND gate NG3, respectively.
The input terminal of the inverter INV1 is connected to the output terminal of the NAND gate NG1, the input terminal of the inverter INV2 is connected to the output terminal of the NAND gate NG2, and the input terminal of the inverter INV3 is connected to the output terminal of the NAND gate NG3.
The output enable signal OE is applied to the input terminal of the inverter INV4. The input terminal of the inverter INV5 is connected to the output terminal of the inverter INV4.
[0061]
In the current sampling circuit of the present embodiment, at the time of current writing (sampling), when both the selection signal SEL and the write enable signal WE are held at high level, the output of the inverter INV3 becomes high level, and the switching element SW3 is turned on. . At this time, since the clock signals CK1 and CK2 are held at the high level, the outputs of the NAND gates NG1 and NG2 are held at the high level, and the outputs of the inverters INV1 and INV2 are held at the low level. At this time, the switching elements SW1, SW2 and SW3 are turned on, and the other switching elements SW4, SW5 and SW6 are turned off. As a result, the gate voltages of the transistors M1 and M2 are held by the capacitors C1 and C2, respectively.
[0062]
After the current writing is completed, the clock signals CK1 and CK2 are sequentially switched to a low level. In response, the switching elements SW1 and SW2 are sequentially turned off. On the other hand, as the switching element SW1 turns off, the switching element SW5 turns on, and as the switching element SW2 turns off, the switching element SW6 turns on.
Then, when the write enable signal WE switches to low level, the switching element SW3 turns off. At this time, the gate voltages of the transistors M1 and M2 are held by the capacitors C1 and C2, respectively.
[0063]
At the time of current reading (current output), the output enable signal OE is held at a high level. In response to this, the switching element SW4 is turned on, so that the transistors M1 and M2 flow a saturation current determined by the respective gate voltages by the voltage held in the capacitors C1 and C2, and this current flows to the output terminal T_outOutput from to the load side.
[0064]
In the current sampling circuit of the present embodiment, preferably, the channel width of the MOS transistor forming the switching element SW5 is formed to be about １ ／ of the channel width of the MOS transistor forming the switching element SW1. Alternatively, of the three gates, one is used as the switching element SW5 and two are used as the switching element SW1. The same applies to the MOS transistors forming the switching elements SW2 and SW6.
[0065]
When shifting from the current writing to the hold state, it is important to cancel the charge generated when the switching elements SW1 and SW2 are turned off in order to accurately hold the writing current. If the switching elements SW5 and SW6 are turned on before the switching elements SW1 and SW2 are turned off, the effect of canceling becomes extremely small. Therefore, the switching elements SW5 and SW6 are driven by the output of the inverter after the NAND output for driving the switching elements SW1 and SW2.
[0066]
According to the current sampling circuit of the present embodiment, the influence of the switching operation, which becomes a problem when a semiconductor integrated circuit is formed, can be improved, whereby the current values at the time of current writing and current reading match with sufficient accuracy, and In addition, the influence of the variation of the circuit on the output load side is suppressed.
[0067]
As described above, the advantage that the output current accuracy can be improved and the influence of the variation on the load side can be reduced by adding the MOS transistor having the cascode configuration has been described. However, the cascode configuration reduces the power supply voltage margin. A disadvantage occurs. Hereinafter, a specific method for expanding the power supply voltage margin will be described.
[0068]
The voltage V required for the current sampling circuit to operate_maxIs given by the following equations (1) to (5). First, here, V_GS1= V_eff1+ V_th, V_GS2= V_eff2+ V_thIn other words, the following equation holds for the first MOS transistor M1.
[0069]
(Equation 1)

[0070]
Similarly, the following equation is obtained for the second MOS transistor M2.
[0071]
(Equation 2)

[0072]
In equations (1) and (2), W1 and W2 indicate the channel widths of transistors M1 and M2, respectively, and L indicates the channel length of transistors M1 and M2. I_maxIs the maximum value of the output current of the current output type driving circuit.
[0073]
V in equations (1) and (2)_eff1And V_eff2Can be said to be an effective voltage necessary for flowing a current through the MOS transistors M1 and M2. When the effective voltage is small, the voltage is likely to be affected by the coupling capacitance between the drain and the gate and the ON / OFF state of the switching elements SW1 and SW2.
Maximum voltage V applied to MOS transistors M1 and M2 having a cascode configuration_maxIs given by the following equation.
[0074]
(Equation 3)

[0075]
In the equation (3), the constant α is a voltage between the drain and the source of the MOS transistor forming the switching elements SW3 and SW4, and α = V_DSIt is about 0.2V. Considering the connection with the DAC output, the maximum voltage V_maxIs given by the following equation.
[0076]
(Equation 4)
V_max≦ (1/2) V_DD… (4)
[0077]
Where V_th= 0.75V, V_DD= 4.75V, the following result is obtained.
[0078]
(Equation 5)
V_eff1+ V_eff2= 0.675V (5)
[0079]
According to equation (5), V_eff1And V_eff2Takes a considerably small voltage of several hundred mV. Since an error of several mV generated at the time of sampling and holding also becomes a problem, sufficient care is required in both circuit design and layout design.
[0080]
Fourth embodiment
FIGS. 6 to 8 are circuit diagrams showing examples of the fourth embodiment of the current sampling circuit according to the present invention.
The examples shown in FIGS. 6 to 8 have substantially the same configuration as the current sampling circuit of the first embodiment of the present invention shown in FIG. However, in each example, the channel length, bulk bias or threshold voltage of the MOS transistors M1 and M2 are different from those of the above-described first embodiment of the present invention.
[0081]
First, in the embodiment of the current sampling circuit shown in FIG. 6, the channel width of the MOS transistor M2 is formed larger than the channel width of the MOS transistor M1. That is, if the channel width of the MOS transistor M1 is W1 and the channel width of the MOS transistor M2 is W2, W2> W1.
[0082]
At the time of current reading of the current sampling circuit, the MOS transistor M2 functions as a cascode transistor, and the output current is determined by the MOS transistor M1. If the gate voltage of the MOS transistor M1 shifts, the read current shifts from a target current value. However, there is no problem in the operation of the cascode even if the gate voltage of the MOS transistor M2 is slightly shifted.
Therefore, in the current sampling circuit of the present embodiment, V_eff1> V_eff2That is, by designing the channel width of the MOS transistors M1 and M2 under the condition of W2> W1, the accuracy of the output current at the time of current reading can be improved.
[0083]
Next, in the embodiment of the current sampling circuit shown in FIG. 7, the bulk bias voltage of the MOS transistor M2 is obtained from its source. That is, as shown in FIG. 7, the substrate (bulk) of the MOS transistor M2 is connected to its source. Thereby, the bulk bias voltage of the MOS transistor M2 is determined by its source voltage.
[0084]
The substrate of the MOS transistor M2 has the power supply voltage V_DD, The difference between the source voltage and the bulk voltage causes the following equation to be satisfied instead of the equation (3) due to the substrate bias effect.
[0085]
(Equation 6)

[0086]
In the current sampling circuit of this embodiment, by connecting the bulk of the MOS transistor M2 to the source, the substrate bias effect ΔV_thOnly the maximum output current I_maxIncreases.
[0087]
In the embodiment of the current sampling circuit shown in FIG. 8, the threshold voltages V of the MOS transistors M1 and M2 are_thIs formed lower than usual. That is, the MOS transistors M1 and M2 are low threshold voltage transistors.
[0088]
According to the above equation (3), the voltage V_maxIs the threshold voltage V of the transistors M1 and M2_thAffected by Therefore, by using the low threshold voltage MOS transistors M1 and M2 as in the present embodiment, the effective voltage V of the transistors M1 and M2 is reduced._eff1And V_eff2While maintaining the voltage V_maxCan be lowered. That is, the voltage V_maxEven if is reduced, the current sampling circuit can operate normally, and the operating characteristics at a low power supply voltage are improved.
[0089]
Fifth embodiment
9 and 10 are circuit diagrams showing examples of the fifth embodiment of the current sampling circuit according to the present invention.
The example of the current sampling circuit of the present embodiment shown in FIG. 9 has almost the same configuration as the circuit example of the third embodiment of the current sampling circuit of the present invention shown in FIG. However, in the current sampling circuit of the present embodiment, the switching elements SW1 and SW2 are formed by pMOS transistors M3 and M4, respectively, and the channel width of the transistor M4 is formed larger than the channel width of the transistor M3.
[0090]
In the current sampling circuit of the present embodiment, the MOS transistor M4 forming the switching element SW2 must flow a current near the intermediate voltage. When the power supply voltage decreases, it becomes difficult to flow current due to the influence of the substrate bias effect of the transistor. Therefore, by designing the channel width W4 of the MOS transistor M4 forming the switching element SW2 to be larger than the channel width W3 of the MOS transistor M3 forming the switching element SW1, the switching element SW2 operates at a low power supply voltage. Can be maintained at a predetermined value, and the operating characteristics of the current sampling circuit are improved.
[0091]
FIG. 10 is a circuit diagram showing another example of the current sampling circuit of the present embodiment.
As shown, the current sampling circuit of this embodiment has substantially the same configuration as the embodiment of the current sampling circuit shown in FIG. 9, but the difference from the embodiment of FIG. 9 is that the switching element SW2 is connected in parallel. And a pMOS transistor M4 and an nMOS transistor M5.
[0092]
As described above, the switching element SW2 must flow a current near the intermediate voltage. For this reason, in the current sampling circuit of the present embodiment, the switching element SW2 is configured by connecting the pMOS transistor M4 and the nMOS transistor M5 in parallel. As a result, a sufficient current can flow even at the intermediate voltage, and the operating characteristics of the current sampling circuit are improved.
[0093]
Sixth embodiment
FIGS. 11 to 13 are circuit diagrams showing examples of the sixth embodiment of the current sampling circuit according to the present invention.
Note that the current sampling circuit of the present embodiment is devised to improve its current holding characteristics.
[0094]
In the embodiment of the current sampling circuit shown in FIG. 11, in the hold state, the MOS transistor M3 forming the switching element SW1, the MOS transistor M4 forming the switching element SW2, and the MOS transistors forming the switching elements SW3 and SW4 are all included. Off.
[0095]
Therefore, the drain voltage of the MOS transistor M1 and the drain voltage of the MOS transistor M2 are equal to the power supply voltage V_DDIs equal to Therefore, the voltage held in the capacitor C1 gradually increases due to the leakage current of the MOS transistor M3 constituting the switching element SW1._DDWill change over time. Similarly, the voltage held in the capacitance element C2 gradually increases due to the leakage current of the MOS transistor M4 forming the switching element SW2._DDWill change over time.
[0096]
The leakage current of the MOS transistor has a threshold voltage V_thIncreases sharply when decreases.
In the current sampling circuit of the present embodiment, the design value of the channel length of the MOS transistor M3 forming the switching element SW1 and the MOS transistor M4 forming the switching element SW2 is designed to be larger than usual. That is, as shown in FIG. 11, the channel length of the MOS transistors M3 and M4 is L + α. As a result, the leakage current of the transistors M3 and M4 during holding is reduced, so that deterioration of the holding characteristics can be prevented.
[0097]
In the embodiment of the current sampling circuit shown in FIG. 12, compared with the embodiments of the other current sampling circuits, the switching element SW7 and the MOS transistor M8 are added, so that the current path is connected to the transistors M1 and M2 in the hold state. Form. Thus, the voltage difference between the switching elements SW1 and SW2 is reduced, and the leakage current is reduced.
[0098]
In FIG. 12, the transistor M8 is diode-connected to form a dummy load circuit. At the time of hold, the switching element SW7 is turned on, so that a dummy load circuit including the transistor M8 is connected in series to the cascode-connected transistors M1 and M2. For this reason, the transistors M1 and M2 are held in the ON state by the voltage held in the capacitors C1 and C2 at the time of current writing, so that the power supply voltage V_DD, A current path is formed to a dummy load circuit including the transistor M8, and a current flows. Thus, the voltage difference between both ends of the switching element SW1 and the voltage difference between both ends of the switching element SW2 are reduced, so that the leakage current of these switching elements SW can be reduced.
[0099]
FIG. 13 is a timing chart showing the operation of the current sampling circuit of the present embodiment shown in FIG.
As shown in FIG. 13, at the time of current writing, the switching elements SW1, SW2, and SW3 are turned on, and the other switching elements are turned off. In this state, the input terminal T_inThe gate voltages of the transistors M1 and M2 generated in response to the current input from are held by the capacitors C1 and C2, respectively.
[0100]
Next, at the time of hold, the switching elements SW5, SW6 and SW7 are turned on, and the other switching elements are turned off. In this state, the transistors M1 and M2 and the transistor M8 are connected to the power supply voltage V_DDAnd reference potential V_SSAre connected in series, a current corresponding to the gate voltage held by the capacitors C1 and C2 flows through the transistors M1 and M2.
As a result, the gate-source voltage of each of the transistors M1 and M2 decreases. That is, the voltage across both ends of the switching elements SW1 and SW2 in the off state decreases. Therefore, the leakage current of the switching elements SW1 and SW2 is reduced, and the holding characteristics of the current sampling circuit are improved.
[0101]
Next, at the time of current reading, the switching element SW4 is turned on, and all other switching elements are turned off. At this time, the gate voltages of the transistors M1 and M2 are determined by the voltages held in the capacitors C1 and C2, and the output voltage I_outIs output to the load circuit via the switching element SW4.
[0102]
According to the examples of the present embodiment described above, the current holding characteristic of the current sampling circuit can be improved, and for example, a temporal change to a level that is completely invisible even when held for several μsec (microseconds) to several tens μsec. Can be suppressed. That is, according to each example of the present embodiment, the current holding characteristic of the current sampling circuit can be improved, whereby the output current supplied to the load circuit at the time of writing the current can be made substantially equal to the write current. The current can be controlled with high precision.
[0103]
The embodiments of the current sampling circuit according to the present invention have been described above. Hereinafter, a current output type driving circuit configured using the current sampling circuit of the present invention will be described.
[0104]
Seventh embodiment
FIG. 14 is a configuration diagram showing one embodiment of a current output type driving circuit according to the present invention. As shown, the current output type driving circuit of the present embodiment includes a test circuit 10, a control circuit 20, a writing circuit 30, a reference current source circuit 40, a flag bidirectional shift register 50, a register array 60 for image data, .., 80-3, 80-4, and current output circuits 90-1, 90-2, 90-3, DACs (current output type) 80-1, 80-2,. 90-4.
[0105]
The test circuit 10 tests the operation of the entire circuit according to the input signals TOUT, TMODE, and TCLK.
The control circuit 20 responds to the direction control signal DIR, the reset signal RESET, the load pulse LOAD, the latch pulse LATCH, and the clock signal MCLK in accordance with the write circuit 30, the flag bidirectional shift register 50, and the control signal generation circuits 70-1 and 70. The driving clock signal and the control signal are output respectively to -2.
The writing circuit 30 receives the m-bit image data D based on the driving clock signal and the control signal from the control circuit 20._in0, D_in1,…, D_inm-1ラ ッ チ is latched, and the operating frequency is preferably lowered by serial-parallel conversion, and is output to the image data register array 60.
[0106]
The reference current source circuit 40 connects, for example, a resistor between an external resistor connection terminal REXT and GND of a reference current generating circuit of a certain driver IC (current output type driving circuit) and sets a reference according to the resistance value. A reference current common to the driver ICs on the display panel is generated at a current output terminal IREFOUT. Each driver IC takes in the reference current through the reference current input terminal IREFIN into the driver IC according to the control of the input signal NEXTREF, increases the required number of outputs, and outputs it to the DACs 70-1 to 70-4.
The flag bidirectional shift register 50 outputs the flag signals START / NEXT and NEXT / START input from both ends of the shift register in accordance with the direction control signal DIR and the drive clock signal and the control signal input from the control circuit 20, respectively. Alternatively, the image data is shifted in one of the right directions, the shifted flag signal is supplied to the image data register array 60, and the position (address) of the register array in which the image data input from the writing circuit 30 is written is selected.
The image data register array 60 is composed of a double buffer type register. The image data input from the writing circuit 30 is held in the preceding register, and the image data held in response to the input of the LATCH signal is stored in the subsequent register. The data is transferred to a register and sequentially output to the DACs 80-1, 80-2, 80-3, and 80-4 according to the channel selection signal input from the control signal generation circuit 70.
[0107]
DACs 80-1, 80-2, 80-3 and 80-4 are current output type digital / analog conversion circuits. That is, these conversion circuits generate current signals corresponding to image data sequentially input from the image data register array 60, and output the current signals to the current output circuits 90-1, 90-2, 90-3, and 90-4. Output by division.
Each of the current output circuits 90-1, 90-2, 90-3, and 90-4 includes the above-described current sampling circuit according to the present invention and a high-voltage or medium-voltage current output transistor. These current output circuits sample and hold the converted current corresponding to the image data input from the DACs 80-1, 80-2, 80-3 and 80-4, and input the LOAD signal to the LOAD signal. Is output to a plurality of output terminals according to.
[0108]
The current output type driving circuit according to the present embodiment is configured to input image data D based on a control signal supplied from the outside._in0, D_in1,…, D_inm-1Is held, and the held image data is output to any of the plurality of DACs 80-1, 80-2, 80-3, and 80-4 according to the channel selection signal.
The DACs 80-1, 80-2, 80-3 and 80-4 generate a reference current supplied from the reference current source circuit 40 and a current corresponding to the input image data. The currents supplied from the DACs 80-1, 80-2, 80-3, and 80-4 are held by the current output circuits 90-1, 90-2, 90-3, and 90-4. The signal is output to a plurality of output terminals according to the input of the LOAD signal.
[0109]
FIG. 15 is a configuration diagram illustrating a configuration example of the current output circuit of the present embodiment.
As shown in the figure, the current output circuit 90 has a medium or high withstand voltage that is sufficient for driving the first bank 91, the second bank 92, and the display panel each including a plurality of current sampling circuits. And a current output transistor array 93 composed of a plurality of transistors having a withstand voltage.
[0110]
As shown in FIG. 15, a plurality of current sampling circuits are arranged in each of the first bank 91 and the second bank 92 by the number of channels of the output current. The current sampling circuits of each channel of the first bank 91 are arranged corresponding to the current sampling circuits of each channel of the second bank 92. Further, the current sampling circuits of each channel of the first bank 91 and the second bank 92 are arranged corresponding to the transistors having a predetermined withstand voltage of each channel of the current output transistor array 93.
[0111]
For example, in the first bank 91, the first channel current sampling circuit 91-1 and the first channel current sampling circuit 92-1 in the second bank 92, and the first channel predetermined sampling in the current output transistor array 93. It is arranged corresponding to transistor 93-1 having a withstand voltage. The current output terminal IOUT of the current sampling circuit 91-1 and the current output terminal IOUT of the current sampling circuit 92-1 are commonly connected to the source of the transistor 93-1 having a predetermined withstand voltage. Similarly, the n-th channel current sampling circuit 91-n of the first bank 91, the n-th channel current sampling circuit 92-n of the second bank 92, and the n-th channel predetermined current in the current output transistor array 93. It is arranged corresponding to transistor 93-n having a withstand voltage. The current output terminal IOUT of the current sampling circuit 91-n and the current output terminal IOUT of the current sampling circuit 92-n are commonly connected to the source of the transistor 93-n having a predetermined withstand voltage. In the current output transistor array 93, the drains of the transistors 93-1, 93-2,..., 93-n having a predetermined withstand voltage are connected to the output pads 94-1, 94-2,. I have.
[0112]
The current input terminals IIN of all the current sampling circuits of the first bank 91 and the second bank 92 are connected to current output terminals of a current output type DAC not shown in FIG. The current sampling circuit of the first bank 91 and the current sampling circuit of the second bank 92 are alternately controlled to the write mode and the read mode according to the control signals OE0 and OE1. By these current sampling circuits, a drive current corresponding to the output current of the DAC is output to the load side through the current output transistors 93-1 93-2,..., 93-n.
[0113]
For example, when driving the organic EL element, the current output circuit 90 of the present embodiment needs to supply a drive current corresponding to the output current of the DAC to the organic EL element at a voltage of about 10 V to 20 V. Therefore, one transistor 93-1 to 93-n having a predetermined withstand voltage of medium or high withstand voltage is provided for each output channel, and the output current from the current sampling circuit is supplied to the pads 94-1 to 94-n. , And outputs to the organic EL element of each channel to cope with a high voltage.
[0114]
The current sampling circuit of the present embodiment corresponds to the above-described embodiments and examples of the current sampling circuit of the present invention. Here, for example, the current sampling circuit is configured by the third embodiment of the current sampling circuit shown in FIG.
[0115]
In each of the current sampling circuits of the present embodiment, when the selection signal SEL and the write enable signal WE are in an active state (for example, high level), the DAC is added to the capacitors C1 and C2 of the current sampling circuit at the timing set by the clock signals CK1 and CK2. The gate voltage corresponding to the output current from is read and held. When the read enable signal OE is in an active state (for example, high level), a current corresponding to the gate voltage held in the capacitors C1 and C2 is output. Therefore, the current output circuit 90 of the present embodiment supplies a high-precision drive current to the organic EL element of each channel based on the output current of the DAC by each current sampling circuit.
[0116]
FIG. 16 is a timing chart showing the operation of the current output type driving circuit of the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIGS.
As shown in FIG. 15, the write operation and the read operation of the current sampling circuits of the first bank 91 and the second bank 92 are alternately controlled by enable signals OE0 and OE1. That is, the enable signal OE0 is input as the write enable signal WE of each current sampling circuit of the first bank 91, and the enable signal OE1 is input as the read enable signal OE. Conversely, in each current sampling circuit of the second bank 92, the enable signal OE1 is input as the write enable signal WE, and the enable signal OE0 is input as the read enable signal OE.
[0117]
Therefore, when the current sampling circuit of the first bank 91 is writing, the current sampling circuit of the second bank 92 outputs a current, and conversely, when the current sampling circuit of the second bank 92 is writing, The current sampling circuit of one bank 91 outputs a current. That is, the current sampling circuit of the first bank 91 and the current sampling circuit of the second bank 92 are alternately controlled to the write mode and the read (current output) mode.
[0118]
As shown in the timing chart of FIG. 16, the clock signals CK1 and CK2 and the enable signals OE0 and OE1 are generated in synchronization with the latch pulse LATCH. The latch pulse LATCH is generated by the system and is supplied to the control signal generation circuits 70-1 and 70-2. The above-described clock signals CK1 and CK2 and the enable signals OE0 and OE1 are respectively generated by these control signal generation circuits and supplied to the current output circuit 90.
[0119]
As illustrated, clock signals CK1 and CK2 and enable signals OE0 and OE1 are generated in synchronization with the latch pulse LATCH.
The enable signal OE0 and the enable signal OE1 are alternately held at a high level and a low level in each cycle of the latch pulse LATCH.
[0120]
When the enable signal OE0 is at a high level, the current sampling circuit of the first bank 91 performs writing. At this time, in the current sampling circuits 91-1, 91-2,..., 91-n of the first bank 91, the gate voltages of the transistors M1 and M2 are applied to the capacitors C1 and C2 at the timing set by the clock signals CK1 and CK2. Are respectively applied and held.
[0121]
In the next cycle of the latch pulse LATCH, the enable signal OE0 switches to a low level, and the enable signal OE1 switches to a high level. Therefore, the current sampling circuit of the second bank 92 performs writing, and the current sampling circuit of the first bank 91 performs reading, that is, current output. As shown in the timing chart of FIG. 16, at this time, for example, a current is output from the current output terminal IOUT of the current sampling circuit 91-1 of the first bank 91.
[0122]
As described above, in the current output circuit 90 of the present embodiment, the current sampling circuit of the first bank 91 and the current sampling circuit of the second bank 92 alternately perform the write mode and the read in response to the enable signals OE0 and OE1. In the write mode, the current sampling circuit performs writing according to the output current from the DAC, and in the read mode, outputs the current held during the write mode operation. Current to the load with high accuracy.
[0123]
FIG. 17 is a configuration diagram illustrating a configuration example of a register array in the current output type driving circuit of the present embodiment. The circuit example shown in FIG. 17 is a partial circuit of a register array corresponding to one DAC in the current output type driving circuit of the present embodiment shown in FIG. In the following description, for convenience, this partial circuit is referred to as a register array and denoted by reference numeral 60.
[0124]
As shown in the figure, the unit cells forming the register array 60 include, for example, double buffer type latch circuits 62-1, 62-2,..., 62-n in which D-type latch circuits having transmission gates are connected in two stages. 63-1, 63-2, ..., 63-n. The latch circuit forms an n × m array in which the number n of channels of the current sampling circuit connected to the output of one DAC is the number of words, and the bit width m of the image data is the bit width. In each latch circuit, the transmission gate of the preceding latch circuit is turned on / off by the outputs WD1, WD2, ..., WDi of the flag registers 50-1, 50-2, ..., 50-i.
[0125]
In the current output type driving circuit of the present embodiment, for example, a start pulse START is input to the flag register 50-1. Further, the image data is output to the data buses DX0 to DXm-1, DY0 to DYm-1, and DZ0 to DZm-1 inside the driving circuit via the writing circuit. The start pulse is sequentially shifted by the flag registers 50-1, 50-2,..., 50-i, so that, for example, in a double buffer type latch circuit in which image data for two channels are connected in two stages for each of three channels, The data is written to the latch circuit.
[0126]
When the writing of the image data is completed, the input of the latch pulse LATCH causes the image data held in the preceding latch circuit in each of the double buffer type latch circuits to be output to the subsequent latch circuit. The output portion of the subsequent latch circuit is a selection circuit, and the output of each selection circuit is connected to a common data bus 66 to 67. Data buses 66 to 67 are connected to the input side of the buffer 64. The output terminal of the buffer 64 is connected to the input terminal of the DAC decoder. That is, the output of the double buffer type latch circuit is input to the DAC decoder via the buffer 64.
[0127]
Which of the double buffer type latch circuits 62-1, 62-2,..., 63-n to 63-1, 63-2,. , SELn input to the subsequent selection circuit of the double buffer type latch circuit. As shown, the selection signals SEL1, SEL2,..., SELn are input to the buffer 65, and the selection signals held by the buffer 65 are respectively supplied to the double buffer type latch circuits 62-1, 62-2,. 63-1, 63-2, ..., 63-n.
[0128]
FIG. 18 is a block diagram showing a configuration of a partial circuit including a register array 60, a control signal generation circuit 70, a DAC 80, and a current output circuit 90 which constitute the current output type driving circuit of the present embodiment.
In the current output type driving circuit of the present embodiment, a series of operations of reading digital image data from the register array 60 in a time sharing manner, outputting a current corresponding to the image data by the DAC 80, and writing the current to the current output circuit 90 sequentially. Done. The control signal generation circuit 70 generates a control signal for controlling the series of operations and outputs the control signal to each component of the current output type driving circuit.
[0129]
For example, n-channel register arrays 62-1, 62-2,..., 62-n are connected to the input side of the decoder of the DAC 80 via a selection circuit and an output buffer 64. On the output side of the DAC 80, a current I for n channels is provided._O1, I_O2, ..., I_OnIs output. Which channel of image data is selected from the register array 60 and output to the DAC 80 is controlled by the selection signals SEL1, SEL2,..., SELn generated by the control signal generation circuit 70. The image data of the selected channel is input from the register array 60 to the decoder of the DAC 80, converted into a current output by the DAC 80, and written to the current output circuit 90.
[0130]
In the current output circuit 90, as shown in the figure, the respective current sampling circuits of the first bank 91 and the respective current sampling circuits 92 of the second bank 92 alternately output a high level signal from the control signal generation circuit 70. The write mode and the read mode are repeated in response to the enable signals OE0 and OE1 which are switched at a low level, the current output from the DAC 80 is taken in, and an image display element (not shown) such as an organic EL element, Output to
[0131]
FIG. 19 is a timing chart showing the operation of each component of the current output type driving circuit of the present embodiment shown in FIG. Hereinafter, the basic operation of this circuit group will be described with reference to FIGS.
In each operation cycle, the control signal generation circuit 70 is cleared by the input of the latch pulse LATCH, and the operation starts.
[0132]
As shown in FIG. 19, the selection signals SEL1, SEL2,..., SELn are sequentially generated from the control signal generation circuit 70 following the latch pulse LATCH. Further, clock signals CK11, CK12, CK21, CK22,..., CK1n, CK2n supplied to each channel are generated in order with the respective selection signals.
[0133]
The selection signals SEL1, SEL2,..., SELn are supplied to the register array 60. In response to this, the image data of each channel held in the register array 60 is sequentially read and input to the DAC 80 decoder.
The input image data is sequentially converted to a current output by the DAC 80 and output to the current output circuit 90. In the current output circuit 90, one of the first bank 91 and the second bank 92 is controlled to the write mode and the other is controlled to the read mode by the enable signals OE0 and OE1. The current output from the DAC 80 is sequentially written to each current sampling circuit in the bank on the write mode side in accordance with the channel selection signals SEL1, SEL2,.
[0134]
Note that the current sampling circuit includes a first clock signal group CK11, CK12,..., CK1n for turning off the first switch circuit at the same time as the channel selection signal, and a second clock signal group CK1n that is delayed by the first switch circuit. , CK2n for turning off the second switch circuit. These selection signals may not be aligned for each channel, and the number of wirings may be reduced by combining several types of selection signals. Also, clock signals may not be aligned for each channel and a few sets of signals may be used. May be shared.
[0135]
As shown in FIG. 19, when a load pulse LOAD is input from the outside, the signals OE0 and OE1 for controlling switching between the write mode and the read mode are inverted, and are alternately switched between a low level and a high level. When the enable signal OE0 is at a low level and the enable signal OE1 is at a high level, the current sampling circuit of the first bank 91 operates in the current read mode, outputs current, and the current sampling circuit of the second bank 92 writes. It operates in the mode and takes in the output current from the DAC. On the other hand, when the enable signal OE0 is at the high level and the enable signal OE1 is at the low level, the current sampling circuits in the second bank 92 operate in the read mode, and the currents held by the current sampling circuits are output from the first bank. The current sampling circuit of the bank 91 operates in the write mode, and takes in the output current from the DAC.
[0136]
Eighth embodiment
FIG. 20 is a configuration diagram showing an eighth embodiment of the current output type driving circuit according to the present invention. Except for the current output circuit, the other components of the current output type driving circuit of the present embodiment have substantially the same configuration as those of the current output type driving circuit of the present invention shown in FIG. FIG. 20 shows the configuration of the current output circuit 90a in the present embodiment. In the following description, only the current output circuit 90a will be described, and for the other components, refer to the description of the above-described seventh embodiment.
[0137]
As shown in FIG. 20, the current output circuit 90a according to this embodiment includes a first bank 91, a second bank 92, a current output transistor array 93, and a dummy current sampling circuit 94. Among them, the dummy current sampling circuit 94 is a part newly added in the present embodiment, and the other partial circuits are the same as the corresponding constituent parts of the current output circuit of the seventh embodiment shown in FIG. It is.
[0138]
As shown in FIG. 20, in the dummy current sampling circuit 94, the current input terminal IIN is connected to a current output terminal of the DAC 80 (not shown). A dummy control terminal is provided in the dummy current sampling circuit 94, and a dummy selection signal DUM from a control signal generation circuit 70a (not shown) is input to the dummy control terminal.
[0139]
FIG. 21 is a block diagram showing the configuration of a partial circuit including the register array 60, the control signal generation circuit 70a, the DAC 80, and the current output circuit 90a which constitute the current output type driving circuit of the present embodiment.
The difference between the partial circuit of the present embodiment shown in FIG. 21 and the partial circuit of the seventh embodiment of the present invention shown in FIG. 18 is that a dummy current sampling circuit 94 is added to the current output terminal of the DAC 80. As the channel selection signals for selecting the current sampling circuit in the register array 60 and the current output circuit 90, the selection signals of channel 1 and channel n are generated by the control signal generation circuit 70a, and SELR1, SELC1, SELRn, and SELCn are generated by the control signal generation circuit 70a, respectively. It is a point.
[0140]
FIG. 22 is a timing chart showing the operation of the partial circuit of the current output type driving circuit of the present embodiment shown in FIG. Hereinafter, the operation of this partial circuit will be described with reference to FIGS. 21 and 22.
As shown in FIG. 22, in this embodiment, a dummy cycle is provided. After the latch pulse LATCH is input, writing to the current sampling circuit of channel 1 does not start immediately, but during the dummy cycle, current is not taken into the true channel, and the dummy current sampling circuit 94 Apply current to Further, even after the current is taken into the last channel, the channel on the register array 60 side is fixed until the next latch pulse LATCH is input.
[0141]
In the current output type drive circuit of the present embodiment, when the load pulse LOAD, the latch pulse LATCH, and the start pulse START are input, many circuits operate simultaneously inside the drive circuit, and thus there is a possibility that the circuits may affect each other. In some cases, writing of current to the current sampling circuit of channel 1 may deviate from an original current value corresponding to input image data. In this embodiment, by providing a dummy cycle, the effect on the output current of channel 1 can be reduced.
[0142]
Further, in the output circuit 90, after the bank switching is performed, the current is immediately taken into the channel 1 and not immediately after the channel 2. For this reason, the drain voltage at the time of reading remains in the transistor of the current sampling circuit of channel 1, and the drain voltage of the transistor of the current sampling circuit in channel 2 and thereafter is the power supply voltage V_DDBack to. Due to this difference, the current value taken into the current sampling circuit at the time of writing to the channel 1 deviates from the actual current value.
[0143]
In order to solve this problem, in the present embodiment, a dummy cycle is provided. First, after the latch pulse LATCH is input, the channel selection signal SELR1 on the register array side is activated (for example, high level) by the control signal generation circuit 70a. ), The image data corresponding to channel 1 is selected in the register array 60, and is input to the decoder of the DAC 80 via the buffer 64. The DAC 80 outputs a current corresponding to the input channel 1 image data. At this time, the dummy selection signal DUM is held in the active state (high level) by the control signal generation circuit 70a. For this reason, the dummy current sampling circuit 94 is controlled to an operation state, and the converted current output from the DAC 80 is taken in by the dummy current sampling circuit 94.
[0144]
Next, as shown in FIG. 22, the dummy selection signal DUM is switched to the inactive state (low level), and accordingly, the selection signal SELC1 on the current output side is held in the active state (high level). In response, dummy current sampling circuit 94 is controlled to a non-operating state. At this time, in the current output circuit 90a, in the bank selected by the enable signals OE0 and OE1 of the first bank or the second bank, the output current of the DAC 80 is taken into the current sampling circuit corresponding to the channel 1.
[0145]
Select signals corresponding to each channel up to channel n are sequentially generated by the control signal generation circuit 70a, and sequentially output to the register array 60 and the current output circuit 90a. In channel n, as shown in FIG. 22, selection signals SELRn and SELCn for controlling channel selection of the register array 60 and the current output circuit 90a, respectively, are generated.
[0146]
In the register array 60, the image data of the n-th channel is selected according to the selection signal SELRn, and is input to the decoder of the DAC 80 via the buffer 64. The DAC 80 outputs a current corresponding to the input image data of the n-th channel.
On the other hand, in the current output circuit 90a, the current sampling circuit corresponding to the channel n is controlled to the operating state in accordance with the selection signal SELCn, and the current output from the DAC 80 is taken into the current sampling circuit and held.
[0147]
As shown in FIG. 22, the selection signal SELRn output to the register array 60 is kept in the active state (high level) until the next latch pulse LATCH is input. While the selection signal SELRn is held at the high level, the register array 60 outputs the n-th channel image data to the decoder of the DAC 80. Therefore, the DAC 80 continuously outputs the current corresponding to the image data of the n-th channel that is output last.
[0148]
In the control signal generation circuit 70a, after the selection signal SELCn of the n-channel value is switched to the inactive state (low level), the dummy selection signal DUM is held in the active state. Therefore, a current corresponding to the n-th channel image data output from the DAC 80 is supplied to the dummy current sampling circuit 94 of the current output circuit 90a.
[0149]
When the next latch pulse LATCH is input, the control signal generation circuit 70a switches the n-th channel selection signal SELRn to an inactive state, and switches the first channel selection signal SELR1 to an active state. Therefore, in the register array 60, the image data of channel 1 is selected and output to the decoder of the DAC 80. The DAC 80 outputs a current corresponding to the input channel 1 image data. At this time, since the dummy selection signal DUM is kept in the active state, the output current from the DAC 80 is output to the dummy current sampling circuit 94 in the current output circuit 90a.
[0150]
As described above, in the current output type driving circuit of the present embodiment, when the load pulse LOAD, the latch pulse LATCH, and the like are input, the dummy selection signal DUM is held in the active state by the control signal generation circuit 70a. In response, in current output circuit 90a, the current output from DAC 80 is output to dummy current sampling circuit 94. Therefore, when a load pulse LOAD, a latch pulse LATCH, or the like is input and an error may occur in the output current of the DAC 80, the output of the DAC 80 is output to the dummy current sampling circuit without being taken into the current sampling circuit. The accuracy of the current output to the load can be improved.
[0151]
Ninth embodiment
FIG. 23 is a configuration diagram showing a ninth embodiment of the current output type driving circuit according to the present invention. The current output type driving circuit of this embodiment has substantially the same configuration as the current output type driving circuit of the present invention shown in FIG. 14 except for the current output circuit portion. FIG. 23 shows the configuration of the current output circuit 90b in the present embodiment. In the following description, only the current output circuit 90b in the present embodiment will be described, and for the other components, refer to the description of the above-described seventh embodiment of the present invention.
[0152]
As shown in FIG. 23, the current output circuit 90b according to the present embodiment includes a first bank 91, a second bank 92, a current output transistor array 93, and current switching transistors 95-1 and 95-2. I have. Among them, the current switching transistors 95-1 and 95-2 are newly added portions in the present embodiment, and the other partial circuits correspond to those of the current output circuit of the seventh embodiment shown in FIG. It is the same as the constituent part.
[0153]
As shown in FIG. 23, the current switching transistor 95-1 is connected between the current output terminal of the DAC 80 and the input terminal of each current sampling circuit of the first bank 91. The enable signal OE0 is applied to the gate of the transistor 95-1. On the other hand, the current switching transistor 95-2 is connected between the current output terminal of the DAC 80 and the input terminal of each current sampling circuit of the second bank 92. The enable signal OE1 is applied to the gate of the transistor 95-2.
[0154]
In the current output circuit 90b of the present embodiment having the above-described configuration, the current switching transistors 95-1 and 95-2 operate as switches that turn on / off according to the enable signals OE0 and OE1. For example, when the enable signal OE0 is at a high level, the current switch 95-1 is turned on. At this time, since the first bank 91 is controlled to the operation mode, the current output from the DAC 80 is supplied to the first bank 91 via the current switching transistor 95-1. In the first bank 91, the current sampling circuits corresponding to the channels 1 to n sequentially operate according to the selection signals SEL1 to SELn, and the output current of the DAC 80 is taken in by each current sampling circuit.
[0155]
Next, when the enable signal OE1 is at a high level, the current switching transistor 95-2 is turned on. On the other hand, at this time, since the enable signal OE0 is held at the low level, the current switching transistor 95-1 is turned off. At this time, since the second bank 92 is controlled to the operation mode, the current output from the DAC 80 is supplied to the second bank 92 via the current switching transistor 95-2. In the second bank 92, the current sampling circuits corresponding to the channels 1 to n sequentially operate according to the selection signals SEL1 to SELn, and the output current of the DAC 80 is taken in by each current sampling circuit.
[0156]
As described above, in the current output circuit 90b of the present embodiment, the current switching transistor 95-1 is provided between the current output terminal of the DAC 80 and the first bank 91, and the current output terminal of the DAC 80 and the second bank 92 , A current switching transistor 95-2 is provided. ON / OFF of the current switching transistors 95-1 and 95-2 is controlled by enable signals OE0 and OE1. When the first bank 91 is in the operation mode, the current switching transistor 95-1 is turned on, the output current of the DAC 80 is supplied to the current sampling circuit of the first bank 91, and the second bank 92 operates. In the mode, the current switching transistor 95-2 is controlled to be turned on, and the output current of the DAC 80 is supplied to the current sampling circuit of the second bank 92. By providing the current switching transistors 95-1 and 95-2 on the current output side of the DAC 80, the load capacity seen from the output side of the DAC is reduced, and the time required for writing is reduced, so that more channels are connected. It becomes possible.
In addition, in order to branch the output current of the DAC 80, the channel is selected by taking a logical product (AND) of a plurality of selection signals, and the channel is branched not by the enable signals OE0 or OE1, but by a part of the channel selection signals. You may.
[0157]
Tenth embodiment
FIG. 24 is a configuration diagram showing a tenth embodiment of the current output type driving circuit according to the present invention. The current output type driving circuit of this embodiment has substantially the same configuration as the current output type driving circuit of the present invention shown in FIG. 14 except for the current output circuit portion. FIG. 24 shows only the configuration of the current output circuit 90c in the present embodiment. In the following description, only the current output circuit 90c in the present embodiment will be described, and other components will be omitted.
[0158]
As shown in FIG. 24, the current output circuit 90c according to the present embodiment includes a first bank 91, a second bank 92, a current output transistor array 93, and a current mirror circuit 96. Among them, the current mirror circuit 96 is a part newly added in the present embodiment, and the other partial circuits are the same as the corresponding components of the current output circuit of the seventh embodiment shown in FIG. is there.
[0159]
The current output circuit 90c of the present embodiment is different from the current output circuit 90b of the ninth embodiment of the present invention shown in FIG. 23 in that the output current of the DAC in the current output circuit 90c of the present embodiment is changed by a current switching transistor. Instead, it is folded using the current mirror circuit 96 and supplied to the current sampling circuits of the first bank 91 and the second bank 92.
[0160]
As shown in FIG. 24, in the current output circuit 90c of the present embodiment, the current mirror circuit 96 is formed by the resistance elements 96-1, 96-2, 96-3 and the transistors 96-4, 96-5, 96-6. It is configured. The gates of the transistors 96-4, 96-5, and 96-6 are commonly connected, and further connected to the source of the transistor 96-4. Drains of transistors 96-4, 96-5, 96-6 and power supply voltage V_DDAre connected to the resistance elements 96-1, 96-2, and 96-3, respectively. A conversion current corresponding to the image data is output to the source of the transistor 96-4 by a DAC 80 (not shown).
[0161]
In the above-described current mirror circuit 96, the output current of the DAC 80 is returned to the sources of the transistors 96-5 and 96-6, respectively. That is, a current corresponding to the output current of the DAC 80 is output from the sources of the transistors 96-5 and 96-6. The output current of the transistor 96-5 is supplied to the current sampling circuit of each channel of the first bank 91, and the output current of the transistor 96-6 is supplied to the current sampling circuit of each channel of the second bank 92.
[0162]
As described above, in the current output circuit 90c of the present embodiment, the output current of the DAC 80 is fed back to the current sampling circuits of the first bank 91 and the second bank 92 using the current mirror circuit 96. By providing a plurality of output lines of the current mirror circuit, the load capacity of each line is reduced, and the time required for writing to the current sampling circuit is reduced, so that more channels can be connected. In the embodiment, the current mirror circuit is shown to be composed of a resistance element and a MOS transistor. However, a current mirror circuit of another form such as a cascode type to which a bias voltage is applied may be used, and a bipolar transistor may be used instead of the MOS transistor. What was used may be used. Preferably, in order to reduce the output load of the DAC and increase the speed, a gate voltage or a base voltage may be generated via a source follower circuit without connecting a MOS transistor or a bipolar transistor with a diode.
[0163]
Eleventh embodiment
FIG. 25 is a configuration diagram showing an eleventh embodiment of the current output type driving circuit according to the present invention.
FIG. 25 shows a current output type driving circuit according to the present invention, which includes register arrays 60-1 and 60-2, a control signal generation circuit 70, DACs 80-1 and 80-2, and current output circuits 90-1 and 90-2. 3 shows a configuration of a partial circuit.
[0164]
In the partial circuit of this embodiment, the control signal generation circuit 70 includes two adjacent groups of register arrays 60-1, 60-2, DACs 80-1, 80-2, and current output circuits 90-1, 90-2. Control. That is, the control signal generation circuit 70 generates control signals such as the channel selection signals SEL1, SEL2,..., SELn, the clock signals CK1, CK2, the enable signals OE0, OE1, and the two groups of register arrays, DACs, and currents, respectively. Output to the output circuit.
[0165]
As shown in the partial circuit of this embodiment, the control signal generation circuit can be reduced in circuit layout area by being shared by two adjacent groups of register arrays, DACs, and current output circuits. Also, digital noise generated by the control signal generation circuit itself can be reduced to some extent.
[0166]
Twelfth embodiment
26 to 28 are diagrams showing a twelfth embodiment of the current output type driving circuit according to the present invention.
FIG. 26 is a circuit diagram showing a configuration of a frequency dividing circuit 100 which is a component of the current output type driving circuit. FIG. 27 shows a channel selection signal according to the frequency division output of the frequency dividing circuit shown in FIG. FIG. 3 is a block diagram showing a control signal generation circuit 70 that generates enable signals OE0 and OE1 and clock signals CK1 and CK2. FIG. 28 is a waveform diagram showing a waveform of a control signal output by control signal generating circuit 70.
[0167]
As shown in FIG. 26, the frequency dividing circuit 100 includes frequency dividers 102 and 104, a clock enable circuit 106, a programmable frequency divider 108, and an n-time counter 110.
As shown in the figure, the load pulse LOAD, the reset signal RESET, the latch pulse LATCH, the basic clock signal MCLK, the frequency division ratio control data DIV, and the half frequency control signal HALF are input to the frequency dividing circuit 100.
[0168]
The two-frequency divider 102 divides the load pulse LOAD by two and outputs a frequency-divided signal as an enable clock signal OECLK.
The clock enable circuit 106 outputs a counter clear signal CNTCLR according to the latch pulse LATCH and the output signal of the counter 110 for n times.
The frequency divider 102 and the clock enable circuit 106 are reset by a reset signal RESET.
[0169]
The ２ divider 104 outputs the basic clock MCLK to a ＣＬＫ divider and a divided signal to a programmable divider 108.
Programmable frequency divider 108 divides the frequency-divided clock signal input from frequency divider 104 by a desired frequency division ratio based on frequency divider ratio control data DIV and half frequency control signal HALF, and outputs a counter clock signal. CNTCLK is output.
As shown in FIG. 26, the frequency divider ratio control data DIV is i-bit data DIV0,..., DIVi-1, and controls the frequency division ratio of the programmable frequency divider 108. In this embodiment, a programmable frequency divider that can be set every 0.5 frequency division is used in order to enable fine setting. However, a programmable frequency divider that can be set every normal frequency division may be used. A form without a frequency divider may be used.
[0170]
The n-time counter 110 counts the counter clock signal CNTCLK input from the programmable frequency divider 108 and outputs a flag signal indicating that the count has reached a predetermined count number n to the clock enable circuit 106.
As shown in FIG. 26, the 2 frequency divider 104, the programmable frequency divider 108, and the n-time counter 110 are cleared by a counter clear signal CNTCLR output from the clock enable circuit 106.
[0171]
In the frequency dividing circuit 100 having the above-described configuration, the enable clock OECLK, the counter clear signal CNTCLR, and the counter clock signal CNTCLK are supplied according to the load pulse LOAD, the reset signal RESET, the latch pulse LATCH, and the basic clock signal MCLK input from the outside. It is generated and supplied to the control signal generation circuit 70. Then, the control signal generation circuit 70 generates a channel selection signal, an output enable signal, a clock signal, and the like for controlling the register array, the DAC, and the current output circuit, according to the signal input from the frequency division circuit 100.
[0172]
FIG. 27 is a block diagram showing an input signal and an output signal of the control signal generation circuit 70. As shown, the control signal generation circuit 70 receives an enable clock OECLK, a counter clear signal CNTCLR, and a counter clock signal CNTCLK generated by the frequency dividing circuit shown in FIG.
[0173]
As shown in FIG. 27, the control signal generation circuit 70 generates channel selection signals SEL1 to SELn, enable signals OE0 and OE1, and clock signals CK1 and CK2, respectively.
[0174]
FIG. 28 is a waveform diagram showing a part of the input signal and the output signal of the frequency dividing circuit 100 and the control signal generating circuit 70 of the present embodiment.
As shown in the figure, the frequency divider circuit 100 generates a counter clock signal CNTCLK in accordance with the latch pulse LATCH and the basic clock signal MCLK. The counter clock signal CNTCLK is output to the control signal generation circuit 70 together with an unillustrated enable clock signal OECLK and a counter clear signal CNTCLR. The control signal generation circuit 70 generates channel selection signals SEL1, SEL2,..., SELn. As illustrated, the channel selection signals SEL1 to SELn are sequentially output for each cycle of the counter clock signal CNTCLK. That is, the pulse interval of the channel selection signals SEL1 to SELn is determined by the period of the counter clock signal CNTCLK supplied by the frequency divider 100. Therefore, in the frequency dividing circuit 100, the pulse width (sampling time) of the channel selection signals SEL1 to SELn can be controlled by controlling the cycle of the counter clock signal CNTCLK.
[0175]
The counter clock signal output from the programmable frequency divider 108 is set by appropriately setting the frequency division ratio control data DIV input to the generated programmable frequency divider 108 by using the frequency dividing circuit 100 of the present embodiment. By controlling the frequency (period) of CNTCLK, the sampling time can be controlled.
[0176]
The writing time of the current sampling circuit assigned to one channel changes according to the number of pixels of the display panel driven by the current output type driving circuit. Therefore, it is necessary to control the sampling time of the channel selection signals SEL1 to SELn according to the number of pixels of the display panel to be driven. In the present embodiment, since the frequency divider 100 is provided with the programmable frequency divider 108, the frequency division ratio control data DIV appropriately set according to the number of pixels of the display panel is input to the programmable frequency divider 108. Thus, the cycle of the output counter clock signal CNTCLK can be controlled. Therefore, the selection signals SEL1 to SELn generated by the control signal generation circuit 70 in response to the counter clock signal CNTCLK have a sampling time optimal for a desired number of pixels.
[0177]
As described above, by using the frequency dividing circuit 100 of the present embodiment, it is possible to easily cope with the number of pixels of the display panel to be driven and to easily design the current output side driving circuit.
[0178]
Thirteenth embodiment
FIG. 29 is a diagram showing a thirteenth embodiment of the current output type driving circuit according to the present invention.
FIG. 29 shows an example of a shield of an input line of a write current of a current sampling circuit constituting a current output circuit of a current output type driving circuit of the present invention.
[0179]
The current input line of the current sampling circuit is connected to a current output line of the DAC 80 (not shown). With this input line, the output current of the DAC 80 is input to each of the current sampling circuits of the first bank 91 and the second bank 92.
Even if a coupling capacitance of only a few fF exists between the input line and the digital signal line, crosstalk of several tens of mV occurs in the current input line due to the voltage fluctuation of the digital signal line. As shown in Equation 5, the effective hold voltage V of the current sampling circuit_eff1And V_eff2Takes a considerably small voltage of several hundred mV. For this reason, even a crosstalk of several tens of mV may greatly affect the hold voltage of the current sampling circuit.
[0180]
In the current output type driving circuit of the present embodiment, the power supply voltage V_DDShielded with a wiring layer that is biased to
In the present embodiment, the current sampling circuit uses the power supply voltage V_DDIs used to hold the voltage between the drain and the gate of the transistor and write the output current of the DAC._DDShield with a conductive layer biased to The current sampling circuit is, for example, a GND potential V_SSWhen writing the output current of the DAC by holding the voltage based on the reference voltage, the shield wiring layer of the current input line is connected to the GND potential V_SSBias.
[0181]
According to the present embodiment, the intersection of the current input line and the digital signal wiring of each current sampling circuit of the current output circuit, the intersection of the current input line and the output line, or the position where these signal lines run in parallel And the power supply voltage V_DDAlso, the GND potential V_SSShielding with a biased conductive layer can prevent coupling due to parasitic capacitance between signal lines, reduce the effect of crosstalk on the hold voltage of the current sampling circuit, and improve the accuracy of current writing.
[0182]
Fourteenth embodiment
FIG. 30 is a diagram showing a fourteenth embodiment of the current output type driving circuit according to the present invention.
FIG. 30 shows another shield example of the write current input line of the current sampling circuit constituting the current output circuit of the current output type driving circuit of the present invention.
[0183]
In the thirteenth embodiment described above, the power supply voltage V is set at the intersection of the current input line of the current sampling circuit and another digital signal wiring or output line._DDOr GND potential V_SSIs shielded by a conductive layer that is biased in the following manner. In the present embodiment, the conductive layer has a more three-dimensional structure to improve the shielding effect.
[0184]
In the current sampling circuit constituting the current output type driving circuit of the present embodiment, the effective hold voltage obtained by subtracting the threshold voltage of the transistor is several hundred mV. If signal lines are provided, crosstalk may occur, which may affect the voltage held by the capacitor.
[0185]
In this embodiment, as shown in FIGS. 30A to 30D, the electrode on the hold node side is surrounded by a three-dimensional shield formed by a conductive layer and a side wall connected to the conductive layer. The conductive layer and the side wall are biased to a predetermined potential. The conductive layer forming the shield is formed of, for example, a metal wiring layer as illustrated.
[0186]
As described above, according to the current output type driving circuit of the present embodiment, in the current sampling circuit, the electrode of the capacitor for holding the gate voltage of the transistor is surrounded by the three-dimensional shield including the conductive layer and the side wall, and The layers are biased to a predetermined voltage. For this reason, the effect of the shield is improved, the influence of crosstalk between the capacitance element and the digital wiring near the capacitor can be reduced, and the accuracy of the hold voltage of the current sampling circuit is improved. Further, even if the amount of current flowing through the power supply line or the GND line at the time of writing the current and the amount of current flowing through the power supply line or the GND line at the time of reading the current change, the power supply voltage or the GND voltage of each current sampling circuit changes, and the hold voltage is not changed. The VGS is held because the variation is correctly added to the data. Therefore, the accuracy of current writing and reading can be improved, and the driving current output by the current sampling circuit can be made more accurate.
[0187]
【The invention's effect】
As described above, according to the present invention, using a current sampling (current sampling) circuit having sufficient current output accuracy, the current sampling circuit is provided with a control signal generation circuit that controls current writing in a time-sharing manner. Furthermore, by adopting a method of writing the output current of the current output type D / A conversion circuit to a plurality of current sampling circuits in a time-sharing manner, the number of D / A conversion circuits can be reduced and a multi-bit DAC can be laid out. It becomes possible.
Further, according to the present invention, it is possible to simplify the distribution of the reference current in the semiconductor chip, reduce the factors that lower the current output accuracy, and provide a current output type driving circuit suitable for a high gradation organic EL display panel. There are benefits that can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a current sampling circuit according to the present invention.
FIG. 2 is a timing chart illustrating an operation of the current sampling circuit according to the first embodiment.
FIG. 3 is a circuit diagram showing a second embodiment of the current sampling circuit according to the present invention.
FIG. 4 is a timing chart illustrating an operation of the current sampling circuit according to the second embodiment.
FIG. 5 is a circuit diagram showing a third embodiment of the current sampling circuit according to the present invention.
FIG. 6 is a circuit diagram showing an example of a fourth embodiment of the current sampling circuit according to the present invention.
FIG. 7 is a circuit diagram showing another example of the fourth embodiment of the current sampling circuit according to the present invention.
FIG. 8 is a circuit diagram showing another example of the fourth embodiment of the current sampling circuit according to the present invention.
FIG. 9 is a circuit diagram showing an example of a fifth embodiment of the current sampling circuit according to the present invention.
FIG. 10 is a circuit diagram showing another example of the current sampling circuit according to the fifth embodiment of the present invention.
FIG. 11 is a circuit diagram showing an example of a sixth embodiment of the current sampling circuit according to the present invention.
FIG. 12 is a circuit diagram showing another example of the sixth embodiment of the current sampling circuit according to the present invention.
FIG. 13 is a timing chart showing an operation of the current sampling circuit shown in FIG.
FIG. 14 is a configuration diagram showing one embodiment of a current output type driving circuit according to the present invention.
FIG. 15 is a circuit diagram showing a configuration example of a current output circuit forming a current output type driving circuit of the present invention.
FIG. 16 is a timing chart showing an operation of the current output type driving circuit of the present embodiment.
FIG. 17 is a circuit diagram showing a configuration example of a register array constituting the current output type driving circuit of the present invention.
FIG. 18 is a block diagram showing a configuration of a register array, a control signal generation circuit, a DAC, and a partial circuit including a current output circuit which constitute the current output type driving circuit of the present embodiment.
FIG. 19 is a timing chart showing an operation of a partial circuit of the current output type driving circuit of the present embodiment.
FIG. 20 is a circuit diagram showing another embodiment of the current output type driving circuit according to the present invention.
FIG. 21 is a block diagram showing a partial circuit including a register array, a control signal generation circuit, a DAC, and a current output circuit that constitute the current output type driving circuit of the present embodiment.
FIG. 22 is a timing chart illustrating an operation of a partial circuit included in the current output type driving circuit according to the embodiment.
FIG. 23 is a configuration diagram showing another embodiment of the current output type driving circuit according to the present invention.
FIG. 24 is a configuration diagram showing another embodiment of the current output type driving circuit according to the present invention.
FIG. 25 is a configuration diagram showing another embodiment of the current output type driving circuit according to the present invention.
FIG. 26 is a configuration diagram showing still another embodiment of the current output type driving circuit according to the present invention, and is a block diagram showing a configuration of a partial circuit including a frequency dividing circuit.
FIG. 27 is a block diagram showing a control signal generation circuit and its input and output signals in the current output type driving circuit according to the present invention.
FIG. 28 is a waveform diagram showing a part of input signals and output signals of a frequency dividing circuit and a control signal generating circuit in a current output type driving circuit according to the present invention.
FIG. 29 is a diagram illustrating an example of a shield of an input line of a write current of a current sampling circuit included in a current output circuit of a current output type driving circuit according to the present invention.
FIG. 30 is a diagram illustrating another shield example of the write current input line of the current sampling circuit included in the current output circuit of the current output type driving circuit according to the present invention.
FIG. 31 is a circuit diagram showing a configuration example of a current output type driving circuit using a conventional voltage-current conversion circuit.
FIG. 32 is a configuration diagram illustrating an example of a current output type driving circuit using a voltage-current conversion circuit.
FIG. 33 is a circuit diagram showing a configuration example of a current output circuit in which a current mirror circuit and a current output type DAC are combined.
34 is a block diagram showing a configuration of a current output type driving circuit using a plurality of current output circuits shown in FIG. 33.
FIG. 35 is a circuit diagram showing a configuration example of a conventional current sampling circuit.
36 is a timing chart showing a basic operation of the current sampling circuit shown in FIG.
[Explanation of symbols]
Reference Signs List 10: test circuit, 20: control circuit, 30: write circuit, 40: reference current source circuit, 50: bidirectional shift register for flag, 60: register array for image data, 70: control signal generation circuit, 80: D / A conversion circuit (DAC), 90: current output circuit, 91: first bank, 92: second bank, 93: current output transistor array, V_DD... Power supply voltage, V_SS... reference potential.

Claims (33)

A first MOS transistor having a source connected to the first power supply and a first switch circuit provided between the drain and the gate;
A first capacitor provided between the gate of the first MOS transistor and the first power supply;
A second MOS transistor having a source connected to the drain of the first MOS transistor and having a second switch circuit provided between the drain and the gate;
A second capacitor provided between the gate of the second MOS transistor and the first power supply;
A third switch circuit provided between the current input terminal and the drain of the second MOS transistor;
Two partial circuits each having a current output terminal and a fourth switch circuit provided between the drain of the second MOS transistor;
The two partial circuits are alternately controlled to a current writing mode and a current reading mode,
In the current write mode, the first, second, and third switch circuits are controlled to be turned on, the fourth switch circuit is controlled to be turned off, and the input current from the current input terminal is controlled. Accordingly, the gate voltage of the first MOS transistor is held in the first capacitor, the gate voltage of the second MOS transistor is held in the second capacitor,
In the current read mode, the first, second, and third switch circuits are controlled to be turned off, the fourth switch circuit is controlled to be turned on, and the current output terminal is used to control the current write mode. A current sampling circuit that outputs a current corresponding to the input current from the current input terminal when 2. The current sampling circuit according to claim 1, wherein in the current writing mode, the first switch circuit, the second switch circuit, and the third switch circuit are sequentially turned off. A fifth switch comprising a MOS transistor having a drain and a source connected to the gate of the first MOS transistor, and being turned on / off in reverse to the first switch circuit in accordance with a control signal applied to the gate; Circuit and
A sixth switch composed of a MOS transistor having a drain and a source connected to the gate of the second MOS transistor and being turned on / off in reverse to the second switch circuit in accordance with a control signal applied to the gate; The current sampling circuit according to claim 1, further comprising a circuit. 4. The current sampling circuit according to claim 3, wherein said first and second switch circuits are constituted by MOS transistors that are turned on / off in response to a control signal applied to a gate. 5. The current sampling circuit according to claim 4, wherein the channel width of the MOS transistor forming the fifth switch circuit is formed to be approximately half the channel width of the MOS transistor forming the first or second switch circuit. 5. The current sampling circuit according to claim 4, wherein the channel width of the MOS transistor forming the sixth switch circuit is formed to be approximately half the channel width of the MOS transistor forming the first or second switch circuit. 2. The current sampling circuit according to claim 1, wherein a channel width of said second MOS transistor is formed larger than a channel width of said first MOS transistor. 2. The current sampling circuit according to claim 1, wherein a bulk terminal of said second MOS transistor is connected to a source of said second MOS transistor. 2. The current sampling circuit according to claim 1, wherein threshold voltages of said first and second MOS transistors are formed lower than usual. 2. The current sampling circuit according to claim 1, wherein a channel width of the MOS transistor forming the second switch circuit is formed larger than a channel width of the MOS transistor forming the first switch circuit. 2. The current sampling circuit according to claim 1, wherein the second switch circuit includes an nMOS transistor and a pMOS transistor connected in parallel. The channel length of the MOS transistor forming the first switch circuit and the channel length of the MOS transistor forming the second switch circuit are formed to be larger than the channel length of the MOS transistor forming the normal logic circuit. The current sampling circuit according to claim 1. A seventh switch circuit provided between the drain of the second MOS transistor and the dummy load circuit, wherein the seventh switch circuit completes the current write mode and the current read mode 2. The current sampling circuit according to claim 1, wherein the current sampling circuit is controlled to be turned on until the start of the operation, and outputs the output current from the drain of the second MOS transistor to the dummy load circuit. At a place where the current input line connected to the current input terminal intersects with the digital signal wiring, or at a place where the digital signal wiring runs in parallel, provided between the current input line and the digital signal wiring, 2. The current sampling circuit according to claim 1, further comprising a shield layer or a shield wiring which is biased. At the point where the current input line connected to the current input terminal and the current output line connected to the current output terminal intersect or run parallel, between the current input line and the current output terminal 2. The current sampling circuit according to claim 1, further comprising: a shield layer or a shield wiring provided and biased by the first power supply. 2. The current sampling circuit according to claim 1, wherein a conductive layer biased to said first power supply voltage is formed around an electrode on a voltage holding side of said first capacitive element. 2. The current sampling circuit according to claim 1, wherein a conductive layer biased to the first power supply voltage is formed around an electrode on a voltage holding side of the second capacitor. A first current switch circuit provided between an output terminal of a D / A conversion circuit for supplying a predetermined current and the current input terminal of one of the two partial circuits;
2. The circuit according to claim 1, further comprising a second current switch circuit provided between the output terminal of the D / A conversion circuit and the current input terminal of the other of the two partial circuits. Current sampling circuit. A current mirror circuit for folding and outputting an output current of a D / A conversion circuit for supplying a predetermined current;
Of the two partial circuits, the current input terminal of one of the partial circuits is connected to one current output terminal of the current mirror circuit,
2. The current sampling circuit according to claim 1, wherein the current input terminal of the other of the two partial circuits is connected to the other current output terminal of the current mirror circuit. A current output type driving circuit that outputs a current of a plurality of channels according to input data,
A register array for holding the input data,
A current output type D / A conversion circuit for outputting a current corresponding to data held in the register array;
A current having a current output circuit having a first group of current sampling circuits and a second group of current sampling circuits that alternately operate in a current writing mode and a current reading mode in accordance with the output current of the D / A conversion circuit. Output type drive circuit. A first MOS transistor having a source connected to the first power supply and a first switch circuit provided between the drain and the gate, the first group and the second group of current sampling circuits;
A first capacitor provided between the gate of the first MOS transistor and the first power supply;
A second MOS transistor having a source connected to the drain of the first MOS transistor and having a second switch circuit provided between the drain and the gate;
A second capacitor provided between the gate of the second MOS transistor and the first power supply;
A third switch circuit provided between a current input terminal connected to a current output terminal of the D / A conversion circuit and a drain of the second MOS transistor;
21. The current output type driving circuit according to claim 20, wherein partial circuits each having a current output terminal and a fourth switch circuit provided between the drains of the second MOS transistors are provided only for the channels of the output current. . In the first and second groups of current sampling circuits, when operating in the current writing mode, the plurality of partial circuits corresponding to the respective channels sequentially operate in accordance with the output current of the D / A conversion circuit. 21. The current output type driving circuit according to claim 20, which performs writing. In the first group and the second group of current sampling circuits, the current output terminals of the respective partial circuits corresponding to the same channel are commonly connected, and between the connection point and the current output pad of the corresponding channel, 21. The current output type driving circuit according to claim 20, further comprising a current output transistor having a withstand voltage corresponding to a voltage of a load circuit to be driven. 21. The current output type driving circuit according to claim 20, wherein the control circuit sequentially outputs a channel selection signal corresponding to each of the channels according to a latch pulse supplied from the outside. The register array selects the input data corresponding to a channel selected by the channel selection signal according to the channel selection signal output by the control circuit, and outputs the input data to the D / A conversion circuit. 25. The current output type driving circuit according to 24. 21. The current output type driving circuit according to claim 20, wherein the control circuit outputs an enable signal which is held at a logic high level and a logic low level every cycle of the latch pulse in response to an externally supplied latch pulse. The first group and the second group of current sampling circuits are controlled in a current writing mode and a current reading mode according to the enable signal,
When the enable signal is at the logic high level, the first group of current sampling circuits is controlled in a current write mode, the second group of current sampling circuits is controlled in a current read mode,
27. The current of claim 26, wherein when the enable signal is at the logic low level, the second group of current sampling circuits is controlled in a current write mode and the first group of current sampling circuits is controlled in a current read mode. Output type drive circuit. The first group and the second group of current sampling circuits, when controlled in the current writing mode in accordance with the enable signal, time-divide the output current of the D / A conversion circuit, and 21. The current output type driving circuit according to claim 20, wherein a current according to a writing current is simultaneously output from each of the partial circuits when the current reading mode is controlled according to the enable signal. A dummy current sampling circuit is provided on the current output side of the D / A conversion circuit,
The output current of the D / A conversion circuit is changed from the end of the current output of the last channel to the start of the current output of the first channel among the plurality of channels in which the current output is sequentially performed. 21. The current output type driving circuit according to claim 20, wherein the current is output to the dummy current sampling circuit. 21. The current output type driving circuit according to claim 20, wherein one of the control circuits is provided for each of the plurality of adjacent D / A conversion circuits, and controls the operation of the plurality of D / A conversion circuits. 21. The current output type driving circuit according to claim 20, further comprising a frequency dividing circuit for dividing an externally supplied system clock signal and supplying the divided frequency to the control circuit. A frequency divider that divides the externally supplied system clock signal by two,
A programmable frequency divider that divides the output signal of the frequency divider by a frequency division ratio that can be set in increments of 0.5 or in increments of 1;
A counter for counting the output signal of the programmable frequency divider a predetermined number of times,
21. The current output type driving circuit according to claim 20, further comprising a clock signal generation circuit having a clock enable circuit for stopping output of a clock signal in accordance with an output signal of the counter. The control circuit is configured to control the register array, the D / A conversion circuit, and the first and second groups of current sampling according to output signals of the frequency divider, the clock enable circuit, and the programmable frequency divider. 33. The current output type driving circuit according to claim 32, which generates a control signal for controlling an operation of the current output circuit including the circuit.

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