JP7383216B2 - Shift register circuit and display device - Google Patents

Description

The present invention relates to a shift register circuit and a display device equipped with the shift register circuit.

In recent years, display devices equipped with liquid crystal display panels, organic EL display panels, etc. have been installed in various electronic devices, and the display screen has become more precise, and the area surrounding the display screen has become smaller, increasing the area occupied by the screen. The picture frames are becoming narrower.

Various circuits formed by, for example, thin film transistors (TFTs) on a substrate and wiring provided on the substrate are arranged in an area surrounding the display screen of the display device. As the resolution of display screens increases, the number of wires routed around the display screen increases, and due to the demand for narrower frames, circuits are configured to place more wires and circuits in a limited area. It has been desired to suppress the number of elements and the size of the elements.

International Publication No. 2017/069021 Special Publication No. 2008-508654 Japanese Patent Application Publication No. 2018-088301

For example, a gate line drive circuit that drives a plurality of gate lines is arranged around a display screen and includes a TFT and a shift register circuit. The shift register circuit included in the gate line driving circuit operates by boosting the voltage of the gate of an output TFT that drives a plurality of gate lines by bootstrapping. For bootstrapping, two methods have been proposed: explicitly providing a capacitor between the gate and source of the output TFT, and using parasitic capacitance occurring between the gate and source.

In addition, an output TFT and a transfer TFT (a TFT that performs input to the next stage shift register and reset to the previous stage shift register) are provided separately, and the load between output and transfer is distributed, and the output TFT is Circuits configured to reduce the load are also used.

For example, Patent Document 1 proposes a shift register circuit configuration in which the output of a transfer TFT and the output of an output TFT are separated, and a bootstrap capacitor is placed between the gate and source of the output TFT. has been done.

However, even in a configuration with a transfer TFT, if a bootstrap capacitor is placed between the gate and source of the output TFT, the output TFT boots its own gate potential while charging the load capacitance on the gate wiring. Since it is necessary to charge the battery using the strap, the state where the load on the output TFT is large cannot be resolved.

Furthermore, as the resolution of display devices progresses, the number of source lines that intersect with one gate line increases compared to before, and the capacitance that occurs between the gate line and multiple source lines is caused by fluctuations in the potential of the source line. may fluctuate significantly due to the influence of If the voltage of the bootstrap capacitor installed between the gate and source of the output TFT fluctuates due to the capacitance generated between the gate line and the source line, the operation of the shift register circuit becomes unstable and is displayed. There was a possibility that the image quality would deteriorate.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a shift register circuit and a display device that can suppress an increase in circuit scale and operate stably.

The shift register circuit according to the first aspect is a circuit that outputs an output signal from a first output terminal and a second output terminal based on a clock that periodically repeats a high level and a low level, and the clock is inputted. a clock input terminal, an output TFT whose source is electrically connected to the first output terminal, whose drain is electrically connected to the clock input terminal, and whose gate is electrically connected to the gate of the output TFT. , a transfer TFT whose source is connected to the second output terminal and whose drain is electrically connected to the drain of the output TFT, and electrically connected to the gate of the output TFT and the gate of the transfer TFT. a bootstrap capacitor connected between the first node and the gate and source of the transfer TFT; a first input terminal to which a signal for switching the voltage of the first node to a high voltage is input; a second input terminal to which a signal for switching the voltage of one node to a low voltage is input; a second node electrically connected to the clock input terminal; a gate electrically connected to the second node; a first TFT electrically connected to the first node, a gate electrically connected to the first node, a drain electrically connected to the drain of the first TFT, and a source electrically connected to the second node. a second TFT connected to the second TFT, and a low voltage is applied to the drain of the first TFT and the drain of the second TFT .

Further, in the shift register circuit according to the first aspect, a second clock input terminal to which a second clock is input which periodically repeats a high level and a low level so as not to become high level at the same time as the clock, and a gate. a first pull-down TFT electrically connected to the second clock input terminal and having a source electrically connected to the first output terminal; a first pull-down TFT having a gate electrically connected to the second clock input terminal; a second pull-down TFT electrically connected to the second output terminal; a third pull-down TFT whose gate is electrically connected to the second node; and whose source is electrically connected to the first output terminal; a fourth pull-down TFT electrically connected to the second node and having a source electrically connected to the second output terminal, and a low voltage is applied to the drains of the first to fourth pull-down TFTs. Ru.
Further, in the shift register circuit according to the first aspect, the output TFT and the transfer TFT include amorphous silicon or an oxide semiconductor (IGZO).

A display device according to a second aspect includes a display section including a plurality of display pixels arranged in a matrix, a gate line arranged along a row in which the plurality of display pixels are arranged, and a gate line in which the plurality of display pixels are arranged. a source line arranged along a column, and a gate drive circuit that drives the gate line, and the gate drive circuit includes a circuit in which the shift register circuit according to any one of the first embodiments is connected in multiple stages. .

According to the present invention, it is possible to provide a shift register circuit and a display device that can suppress an increase in circuit scale and operate stably.

FIG. 1 is a diagram schematically showing a configuration example of a display device according to a first embodiment. FIG. 2 is a diagram schematically showing a configuration example of the shift register circuit shown in FIG. 1. In FIG. FIG. 3 is a diagram schematically showing a configuration example of the unit shift register circuit shown in FIG. 2. In FIG. FIG. 4 is a diagram for explaining an example of the operation of the unit shift register circuit shown in FIG. 3. FIG. 5 is a diagram showing an example of a modeled unit shift register circuit. FIG . 6 is a diagram showing an example of the relationship between the arrangement of the bootstrap capacitor and the voltage response of the gate nodes of the transfer TFT and the output TFT. FIG. 7 is a diagram schematically showing a unit shift register circuit of a first comparative example. FIG. 8 is a diagram schematically showing a unit shift register circuit of a second comparative example. FIG. 9 is a diagram schematically showing a unit shift register circuit of a third comparative example. FIG. 10 is a diagram for explaining the effects of the shift register circuit and display device of the embodiment. FIG. 11 is a diagram schematically showing a configuration example of a unit shift register circuit included in the shift register circuit of the second embodiment. FIG. 12 is a diagram schematically showing a configuration example of a gate driver circuit driven by an 8-phase clock. FIG. 13 is a diagram showing an example of drive timing of the gate driver circuit shown in FIG. 12.

Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions, proportions, etc. of each drawing are not necessarily the same as those in reality. Further, even when the same parts are shown in two drawings, the relationships and ratios of the dimensions may be different. In particular, some of the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is is not specified. In the following description, elements having the same functions and configurations will be denoted by the same reference numerals, and duplicate description will be given only when necessary.

(First embodiment)
FIG. 1 is a diagram schematically showing a configuration example of a display device according to a first embodiment.
The display device of this embodiment includes a display panel 100 and a control circuit 200 that controls the operation of the display panel 100. The control circuit 200 is a circuit that controls the operation of the display panel 100 based on image data input from the outside. The display panel 100 includes, for example, an array substrate (not shown), a counter substrate (not shown) disposed opposite to the array substrate, and a liquid crystal layer LQ held between the array substrate and the counter substrate. It is a liquid crystal display panel equipped with

The array substrate includes, for example, pixel electrodes PE formed corresponding to a plurality of pixels PX arranged in a matrix, and a plurality of gate lines G1, G2 arranged along the rows in which the plurality of pixel electrodes PE are arranged. ...GN, a plurality of source lines S1, S2, ...SM arranged along the columns in which a plurality of pixel electrodes PE are arranged, gate lines G1, G2, ...GN, and source lines S1, S2, ...SM. A pixel switch SP arranged near each of the intersecting positions, a gate line drive circuit GD that drives the plurality of gate lines G1, G2, ... GN, and a source line that drives the plurality of source lines S1, S2, ... SM. A drive circuit SD is provided. The gate line drive circuit GD includes a shift register circuit 10. The shift register circuit 10 generates drive signals for gate lines G1, G2, . . . , GN.

The counter substrate includes a common electrode CE facing a plurality of pixel electrodes PE. Note that the common electrode CE may be arranged on the array substrate so as to face the plurality of pixel electrodes PE, for example, with an insulating layer interposed therebetween.

The pixel switch SP is, for example, a thin film transistor, and in each of the plurality of pixels PX, the gate of the pixel switch SP is electrically connected to the corresponding gate line G (or is formed integrally with the gate line G), and the pixel switch SP The source of the pixel switch SP is electrically connected to the corresponding source line S (or formed integrally with the source line S), and the drain of the pixel switch SP is electrically connected to the corresponding pixel electrode PE (or formed integrally with the pixel electrode PE). formed).

When the gate lines G1, G2, ...GN are sequentially driven by the gate line drive circuit GD, a high-level voltage is applied to the gate of the corresponding pixel switch SP, and conduction occurs between the source and drain of the pixel switch SP, and the pixel A predetermined voltage is applied from the corresponding source lines S1, S2, . . . SM to the pixel electrode PE via the switch SP.

FIG. 2 is a diagram schematically showing a configuration example of the shift register circuit shown in FIG. 1. In FIG.
The shift register circuit 10 includes a plurality of unit shift register circuits SR1, SR2,...SRn (n=N). The unit shift register circuits SR1, SR2,...SRn are connected in multiple stages, and one of the unit shift register circuits SR1, SR2,...SRn is connected to each of the gate lines G1, G2,...Gn.

The unit shift register circuits SR1, SR2,...SRn have a first clock input terminal to which the clock ClkA is input, a second clock input terminal to which the clock ClkB is input, and a first input terminal to which the start signal V is input. , a second input terminal to which the reset signal RST is input, a first output terminal connected to the gate lines G1, G2,...Gn, a second output terminal connected to the unit shift register circuit of the next stage, and a second output terminal connected to the unit shift register circuit of the next stage; and a third output terminal connected to the stage shift register circuit.

The clocks ClkA and ClkB are signals common to the plurality of unit shift register circuits SR1, SR2, . . . SRn, and are signals that periodically repeat a high level and a low level.
For example, the shift register circuit SRk receives the signal (V_OUT) output from the previous stage shift register circuit SR (k-1) as the start signal V, and the signal (V_OUT) output from the subsequent stage shift register circuit SR (k+1). V_OUT) is input as the reset signal RST.

FIG. 3 is a diagram schematically showing a configuration example of the unit shift register circuit shown in FIG. 2. In FIG.
Since the plurality of unit shift register circuits SR1, SR2, .

The unit shift register circuit SRn includes a high potential side TFTM2, a low potential side TFTM5, a transfer TFTM3b, an output TFTM3, pull-down TFTM4, M4b, a bootstrap capacitor Cbt, a node (first node) An, It is equipped with a pseudo inverter circuit. The pseudo inverter circuit includes a first TFTM6, a second TFTM7, a capacitor CA, and a node (second node) Bn.

In this embodiment, the plurality of TFTs included in the unit shift register circuit SRn include crystalline silicon, and may include a semiconductor layer formed of, for example, amorphous silicon or an oxide semiconductor (IGZO), or may include a semiconductor layer formed of polysilicon. It may also include a formed semiconductor layer.

The gate of the high potential side TFTM2 is electrically connected to the input terminal (V_in) of the start signal V. A high voltage VGH is applied to the drain of the high potential side TFTM2, and the source is electrically connected to the gate of the output TFTM3 and the transfer TFTM3b.

The gate of the low potential side TFTM5 is electrically connected to the input terminal (RST_in) of the reset signal RST, the low voltage VGL (=Vss) is applied to the drain of the low potential side TFTM5, and the source is used for output. It is electrically connected to the gate of TFTM3 and the gate of transfer TFTM3b.

The gate of the transfer TFT M3b is electrically connected to the gate of the output TFT M3, and is also electrically connected to the source of the high potential side TFTM2, the source of the low potential side TFTM5, and the pseudo-inverter circuit. The drain of the transfer TFT M3b is electrically connected to the drain of the output TFT M3 and the input terminal of the clock ClkA (first clock input terminal). The source of the transfer TFT M3b is electrically connected to the output terminal (second output terminal) of the start signal V to the next stage unit shift register circuit and the output terminal (third output terminal) to the previous stage unit shift register circuit. are doing. A bootstrap capacitor Cbt is electrically connected between the gate and source of the transfer TFT M3b.

The gate of the output TFT M3 is electrically connected to the gate of the transfer TFT M3b, and is also electrically connected to the source of the high potential side TFTM2, the source of the low potential side TFTM5, and the pseudo-inverter circuit. The drain of the output TFT M3 is electrically connected to the drain of the transfer TFT M3b and the input terminal of the clock ClkA (first clock input terminal). The source of the output TFT M3 is electrically connected to an output terminal (first output terminal) that outputs a drive signal for the gate lines G1, G2, . . . Gn.

The gate of the pull-down TFTM4b is electrically connected to the input terminal of the clock ClkB (second clock input terminal). A low voltage Vss (=VGL) is applied to the drain of the pull-down TFTM4b. The source of the pull-down TFTM4b is electrically connected to the output terminal (second output terminal) of the start signal V to the next-stage unit shift register circuit.

The gate of the pull-down TFTM4 is electrically connected to the input terminal of the clock ClkB (second clock input terminal). A low voltage Vss (=VGL) is applied to the drain of the pull-down TFTM4b. The source of the pull-down TFTM4b is electrically connected to an output terminal (first output terminal) that outputs a drive signal for the gate lines G1, G2, . . . Gn.

When the clock ClkB is at high level, the pull-down TFTM4, M4b conducts between the source and drain, and the output voltage to the gate lines G1, G2,...Gn and the next stage unit shift register circuit becomes low level (=Vss). Retained.

The gate of the first TFTM6 is electrically connected to the source of the second TFTM7, and is also electrically connected to the input terminal of the clock ClkA (first clock input terminal) via the capacitor CA. A low voltage Vss (=VGL) is applied to the drain of the first TFTM6. The source of the first TFTM6 is electrically connected to the gate of the output TFTM3 and the transfer TFTM3b. The first TFTM6 changes the potential of the node An toward the low voltage VGL (=Vss) potential when the potential of the node Bn is at a high level (VGH).

The gate of the second TFTM 7 is electrically connected to the gate of the output TFTM 3 and the gate of the transfer TFTM 3b. A low voltage Vss (=VGL) is applied to the drain of the second TFTM7. The source of the second TFTM7 is electrically connected to the gate of the first TFTM6, and is also electrically connected to the input terminal of the clock ClkA (first clock input terminal) via the capacitor CA. The second TFTM7 changes the potential of the node Bn toward the low voltage VGL (=Vss) when the potential of the node An is at a high level (VGH).

The capacitor CA is placed in place of the diode-connected TFT, and can prevent output from becoming unstable due to deterioration of the diode-connected TFT. As mentioned above, the capacitor CA is used in place of a diode-connected TFT, and does not need to have a large capacity. Even if the capacitor CA is used, it is necessary to prevent the circuit scale of the shift register circuit from increasing. It is something that can be done.

The first TFTM 6, the second TFTM 7, and the capacitor CA are circuits for stabilizing the voltages at the gates of the output TFTM 3 and the transfer TFTM 3b.

FIG. 4 is a diagram for explaining an example of the operation of the unit shift register circuit shown in FIG. 3.
Here, an example of clocks ClkA and ClkB, which are input signals, a start signal V, and a reset signal RST, a voltage Va of a node An, a voltage Vb of a node Bn, and an output voltage V_OUT is shown.

The node An is a node electrically connected to the gate of the output TFTM 3 and the transfer TFTM 3b, and is a node to which a voltage for controlling the output of the unit shift register circuit SRn is applied.

Node Bn is a node electrically connected to the gate of the first TFTM 6 and the source of the second TFTM 7, and is provided to stabilize the voltage of the node An.

The clock ClkA and the clock ClkB are signals that do not go high at the same time, but periodically switch between high and low levels.

When the clock CLKA is at a low level and the start signal V is at a high level, a high voltage VGH is applied to the node An. In this state, the clock CLB becomes high level, and the output voltage V_OUT is maintained at the low voltage VGL. At this time, conduction occurs between the source and drain of the second TFTM 7, and the low voltage VGL (=Vss) is applied to the node Bn.

Subsequently, the start signal V becomes low level, and the source and drain of the high potential side TFT M2 become non-conductive. After that, when the clock ClkA becomes high level, a high level voltage is applied to the drain of the transfer TFT M3b and the drain of the output TFT M3, and the voltage of the bootstrap capacitor Cbt increases accordingly. Since one end of the bootstrap capacitor Cbt is electrically connected to the gate of the transfer TFTM3b and the gate of the output TFTM3, the voltage of the node An increases as the voltage of the bootstrap capacitor Cbt increases. As a result, conduction occurs between the sources and drains of the transfer TFTM 3b and the output TFTM 3, and the output voltage V_OUT and gate drive signal G_OUT become high level.

When the clock ClkA becomes low level, the voltage of the bootstrap capacitor Cbt drops, and the voltage of the node An also drops accordingly, so that the sources and drains of the transfer TFTM 3b and the output TFTM 3 become non-conductive.

When the clock ClkA becomes low level, the output voltage V_OUT and the gate drive signal G_OUT become the low level potential (VGL) of the clock ClkA. Subsequently, when the clock ClkB and the reset signal RST become high level , conduction occurs between the source and drain of the low potential side TFTM5, and the low voltage VGL (=Vss) is applied to the node An.

(effect)
Next, an example of the effects of the shift register circuit and display device of this embodiment will be described.
FIG. 5 is a diagram showing an example of a modeled unit shift register circuit.
In FIG. 5, R1 is the on-resistance of the transfer TFTM 3b, R2 is the on-resistance of the output TFTM 3, C1 is the capacitance between the gate and source of the transfer TFTM 3b (the capacitance of the bootstrap capacitor Cbt), and C2 is the capacitance between the gate and source of the output TFTM 3 (the capacitance of the bootstrap capacitor Cbo), C3 is the capacitive load at the output end of the transfer TFTM 3b, and C4 is the capacitive load at the gate output end. That is, C3 is the capacitance obtained by adding the connection wiring capacitance to the gate capacitance of the high potential side TFTM2 and the low potential side TFTM5, and C4 corresponds to the gate wiring capacitance (=C_out).

In the above model circuit, the voltage at the gate node An of the transfer TFT M3b and the output TFT M3 is Va, and how does the transient response of this node voltage Va depend on the capacitance of the bootstrap capacitor Cbt and the bootstrap capacitor Cbo? We considered whether this would change.

Here, a first comparative example (C1<<C2) in which a bootstrap capacitor Cbo is connected between the gate and source of the output TFT, and a bootstrap capacitor Cbo is connected between the gate and source of the output TFT, and A second comparative example (C1=C2) in which a bootstrap capacitor Cbt is connected between the gate and source of the transfer TFT, and a third comparative example (C1>) in which a bootstrap capacitor Cbt is connected between the gate and source of the transfer TFT. >C2), the changes in the transient response of the node voltage Va will be compared.

FIG. 7 is a diagram schematically showing a unit shift register circuit of a first comparative example.
FIG. 8 is a diagram schematically showing a unit shift register circuit of a second comparative example.
FIG. 9 is a diagram schematically showing a unit shift register circuit of a third comparative example. Note that the unit shift register circuit shown in FIG. 3 corresponds to the configuration of the third comparative example.

In the model circuit shown in FIG. 5, the node voltage Va can be expressed by the following formula.
In the above formula, Vgl is the low voltage at the gates of the transfer TFTM 3b and output TFTM 3, Vgh is the high voltage at the gates of the transfer TFTM 3b and output TFTM 3, and Vghl is the difference between the high voltage and low voltage of the gates. τ1 and τ2 are time constants.

According to the above formula, there are two time constants, τ1 and τ2, which determine the transient response characteristics of the node voltage Va, and the difference between them depends on the difference in output load. In other words, when the bootstrap capacitor Cbo is connected between the gate and source of the output TFT M3 whose output load corresponds to the gate wiring capacitance (first comparative example and second comparative example), the transient response characteristic of the node voltage Va is It depends on the charging capacity of TFTM3.

On the other hand, if the bootstrap capacitor Cbt is provided only on the transfer TFTM 3b side as in the third comparative example, the output load of the transfer TFTM 3b is smaller than that of the output TFTM 3, and the node voltage Va is charged quickly. It will be done.

FIG. 6 is a diagram showing an example of the relationship between the arrangement of the bootstrap capacitor and the voltage response of the gate nodes of the transfer TFT and the output TFT.
In this example, for example, R1 is set to 150 kΩ, R2 is set to 25 kΩ, C3 is set to 0.5 pF, C4 is set to 80 pF, Vgh is set to 16 V, Vgl is set to -12 V, and C1 + C2 is fixed at 2.8 pF. When the relationship is changed, the initial value of the node voltage Va is set to 16V (=Vgh), and the process of increasing the node voltage Va to 2Vgh−Vgl=44V is shown.

According to the example shown in FIG. 6 , there was a tendency that the response of the node voltage Va became faster as C1 became larger, and the response of the node voltage Va became slower as C2 became larger.
From the above, it is clear that the bootstrap capacitor Cbt is connected only to the transfer TFTM3b as in the third comparative example, rather than the case where the bootstrap capacitor Cbo is connected to the output TFTM3 as in the first and second comparative examples. In this case, the response speed of the node voltage Va becomes faster, and it becomes possible to realize a shift register circuit that responds faster.

Furthermore, since the potential of the source of the output TFT M3 is affected by potential fluctuations of the source line via the gate lines G1, G2,...Gn, the bootstrap capacitor Cbo connected between the gate and source of the output TFT M3 is also affected. It will be affected by potential fluctuations of the source line.

FIG. 10 is a diagram for explaining the effects of the shift register circuit and display device of the embodiment.
For example, gate lines G1, G2, . . . Gn are arranged across a plurality of pixels PX, and intersect with a plurality of source lines S1, S2, . Therefore, the potentials of the gate lines G1, G2, . In the above circuit model, C4 is described as a static capacitor (=C_out), but in reality, the potential of this capacitor C4 fluctuates under the influence of the inter-wiring capacitance C_line.

From the above, when a bootstrap capacitor is connected to the output TFTM3, the charge charged to the gate wiring capacitance (=C_out) will also be charged to the bootstrap capacitor in proportion to Cbo due to the relationship Q=CV. Therefore, the influence of fluctuations in the inter-wiring capacitance C_line on the node voltage Va of the unit shift register circuit SRn becomes large.

On the other hand, when the bootstrap capacitor Cbt is connected to the transfer TFTM 3b, the load capacitance at the output end is small, so that the influence of the load capacitance at the output end on the shift register circuit can be reduced.

As described above, according to the shift register circuit of this embodiment, stable operation can be achieved without increasing the number of elements configuring the circuit. That is, according to the present embodiment, it is possible to provide a shift register circuit and a display device that can suppress an increase in circuit scale and operate stably.

Furthermore, in the shift register circuit of this embodiment, since the transfer circuit and the output circuit are separated, it is possible to suppress the function of the gate driver GD from being affected by noise or load from the gate output terminal.

(Second embodiment)
Next, a shift register circuit and a display device according to a second embodiment will be described in detail with reference to the drawings. In addition, in the following description, the same code|symbol is attached|subjected to the structure similar to the above-mentioned 1st Embodiment, and description is abbreviate|omitted.

FIG. 11 is a diagram schematically showing a configuration example of a unit shift register circuit included in the shift register circuit of the second embodiment.

The shift register circuit of this embodiment differs from the above-described first embodiment in that it further includes pull-down TFTM8 and M8b and in the configuration of node Bn.

The gate of pull-down TFTM8 is electrically connected to the input terminal of clock ClkA via node Bn and capacitor CA. A low voltage Vss (=VGL) is applied to the drain of the pull-down TFTM8. The source of the pull-down TFTM8 is electrically connected to the output terminal of the gate drive signal.

The gate of pull-down TFT M8b is electrically connected to the input terminal of clock ClkA via node Bn and capacitor CA. A low voltage Vss (=VGL) is applied to the drain of the pull-down TFTM8b. The source of the pull-down TFT M8b is electrically connected to the output terminal of the output signal to the next stage unit shift register circuit.

By providing the pull-down TFTM8 and M8b, when the voltage at node Bn is at a high level, the voltage at the output terminal of the unit shift register circuit SRn becomes a low voltage Vss, and the voltage at the output terminal during all periods other than the selection period. can be set to a low voltage Vss. Thereby, the operation of the shift register circuit can be made more stable.

The shift register circuit of this embodiment is the same as the first embodiment described above except for the above configuration, and can obtain the same effects as the first embodiment described above.

Although the number of circuit elements constituting the unit shift register circuit SRn shown in FIG. 11 is larger than that in the first embodiment, the pull-down TFTs M8 and M8b have leakage current at the output terminal when operating in a predetermined temperature environment, for example. It is only necessary to prevent the output of the shift register circuit from becoming unstable due to the current flowing, and there is no need to use large-sized elements. Therefore, the shift register circuit of this embodiment does not increase the circuit scale.

Further, in the display device of this embodiment, the gate driver GD may be configured to operate using a plurality of (three or more) clocks.
FIG. 12 is a diagram schematically showing a configuration example of a gate driver circuit driven by an 8-phase clock.
FIG. 13 is a diagram showing an example of drive timing of the gate driver circuit shown in FIG. 12.

In this case, the gate driver GD includes a first shift register circuit that drives the 4x-3rd gate line G (4x-3) and a second shift register circuit that drives the 4x-2nd gate line G (4x-2). It includes a register circuit, a third shift register circuit that drives the 4x-1st gate line G (4x-1), and a fourth shift register circuit that drives the 4x-th gate line G (4x). .

The first shift register circuit receives the clock Clk1 as the clock ClkA, and the clock ClkX1 as the clock ClkB.
The clock Clk2 is input as the clock ClkA, and the clock ClkX2 is input as the clock ClkB to the second shift register circuit.

Clock Clk3 is inputted as clock ClkA, and clock ClkX3 is inputted as clock ClkB to the third shift register circuit.
The clock Clk_4 is input as the clock ClkA, and the clock ClkX4 is input as the clock ClkB to the fourth shift register circuit.

For example, when driving gate lines G1 to G1280, each shift register circuit sequentially drives 320 gate lines.
Even with the configuration of the gate driver GD described above, the same effects as in the first embodiment and the second embodiment described above can be obtained.

Further, the present invention is not limited to the above-described embodiments as they are, and in the implementation stage, the constituent elements can be modified and embodied without departing from the spirit of the invention. Moreover, various inventions can be formed by appropriately combining the plurality of components disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiments. Furthermore, components of different embodiments may be combined as appropriate.

10...Shift register circuit, SR1...Unit shift register circuit, 100...Display panel, 200...Control circuit, G1-GN...Gate line, S1-SM...Source line, M2...High potential side TFT, M3...Output TFT, M3b...Transfer TFT, M4...Pulldown TFT (first pulldown TFT), M4b...Pulldown TFT (second pulldown TFT), M5...Low potential side TFT, M8...Pulldown TFT (third pulldown TFT), M8b...Pulldown TFT (4th pull-down TFT), Cbt...bootstrap capacitor

Claims (4)

A circuit that outputs an output signal from a first output terminal and a second output terminal based on a clock that periodically repeats high level and low level,
a clock input terminal into which the clock is input;
an output TFT whose source is electrically connected to the first output terminal and whose drain is electrically connected to the clock input terminal;
a transfer TFT having a gate electrically connected to the gate of the output TFT, a source connected to the second output terminal, and a drain electrically connected to the drain of the output TFT;
a first node electrically connected to the gate of the output TFT and the transfer TFT;
a bootstrap capacitor connected between the gate and source of the transfer TFT;
a first input terminal into which a signal for switching the voltage of the first node to a high voltage is input;
a second input terminal receiving a signal for switching the voltage of the first node to a low voltage;
a second node electrically connected to the clock input terminal;
a first TFT whose gate is electrically connected to the second node and whose source is electrically connected to the first node;
a second TFT having a gate electrically connected to the first node, a drain electrically connected to the drain of the first TFT, and a source electrically connected to the second node;
A shift register circuit , wherein a low voltage is applied to the drain of the first TFT and the drain of the second TFT . a second clock input terminal to which a second clock is input that periodically repeats a high level and a low level so as not to become high level at the same time as the clock;
a first pull-down TFT whose gate is electrically connected to the second clock input terminal and whose source is electrically connected to the first output terminal;
a second pull-down TFT whose gate is electrically connected to the second clock input terminal and whose source is electrically connected to the second output terminal;
a third pull-down TFT whose gate is electrically connected to the second node and whose source is electrically connected to the first output terminal;
a fourth pull-down TFT whose gate is electrically connected to the second node and whose source is electrically connected to the second output terminal;
2. The shift register circuit according to claim 1 , wherein a low voltage is applied to the drains of the first to fourth pull-down TFTs. 2. The shift register circuit according to claim 1, wherein the output TFT and the transfer TFT include amorphous silicon or an oxide semiconductor. a display section including a plurality of display pixels arranged in a matrix;
a gate line arranged along a row in which a plurality of the display pixels are arranged;
a source line arranged along a column in which the plurality of display pixels are arranged;
A gate drive circuit that drives the gate line,
A display device, wherein the gate drive circuit includes a circuit in which the shift register circuit according to claim 1 is connected in multiple stages.