JP2004064262A - Differential amplifier circuit and reception circuit for radio controlled watch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit with a small current and a low occupation area the gain of which at a desired frequency is increased and which is very useful for amplification purpose for a device such as a radio controlled watch which receives a radio wave of a single carrier frequency. <P>SOLUTION: The differential amplifier circuit (10) is configured to include a pair of transistors (Q1, Q2) and a pair of loads provided to an output terminal (VOUT) side of a pair of the transistors. The loads of the differential amplifier circuit are constituted by connecting in parallel a pair of capacitors (CL1, CL2) acting like the impedance for deciding a gain at a desired frequency, and a pair of current sources (Q6, Q7, Q8) for canceling the bias currents of the differential amplifier circuit, and a pair of high resistance resistors (Rb1, Rb2) for deciding output bias voltage connected in parallel. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit that amplifies a signal of a specific frequency with low voltage, low current consumption, and small area. The differential amplifier circuit of the present invention is suitable, for example, for a radio-controlled timepiece receiving integrated circuit.
[0002]
[Prior art]
The receiving integrated circuit for a radio-controlled timepiece amplifies an input signal having a wide dynamic range (about 110 dB) from about 0.3 μVrms (root mean square value) to about 80 mVrms depending on the strength of radio waves in the receiving area, the performance of the antenna, and the like. -It is necessary to detect. For this reason, in the radio-controlled timepiece receiving integrated circuit, a fixed gain amplifier composed of several stages of amplifier circuits is arranged in front of the detection circuit in the same manner as a gain control amplifier (GCA) composed of several stages of amplifier circuits. Is becoming more common. Further, since the carrier of the signal for the radio clock is a single frequency with high accuracy (for example, in Japan, 40 kHz or 60 kHz in the radio clock reception radio wave provided by the Communications Research Laboratory, Japan), noise removal is performed. For the purpose, it is common to insert a crystal filter between the GCA and the fixed gain amplifier.
[0003]
FIG. 5 shows a configuration of a general conventional receiving circuit block for a radio controlled watch. 5, 50 is a receiving antenna, 51 is a GCA amplifier, 52 is a fixed gain amplifier, 53 is a crystal filter, 54 is a rectifier, 55 is a low-pass filter (LPF), 56 is a peak / bottom detector, and 57 is an AGC (automatic gain control). Gain control), 58 is a comparator, and 59 is an output.
[0004]
Each of the components of the GCA amplifier 51 and the fixed gain amplifier 52 includes a differential circuit having a resistive load _RL as shown in FIG. 6 because of its circuit simplicity, gain accuracy, noise removal, and the like. An amplifier circuit 60 is generally used. In an integrated circuit, the characteristics of _two transistors Tr ₁ and Tr ₂ close to each other can be made equal, so that the differential amplifier circuit 60 that eliminates the influence of drift such as temperature is often used. Differential amplifier using a pair of transistors Tr ₁ and Tr ₂ of the same characteristics, each of the base is used as the input terminal for the input _{V i1} and _{V i2,} between respective collectors for the output _{V o1} and _{V o2} Output terminal. And, the emitters of the pair of transistors Tr ₁ and Tr ₂ are connected to a common bias supply, each collector is connected to a power supply via a load resistor R _L of the same size. The ratio of the change in the output voltage difference _V o1 _{-V o2} of for the difference _V i1 changes in _{-V i2} of the two input voltages of the differential amplifier circuit 60 is called the differential gain G, as in the following expression (1) Is represented by
[0005]
_{G = | (V o1 -V o2} ) / (V i1 -V i2) | = g m * R L (1)
Here, _{R L} is the transistor Tr ₁ and Tr ₂ of the collector is in connection a load resistor size, _{g m has} a relationship of g _{m =} qI e / 2kT. Here, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, _{I e} is a double emitter current of a pair of transistors Tr ₁ and Tr ₂ (also referred to as a bias current). Thus, the differential gain G is determined by the load resistance _RL and the magnitude of both emitter currents _Ie . Since the values of the bias current _Ie and the load resistance _RL flowing through the differential amplifier circuit 60 are design parameters that are relatively easy to control, the circuit 60 can easily obtain a desired gain. Often used.
[0006]
[Problems to be solved by the invention]
However, in the load resistance type differential amplifier circuit shown in FIG. 6, when trying to increase the differential gain G, one of the following methods must be used. {Circle around (1)} Increase the circuit current _Ie . (2) Increase the load resistance _RL . {Circle around (3)} Increase the number of stages of the amplifier circuit.
[0007]
While it is desired to reduce the current consumption of the integrated circuit, it is practically difficult to increase the circuit current in (1). The measure of increasing the load resistance in (2) increases the chip area and is disadvantageous in cost. Further, there is a concern that the parasitic capacitance of the resistor increases and affects the frequency characteristics. The measure (3) brings about both an increase in current consumption and an increase in chip area.
[0008]
As described above, the resistance load type differential amplifier, which has been widely used, has various difficulties as described above when trying to obtain low current consumption and high gain.
[0009]
On the other hand, Japanese Patent Application Laid-Open No. Hei 9-181569 discloses a phase shifter circuit constituted by a differential amplifier circuit having a load composed of an impedance passive element using a parallel connection of a resistor and a capacitor. This impedance passive element is used to obtain an output signal having a phase difference of exactly 90 degrees by using the passive element in combination with a feedback section having the same resistance and capacitance connected in parallel. Therefore, the configuration of this conventional example is not for increasing the differential gain G. Further, the magnitude of the resistor incorporated in parallel with the conventional impedance passive element affects the magnitude of the impedance Z at a desired operating frequency. Therefore, there is the problem (2).
[0010]
Japanese Patent Laying-Open No. 2001-251150 discloses a differential amplifier circuit having an impedance load. However, this conventional example does not disclose the use of a capacitance as an impedance load to increase the gain of a specific frequency.
[0011]
SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit and a radio-controlled timepiece receiving circuit which solve the above problem, improve the controllability of gain at a specific frequency, and can be realized with low current consumption and small area. It is in.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a differential amplifier circuit according to the present invention is a differential amplifier circuit having a pair of transistors and a pair of loads provided on an output terminal side of the pair of transistors. In order to determine the output bias voltage, a pair of capacitors as impedances for determining a gain at a desired frequency as a load of the differential amplifier circuit, a pair of current sources for canceling a bias current of the differential amplifier circuit, And a pair of high resistances are added in parallel.
[0013]
Further, the present invention described in claim 2 has a configuration in which a current source for flowing a current through a high resistance to determine an output bias voltage is separately provided in addition to the configuration of claim 1.
[0014]
Furthermore, the present invention described in claim 3 is a configuration having a pair of MOS transistors as a pair of high resistances for determining the output bias voltage of claim 1 or 2.
[0015]
Further, a receiving circuit for a radio-controlled timepiece according to a fourth aspect of the present invention has a configuration in which the receiving section includes the differential amplifier circuit according to any one of the above-described aspects.
[0016]
[Action]
According to the differential amplifier circuit of the present invention described in claim 1, the capacitance C (Farad) has an impedance Z (ohm) having a magnitude of 1 / 2πfC at a frequency f (Hertz). The magnitude of the capacitance C for a desired frequency f can be selected so that the impedance Z is substituted for _RL in the above equation (1) to obtain a desired gain G. As can be expressed by the relational expression of Z = 1 / 2πfC, the magnitude of the impedance Z due to the capacitance C is larger as the capacitance C is smaller, that is, as the shape of the capacitance C is smaller. As a result, the magnitude of Z substituted for R _L in the above equation (1) increases as the capacitance C decreases for the same frequency f. For this reason, according to the differential amplifier circuit of the present invention, a large gain G can be obtained with a small capacitance C, which is suitable for miniaturization. The pair of current sources cancel the bias current flowing through the differential amplifier circuit. The pair of high resistors determines the output bias voltage of the differential amplifier circuit according to the current flowing through them.
[0017]
According to the differential amplifier circuit of the present invention described in claim 2, since a separate current source for flowing a current through the high resistance determining the output bias voltage is provided, a desired output bias voltage can be easily set.
[0018]
According to the differential amplifier circuit of the third aspect of the present invention, since a pair of MOS transistors is used as a pair of high resistances for determining the output bias voltage of the first or second aspect, the occupied area is reduced. The size can be reduced and the size can be reduced.
[0019]
According to a fourth aspect of the present invention, there is provided a receiver for a radio-controlled timepiece according to the present invention, wherein the differential amplifier circuit according to any one of the first to fourth aspects is provided in a receiving unit, so that miniaturization and low power consumption are promoted. At the same time, high-accuracy reception sensitivity that is hardly affected by temperature changes can be obtained.
[0020]
Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a differential amplifier circuit 10 according to a first embodiment of the present invention. The differential amplifier circuit 10 has a pair of NPN transistors Q1 and Q2 having the same characteristics, the input terminal VIN is connected to the base of the pair of transistors Q1 and Q2, and the output terminal VOUT is connected to the collector. Each is connected. One end of a pair of capacitors CL1 and CL2 of the same size for an impedance load for determining a gain G at a predetermined frequency f is connected to a connection point between the collector and the output terminal of the pair of transistors Q1 and Q2. The other ends of the pair of capacitors CL1 and CL2 are connected to a power supply. Further, one end of a pair of high resistances Rb1 and Rb2 for determining the output bias voltage of the output terminal is connected to a connection point between the collector and the output terminal of the pair of transistors Q1 and Q2, respectively. And the other end of Rb2 are connected to a power supply. The emitters of the pair of transistors Q1 and Q2 are commonly connected, and are connected to the collector of an NPN transistor Q5. The emitter of the transistor Q5 is grounded.
[0022]
The transistor Q5, together with the NPN transistor Q3, forms a current mirror for mirror-flowing the reference current Iref, and the base of the transistor Q5 is connected to the collector and the base of the transistor Q3. Further, the transistor Q3 forms a current mirror for mirroring and flowing the same reference current Iref together with the NPN transistor Q4, and the base of the transistor Q4 is connected to the base and the collector of the transistor Q3. The emitters of transistors Q3 and Q4 are grounded. The mirror ratio of the two current mirrors can be changed by changing the number of transistors or the emitter size, but here, for simplicity, each is set to 1: 1. The collector of the transistor Q3 is connected to a power supply through which the reference current Iref flows.
[0023]
The collector of the transistor Q4 is connected to the collector of the PNP transistor Q6. The PNP transistor Q6 mirrors the current Iref mirrored by the transistor Q4 to a PNP transistor Q7 and a PNP transistor Q8 which are current sources for canceling the bias current Iref of the differential amplifier circuit 10. is there. The base of the transistor Q7 is connected to the base and the collector of the transistor Q6. The collector of the transistor Q7 is connected to a connection point between the collector and the output terminal of the transistor Q1. The emitter of the transistor Q7 is connected to a power supply. The base of the transistor Q8 is connected to the base and the collector of the transistor Q6. The collector of the transistor Q8 is connected to a connection point between the collector and the output terminal of the transistor Q2. The emitter of the transistor Q8 is connected to a power supply.
[0024]
As described above, in the differential amplifier circuit of FIG. 1, the load capacitances CL1 and CL2, the high resistances Rb1 and Rb2, and the transistors Q7 and Q8 are connected between the power supply and the collectors of the pair of transistors Q1 and Q2 constituting the output terminal. Are connected in parallel.
[0025]
Since a current of Iref / 2 flows through each of the pair of transistors Q1 and Q2, it is necessary to use two transistors in parallel as the transistor Q6 or to double the emitter size of the transistors Q7 and Q8. There is. Thereby, the bias current Iref supplied from Q5 can be almost cancelled.
[0026]
However, in the case of a bipolar transistor, since a base current exists, the current flowing through each of the transistors Q7 and Q8 is about 96% of Iref / 2 (when hfe is 100). On the other hand, since a current of Iref / 2 flows through the pair of transistors Q1 and Q2, approximately 4% of the difference flows through the resistors Rb1 and Rb2. The resulting voltage can be used as the output bias voltage. The magnitudes of the resistors Rb1 and Rb2 need to be large enough not to affect the impedances Z = 1 / 2πfCL1 and Z = 1 / 2πfCL2 of the capacitors CL1 and CL2 at the desired frequency.
[0027]
According to the differential amplifier circuit 10 of the first embodiment of the present invention shown in FIG. 1, the impedance Z of the capacitors CL1 and CL2 at the desired frequency f is Z = 1 / 2πfCL1 and Z = 1 / 2πfCL2. The capacitances CL1 and CL2 are selected so that the desired magnitude of the impedance Z is obtained at this frequency f, and the magnitude of the desired impedance Z is determined by the above equation (1). by substituting the of R _L, it is possible to obtain the gain G of the desired size.
[0028]
A second embodiment of the present invention will be described with reference to FIG. In order to avoid repetition, the same parts as those in the first embodiment described with reference to FIG.
[0029]
The differential amplifier circuit 20 according to the second embodiment shown in FIG. 2 includes NPN transistors Q9 and Q10 each having a collector connected to the output terminal VOUT. The bases of the transistors Q9 and Q10 are commonly connected to the bases of the transistors Q3, Q4 and Q5, respectively. The emitters of transistors Q9 and Q10 are grounded via resistors R1 and R2, respectively. The transistors Q3 and Q9, the resistor R1, the transistors Q3 and Q10, and the resistor R2 each constitute a Widlar-type current mirror circuit. This circuit is often used when it is desired to mirror a very small current with respect to the reference current Iref. The mirror ratio can be determined by changing R1 and R2. The currents generated by the transistors Q9 and Q10 flow through the resistors Rb1 and Rb2, respectively, to generate an output bias voltage at the output terminal VOUT. Therefore, the second embodiment is different from the first embodiment in that the voltage generated at the resistors Rb1 and Rb2 by the difference current between the transistors Q1 and Q7 and the transistors Q2 and Q8 alone is not sufficient as the output bias voltage. A new current source dedicated to the output bias voltage is added.
[0030]
A third embodiment of the present invention will be described with reference to FIG. To avoid repetition, the same parts as those in the first and second embodiments described in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
[0031]
In the differential amplifier circuit 30 according to the third embodiment shown in FIG. 3, a long channel length and a narrow channel width are used instead of the pure resistors Rb1 and Rb2 used in the first and second embodiments. And the on-resistance of p-channel MOS (metal-oxide-silicon) transistors MP1 and MP2 having As described above, the resistance values of the high resistances Rb1 and Rb2 for determining the output bias voltage need to be large enough not to affect the impedance of the capacitors CL1 and CL2 at the desired frequency f. If this is made with pure resistors Rb1 and Rb2, the purpose is to contradict the purpose of reducing the resistance area. Therefore, if an appropriate gate bias voltage (VB) is applied using the on-resistance of the MOS transistors MP1 and MP2 having a long channel length and a narrow channel width, it is possible to produce a large resistance with a small area. As a result, the area of the differential amplifier circuit can be reduced.
[0032]
FIG. 4 shows a simulation of the magnitude of the gain G of the differential amplifier circuit according to the third embodiment shown in FIG. 3 with respect to the frequency f. In the differential amplifier circuit of FIG. 3, the capacitances CL1 and CL2 are 1 pF, the channel width W / channel length L of the MOS transistors MP1 and MP2 is 2.5 μm / 140 μm, and the current of the differential circuit is 1 μA. I do. The curves (1), (2), and (3) in FIG. 4 are obtained by changing the on-resistances of the MOS transistors MP1 and MP2 by + 100% and -50% with respect to (1). This variation does not affect the gain G (about 36 dB) determined by the impedance Z of the capacitors CL1 and CL2 at a desired frequency f (here, 40 kHz). From the figure, it can be seen that the gain at the desired frequency f is determined by the impedance Z of the capacitors CL1 and CL2, and is not affected by variations in the MOS transistors MP1 and MP2 as resistors. In other words, in the semiconductor process, the capacitance can be formed with higher precision than the resistance, and the resistance at the desired frequency f can be realized with high precision by the high-precision capacitance. Since there is no resistor and the bias voltage is determined, a precision error of the resistor is allowed.
[0033]
The area occupied by the capacitors CL1 and CL2 and the MOS transistors MP1 and MP2 of the third embodiment shown in FIG. 3 is sufficiently small. If the conventional differential amplifier circuit 60 shown in FIG. 6 has the same gain with a resistance load RL (about 100 kΩ) corresponding to the same area occupied by the capacitors CL1 and CL2 and the MOS transistors MP1 and MP2 of the third embodiment. When trying to obtain, the current that must be passed through the differential amplifier circuit is about 31 μA, and it is not possible to reduce the current consumption. On the other hand, in the conventional differential amplifier circuit 60 shown in FIG. 6, when trying to obtain a gain equivalent to that of the third embodiment of FIG. 3 with a current of 1 μA, the load resistance RL must be 3.1 MΩ. Rather, it takes up a considerable area.
[0034]
In the present invention, in the configuration of the above-described embodiment, the capacitors CL1 and CL2 are a pair of capacitors of the same size, but a plurality of pairs of capacitors of different sizes are provided, and the plurality of pairs are formed by using an analog switch. Switching may be performed so that the magnitude of the capacity to be a load is changed in accordance with the frequency so as to correspond to reception of a plurality of carrier wave frequencies.
[0035]
Furthermore, in the present invention, in the configuration of the above-described embodiment, a configuration in which the NPN transistor is converted to a PNP transistor, the PNP transistor is converted to an NPN transistor, and the P-channel MOS transistor is converted to an N-channel MOS transistor is also possible.
[0036]
Further, in the present invention, in the configuration of the above-described embodiment, a configuration in which the NPN transistor is converted to an N-channel MOS transistor and the PNP transistor is converted to a P-channel MOS transistor is also possible.
[0037]
In addition, the radio-controlled timepiece receiving circuit of the present invention replaces the GCA amplifier 51 and the fixed gain amplifier 52 of the radio-controlled timepiece receiving circuit shown in FIG. Is used. As described above, the differential amplifier circuit of each of the above-described embodiments is designed to achieve high-precision gain that is not easily affected by temperature changes while promoting downsizing and low power consumption as described above. It is possible to reduce the area and reduce the power consumption, and to realize high-accuracy receiving sensitivity that is hardly affected by a temperature change.
[0038]
【The invention's effect】
According to the configuration of the present invention, as described above, the effects of reducing the current consumption and reducing the area of the differential amplifier circuit according to the present invention can be understood as compared with the related art. The specific effect of the present invention is that when the impedance is increased, the value of the resistance must be increased and the shape thereof must be increased. When the shape is made smaller by making it smaller, it is brought about by effectively utilizing the point that the impedance Z = 1 / 2πfC becomes larger.
[0039]
In general, in a semiconductor process, it is also advantageous that the production of capacitance is smaller than that of resistance, and that the variation in gain of the differential amplifier circuit can be reduced. Further, the change in capacitance due to temperature change is smaller than the change in resistance due to temperature change, and the change in gain of the differential amplifier circuit due to temperature change is also small.
[0040]
As described above, according to the configuration of the present invention, it is possible to increase the gain of the differential amplifier circuit at a desired frequency with a low current and a small occupation area, and to receive a single carrier frequency radio wave such as a radio clock. It is possible to create an amplifier circuit which is very useful for amplifying a circuit. Further, it is also possible to adjust the gain of the operational amplifier circuit so as to be able to cope with a plurality of carrier frequencies by providing a number of different capacitance sizes and switching them with a switch.
[0041]
In addition, if the differential amplifier circuit of the present invention is applied to a radio-controlled timepiece receiving circuit, it is possible to reduce the area and power consumption of the radio-controlled timepiece receiving circuit, and to reduce the influence of temperature changes. Accurate receiving sensitivity can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a differential amplifier circuit according to a third embodiment of the present invention.
FIG. 4 is a diagram showing a graph of gain by simulation of the differential amplifier circuit according to the embodiment of the present invention shown in FIG. 3;
FIG. 5 is a block diagram of a conventional radio-controlled timepiece receiving circuit.
FIG. 6 shows a conventional differential amplifier circuit.
[Explanation of symbols]
10, 20, 30 Differential amplifier circuit CL1, CL2 Capacitance R1, R2 Resistance Rb1, Rb2 High resistance Q1, Q2 A pair of NPN transistors Q3, Q4, Q5, Q9, Q10 NPN transistors Q6, Q7, Q8 PNP transistors MP1, MP2 p-channel MOS transistor

Claims (4)

A differential amplifier circuit having a pair of transistors and a pair of loads provided on an output end side of the pair of transistors, wherein the pair of loads has an impedance that determines a gain of the differential amplifier circuit at a predetermined frequency. A configuration in which a pair of capacitances, a pair of current sources for canceling a bias current of the differential amplifier circuit, and a pair of high resistances for determining an output bias voltage of the output terminal are added in parallel. Having a differential amplifier circuit. 2. The differential amplifier circuit according to claim 1, further comprising a pair of current sources for flowing a current through the pair of high resistances for determining the output bias voltage. 3. 3. The differential amplifier circuit according to claim 1, wherein the pair of high resistances is a pair of MOS transistors. A receiving circuit for a radio-controlled timepiece, comprising a differential amplifier circuit according to claim 1 in a receiving unit.

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