JP2004063720A - Manufacturing method of build-up multilayer printed-wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a build-up multilayer printed-wiring board that can form a filled via whose surface is flat in a hole for via having a small diameter (100 μmϕ or less) and high aspect ratio (0.7 or more). <P>SOLUTION: A resin photosensitive layer 31 is formed on both the surfaces of a circuit board (an internal layer board) 10. A series of patterning treatments such as pattern exposure and development are made. An insulating layer 31a where the hole 32 for via is formed at a specific position is formed. A ground conductor layer is formed on the insulating layer 31a and in the hole 32 for via by electroless copper plating. By electrolytic panel plating using an electrolytic copper plating bath where an addition agent for the filled via is added with the plating substrate conductor layer as a cathode, a conductor layer 41 and the filled via 42 are formed, the conductor layer 41 is subjected to patterning treatment, second wiring layers 41a, 41b, a pad electrode 41c, and the like are formed, and the four-layer build-up multilayer printed-wiring board 100 is obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【００２０】
次に、導体層４１をパターニング処理することにより、第２配線層４１ａ、第２配線層４１ｂ及びパッド電極４１ｃ等を形成して、第２配線層４１ａ、第２配線層４１ｂ及びパッド電極４１ｃが第１配線層２１ａ及び第１配線層２１ｂとフィルドビア４２にて電気的に接続された４層のビルドアップ多層プリント配線板１００を得ることができる（図１（ｅ）参照）。
さらに必要であれば、上記工程を必要回数繰り返すことにより所望層数のビルドアップ多層プリント配線板を作製することができる。
【００２１】
【実施例】
以下、実施例により本発明を詳細に説明する。
まず、ガラス不織布にエポキシ樹脂を含浸させた絶縁基材１１の両面に１８μｍの銅箔を貼り合わせた銅張り積層板を用い、パターニング処理して第１配線層２１ａ及び第１配線層２１ｂが形成された回路基板（内層基板）１０を作製した（図１（ａ）参照）。
【００２２】
次に、回路基板（内層基板）１０の両面にアディティブ用接着剤を塗布し、乾燥して、樹脂感光層３１を形成し（図１（ｂ）参照）、パターン露光、現像等の一連のパターニング処理を行って、所定位置に５０μｍφのビア用孔３２が形成された５０μｍ厚の絶縁層３１ａを形成した（図２（ｃ）参照）。
【００２３】
次に、絶縁層３１ａ上及びビア用孔３２内を過マンガン酸溶液からなる粗化剤にて粗面化処理し、Ｐｄ等の触媒核を付与した後活性化処理を行った。
次に、無電解銅めっき浴（キューポジット２５３（商品名）：シプレイ社製）を用いて処理温度：３４℃、処理時間：３０分にて無電解銅めっきを行い、絶縁層３１ａ上及びビア用孔３２内に０．５μｍ厚のめっき下地導体層（特に、図示せず）を形成した。
【００２４】
次に、噴流式めっき装置を用いて、めっき下地導体層をカソードにしてフィルドビア用添加剤を添加してなる電解銅めっき浴を用いて、下記に示すめっき条件にて電解パネルめっきを行い、ビア用孔３２内にフィルドビア４２を、絶縁層３１ａ上に２５μｍ厚の導体層４１を形成した（図１（ｄ）参照）。
電解銅めっき浴：
ＣｕＳＯ_４　　　　２２５ｇ／リットル
Ｈ_２ＳＯ_４　　　　　５５ｇ／リットル
ＣＬ　　　　　　　６０ｍｌ／リットル
処理温度：２３℃
処理時間：１１３分
通電条件
電流密度：１．０Ａ／ｄｍ^２
ユニポーラ電流：定常時間；２０ｍｓｅｃ、休止時間；１ｍｓｅｃ
噴流式めっき装置での噴流流量：３０Ｌ／分
【００２５】
次に、導体層４１上にドライフィルム（ＡＱ２５５８（商品名）：旭化成工業社製）を加熱、転写して感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってレジストパターンを形成し、レジストパターンをエッチングマスクにして塩化第２鉄溶液を用いて導体層４１のエッチングを行い、第２配線層４１ａ、第２配線層４１ｂ及びパッド電極４１ｃ等を形成して、第２配線層４１ａ、第２配線層４１ｂ及びパッド電極４１ｃが第１配線層２１ａ及び第１配線層２１ｂとフィルドビア４２にて電気的に接続された４層のビルドアップ多層プリント配線板１００を得た（図２（ｅ）参照）。
【００２６】
ビルドアップ多層プリント配線板１００のフィルドビア４２上には窪み等は形成されておらず、ビルドアップ層３０はほぼ平坦な面が形成されていることが確認された。
【００２７】
本発明のビルドアップ多層プリント配線板の製造法を適用することにより、以下のような効果を得ることができる。
ビア用孔３２を１００μｍφ以下の小径にしても、本発明の電解銅めっき条件を採用することにより、中央部に窪みを生じない、表面が平坦なフィルドビア４２を得ることができる。
また、めっき下地導体層及びその上に析出する導体層４１が、ともに銅で形成されているため、各層界面での高い密着性が付与され、信頼性の高いフィルドビア、第２配線層及びパッド電極等を得ることができる。さらに、銅は導電性に優れるので、低抵抗のフィルドビアを得ることができる。
【００２８】
【発明の効果】
上記したように、本発明のビルドアップ多層プリント配線板の製造法を適用することにより、ビア用孔の径が１００μｍ以下であっても、表面が平坦な、密着性に優れたフィルドビアを形成でき、低コストで、高信頼性のビルドアップ多層プリント配線板を提供できる。
【図面の簡単な説明】
【図１】（ａ）〜（ｅ）は、本発明のビルドアップ多層プリント配線板の製造方法の一実施例を工程順に示す模式構成部分断面図である。
【符号の説明】
１０……回路基板（内層基板）
１１……絶縁基材
２１ａ、２１ｂ……第１配線層
３０……ビルドアップ層
３１……感光層
３１ａ……絶縁層
３２……ビア用孔
４１……導体層
４２……フィルドビア
４１ａ、４１ｂ……第２配線層
４１ｃ……パッド電極
１００……ビルドアップ多層プリント配線板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a build-up multilayer printed wiring board in which at least two or more wiring layers are formed on an insulating base via an insulating layer.
[0002]
[Prior art]
As the miniaturization, high density, and high performance of electronic devices are progressing, the demands for miniaturization, high density, and high speed of the multilayer circuit boards used therein are also increasing. There is a need for multilayer printed wiring boards.
The multilayer printed wiring board is formed by laminating a circuit board (inner layer board) and a prepreg sheet, forming a wiring layer to form a multilayer printed wiring board board, and forming an insulating layer on the circuit board (inner layer board). It is shifting to a build-up type multilayer printed wiring board in which wiring layers are alternately stacked.
[0003]
Such a build-up multilayer printed wiring board is manufactured by the following procedure.
1A to 1E show an example of a method for manufacturing a build-up multilayer printed wiring board.
First, an additive adhesive is applied to both surfaces of the circuit board (inner substrate) 10 having the first wiring layer 21a and the first wiring layer 21b formed on both surfaces of the insulating base material 11 to a thickness of several tens of μm and dried. Then, a resin photosensitive layer 31 is formed (see FIGS. 1A and 1B). Next, a series of patterning processes such as pattern exposure and development are performed on the resin photosensitive layer 31 to form an insulating layer 31a in which a via hole 32 having an inner diameter of 100 μm to 200 μm is formed at a predetermined position of the resin photosensitive layer ( FIG. 1 (c)).
[0004]
Next, after performing roughening treatment, catalyst nucleus provision and activation treatment on the inner wall of the insulating layer 31a and the via hole 32, the inner wall of the insulating layer 31a and the inner wall of the via hole 32 are formed by electroless copper plating or the like. A plating base conductor layer having a thickness of 2 to 1.0 μm is formed (not particularly shown).
Next, electrolytic panel plating is performed using the plating base conductor layer as a cathode to form a filled via 42 in the via hole and a conductor layer 41 on the insulating layer 31a (see FIG. 1D).
[0005]
Next, the second wiring layer 41a and the second wiring layer 41b are formed by patterning the conductor layer 41, and the second wiring layer 41a and the second wiring layer 41b are formed by the first wiring layer 21a and the first wiring layer. A four-layer build-up multilayer printed wiring board electrically connected to the via 21b and the filled via 42 can be manufactured (see FIG. 1E).
[0006]
[Problems to be solved by the invention]
In this type of build-up multilayer printed wiring board, there is a demand that the surface of the build-up layer 30 must be flat.
This is because, if the surface of the build-up layer 30 has irregularities, solder voids or the like may occur when performing surface mounting, thereby causing failure of each electronic component.
The largest cause of such unevenness on the surface of the build-up layer 30 is that the filling of the via hole 32 is incomplete and the center of the filled via 42 is depressed.
[0007]
However, via holes are becoming smaller and deeper as the diameter of vias is reduced and the aspect ratio is increased due to the increase in the number of layers and the density of conductor patterns in recent years. Therefore, when the filled via is formed by electrolytic panel plating, it is difficult to exchange the plating solution in the via hole, and as a result, the hole filling by the electrolytic plating is incomplete and the center of the filled via is depressed, There is a problem that voids (hollowing) occur.
[0008]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is a build-up multilayer print capable of forming a filled via with a flat surface in a via hole having a small diameter (100 μmφ or less) and a high aspect ratio (0.7 or more). An object of the present invention is to provide a method for manufacturing a wiring board.
[0009]
[Means for Solving the Problems]
In order to solve the above problems in the present invention, first, according to claim 1, each wiring of a build-up multilayer printed wiring board in which at least one wiring layer is formed on an insulating base via an insulating layer In a method for manufacturing a build-up multilayer printed wiring board, wherein a filled via for electrically connecting layers is formed by a plating method, a via hole is formed in the insulating layer having a predetermined thickness, and then the insulating layer is formed using an electroless plating bath. An underplating conductor layer is formed on the top and in the via hole, and the via hole is filled by electrolytic panel plating using an electroplating bath using a filled via additive with the plating underconductor layer as a cathode. A method of manufacturing a build-up multilayer printed wiring board characterized by having the above-described structure.
[0010]
2. The build according to claim 1, wherein the via hole has an opening diameter of 100 μm or less and an aspect ratio of 0.7 or more in the insulating layer having a thickness of 150 μm or less. This is a method for manufacturing an up-multilayer printed wiring board.
[0011]
According to a third aspect of the present invention, there is provided the method of manufacturing a build-up multilayer printed wiring board according to the first or second aspect, wherein the electrolytic plating bath is an electrolytic copper sulfate plating bath.
[0012]
Still further, in claim 4, the electrolytic panel plating is performed by using a plating facility having a jet structure and a pulse power supply having a unipolar current. The method for producing a build-up multilayer printed wiring board described in (1).
[0013]
When making a filled via of a build-up multilayer printed wiring board, if the via hole has a small diameter (100 μm or less) and a high aspect ratio (0.7 or more), the plating solution needs to be exchanged into the via hole during electrolytic plating. Therefore, it is necessary to compensate for insufficient supply of metal ions and additives in the electrolytic plating bath. In the present invention, in an electrolytic panel plating using an electrolytic plating bath using an additive for filled via, sufficient liquid agitation in a jet plating apparatus or a unipolar current using a pulse power source (the pause time in the unipolar current is a Since the ions are not attracted to the electrode, the metal ions in the bath at the time of electrolytic plating can be removed by using a random thermal diffusion motion of the metal ions, which has the effect of restoring the metal ion concentration in the diffusion layer. Additives were supplied into the via holes to further promote plating deposition.
Thus, by uniformizing the plating deposition rate between the periphery of the opening of the via hole and the bottom, the state of electrolytic deposition can be more smoothly improved, and the filled via has a flat surface. Build-up layer can be obtained.
[0014]
According to the third aspect of the present invention, since the plating base conductor layer and the filled via are both conductor layers made of copper, they are easily compatible with each other and have high adhesion, so that a highly reliable filled via can be obtained. . Further, copper has excellent conductivity, so that a low-resistance filled via can be obtained.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a build-up multilayer printed wiring board according to the present invention will be described with reference to the drawings.
1A to 1E are schematic partial cross-sectional views showing one embodiment of a method for manufacturing a build-up multilayer printed wiring board according to the present invention in the order of steps.
First, using a copper-clad laminate in which a copper foil is bonded to both sides of an insulating base material 11 in which a glass nonwoven fabric is impregnated with an epoxy resin, the copper foil is subjected to a patterning process by a subtractive process. Then, a first wiring layer 21a and a first wiring layer 21b are formed, and a circuit board (inner substrate) 10 is manufactured (see FIG. 1A).
[0016]
Next, an additive adhesive is applied to both sides of the circuit board (inner layer substrate) 10 and dried to form a resin photosensitive layer 31 (see FIG. 1B), and a series of patterning such as pattern exposure and development is performed. By performing the processing, an insulating layer 31a having a via hole 32 formed at a predetermined position is formed (see FIG. 1C).
Here, the via hole 32 is applied to a via hole having an opening diameter of 100 μm or less in an insulating layer having a thickness of 150 μm or less.
The additive adhesive is, for example, a photosensitive resin solution in which a readily soluble resin filler is dispersed in a hardly soluble epoxy resin matrix to impart photosensitivity.
Further, the via holes 32 are formed by using a photo process, but may be formed by laser processing or the like. In that case, since no photosensitivity is required, a normal insulating layer can be used as it is.
Further, the thickness of the insulating layer 31a is set to about 20 μm to 150 μm.
[0017]
Next, the surface of the insulating layer 31a and the inside of the via hole 32 are roughened with a roughening agent to form a roughened surface having fine anchor recesses.
Here, the roughening agent is a chemical that dissolves easily soluble components in the insulating layer 31, and examples thereof include solutions of chromic acid, chromate, sulfuric acid, hydrochloric acid, permanganic acid, and the like.
Further, after a catalyst nucleus such as Pd (palladium) serving as a core during electroless plating deposition is provided on the insulating layer 31a and in the via hole 32, a process of activating the catalyst nucleus is performed. At this time, the catalyst nuclei are also applied to the side surface of the via hole 32 and the bottom surface of the via hole 32.
[0018]
Next, electroless copper plating is performed in an electroless copper plating bath (Cuposit 253 (trade name): manufactured by Shipley Co., Ltd.) at a processing temperature of 30 to 40 ° C. and a processing time of 10 to 40 minutes. A plating base conductor layer (particularly not shown) is formed on the upper side and in the via hole 32. This plating base conductor layer is a so-called thin plating conductor layer, and its thickness is as extremely small as 0.1 μm to 3.0 μm.
[0019]
Next, using a jet-type plating apparatus, the electrolytic copper plating bath containing the additive for the filled via was stirred with the base conductor layer of the plating as a cathode, and further subjected to electrolysis under a unipolar current supply condition by a pulse power supply. Panel plating is performed to form a filled via 42 in the via hole and a conductor layer 41 on the insulating layer 31a (see FIG. 1D).
Here, in the electrolytic copper plating bath, it is desirable to use a filled via additive in order to grow the plating thickly in the via hole and to fill the via hole with plating.
An example of conditions for electrolytic panel plating using an electrolytic copper plating bath is described below.

[0020]
Next, by patterning the conductor layer 41, the second wiring layer 41a, the second wiring layer 41b, the pad electrode 41c and the like are formed, and the second wiring layer 41a, the second wiring layer 41b, and the pad electrode 41c are formed. A four-layer build-up multilayer printed wiring board 100 electrically connected to the first wiring layer 21a and the first wiring layer 21b by the filled via 42 can be obtained (see FIG. 1E).
If necessary, the above steps are repeated as many times as necessary to produce a build-up multilayer printed wiring board having a desired number of layers.
[0021]
【Example】
Hereinafter, the present invention will be described in detail with reference to examples.
First, a first wiring layer 21a and a first wiring layer 21b are formed by patterning using a copper-clad laminate in which 18 μm copper foil is bonded to both surfaces of an insulating base material 11 in which a glass nonwoven fabric is impregnated with an epoxy resin. Thus, a circuit board (inner layer substrate) 10 was manufactured (see FIG. 1A).
[0022]
Next, an additive adhesive is applied to both sides of the circuit board (inner layer substrate) 10 and dried to form a resin photosensitive layer 31 (see FIG. 1B), and a series of patterning such as pattern exposure and development is performed. By performing the process, an insulating layer 31a having a thickness of 50 μm and a via hole 32 having a diameter of 50 μm was formed at a predetermined position (see FIG. 2C).
[0023]
Next, the surface of the insulating layer 31a and the inside of the via hole 32 were subjected to a surface roughening treatment using a roughening agent composed of a permanganic acid solution, and a catalyst nucleus such as Pd was provided, followed by an activation treatment.
Next, using an electroless copper plating bath (Cuposit 253 (trade name), manufactured by Shipley Co., Ltd.), electroless copper plating was performed at a processing temperature of 34 ° C. and a processing time of 30 minutes, and the insulating layer 31a and the via A 0.5 μm-thick plating base conductor layer (particularly not shown) was formed in the hole 32.
[0024]
Next, using a jet plating apparatus, electrolytic panel plating was performed under the following plating conditions using an electrolytic copper plating bath obtained by adding an additive for a filled via with the plating underlying conductor layer as a cathode, and A filled via 42 was formed in the hole 32, and a conductor layer 41 having a thickness of 25 μm was formed on the insulating layer 31a (see FIG. 1D).
Electrolytic copper plating bath:
CuSO ₄ 225 g / liter H ₂ SO ₄ 55 g / liter CL 60 ml / liter Processing temperature: 23 ° C.
Processing time: 113 minutes Energizing condition Current density: 1.0 A / dm ²
Unipolar current: steady time; 20 msec, pause time; 1 msec
Jet flow rate in jet plating apparatus: 30 L / min
Next, a dry film (AQ2558 (trade name) manufactured by Asahi Kasei Kogyo Co., Ltd.) is heated and transferred onto the conductor layer 41 to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern. The conductive layer 41 is etched using a ferric chloride solution using the resist pattern as an etching mask to form a second wiring layer 41a, a second wiring layer 41b, a pad electrode 41c, etc. A four-layer build-up multilayer printed wiring board 100 in which the layer 41a, the second wiring layer 41b, and the pad electrode 41c are electrically connected to the first wiring layer 21a, the first wiring layer 21b, and the filled via 42 is obtained (FIG. 2 (e)).
[0026]
No depression or the like was formed on the filled via 42 of the build-up multilayer printed wiring board 100, and it was confirmed that the build-up layer 30 had a substantially flat surface.
[0027]
By applying the method for manufacturing a build-up multilayer printed wiring board of the present invention, the following effects can be obtained.
Even if the via hole 32 has a small diameter of 100 μmφ or less, the electrolytic via plating condition of the present invention can provide a filled via 42 having a flat surface with no depression at the center.
In addition, since the plating base conductor layer and the conductor layer 41 deposited thereon are both formed of copper, high adhesion is provided at each layer interface, and a highly reliable filled via, a second wiring layer, and a pad electrode are provided. Etc. can be obtained. Further, copper has excellent conductivity, so that a low-resistance filled via can be obtained.
[0028]
【The invention's effect】
As described above, by applying the method for manufacturing a build-up multilayer printed wiring board of the present invention, a filled via having a flat surface and excellent adhesion can be formed even when the diameter of the via hole is 100 μm or less. A low-cost, highly reliable build-up multilayer printed wiring board can be provided.
[Brief description of the drawings]
FIGS. 1A to 1E are schematic partial cross-sectional views showing one embodiment of a method for manufacturing a build-up multilayer printed wiring board according to the present invention in the order of steps.
[Explanation of symbols]
10 Circuit board (inner layer board)
11 Insulating base materials 21a and 21b First wiring layer 30 Build-up layer 31 Photosensitive layer 31a Insulating layer 32 Via hole 41 Conductor layer 42 Filled vias 41a and 41b ... Second wiring layer 41c... Pad electrode 100... Build-up multilayer printed wiring board

Claims (4)

A build-up multilayer printed wiring board in which a filled via for electrically connecting each wiring layer of a build-up multilayer printed wiring board having at least two or more wiring layers formed on an insulating base via an insulating layer is formed by plating. In the manufacturing method, after forming a via hole in the insulating layer having a predetermined thickness, a plating base conductor layer is formed on the insulating layer and on the inner wall of the via hole using an electroless plating bath. A method for manufacturing a build-up multilayer printed wiring board, characterized in that said via holes are filled by electrolytic panel plating using an electrolytic plating bath using an additive for filled vias with an underlying conductor layer as a cathode. 2. The manufacture of a build-up multilayer printed wiring board according to claim 1, wherein the via hole has an opening diameter of 100 μm or less and an aspect ratio of 0.7 or more in the insulating layer having a thickness of 150 μm or less. 3. Method. The method for manufacturing a build-up multilayer printed wiring board according to claim 1, wherein the electrolytic plating bath is an electrolytic copper sulfate plating bath. 4. The build-up multilayer printed wiring board according to claim 1, wherein the electrolytic panel plating is performed by using a plating facility having a jet structure and a pulse power supply having a unipolar current. 5. Manufacturing method.

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