JP2001291957A - Wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which is manufactured, while using a forming method for fine via hole for completely filling a hole for fine micro-via hole (having a hole diameter of <=50 μm and an aspect ratio of >=1), and to provide a producing method therefore. SOLUTION: Insulating layers 13 are formed on both the sides of an insulating substrate 11 formed with wiring layers 12a and 12b, holes 14a and 14b for via hole are formed at the prescribed positions of the insulating layers 13 by laser working, and catalyst cores are formed on the surfaces of the wiring layers 12a and 12b inside the holes 14a and 14b for via hole by substitution reaction treatment in a catalytic liquid, containing dihydric palladium ions. Copper is deposited inside the holes 14a and 14b for via hole by electroless copper plating, via holes 15a and 15b are formed, wiring layers 16a and 16b are formed on both the sides by a well-known method, and the four-layer build-up multilayered printed board can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board such as a build-up type multilayer printed wiring board and a tape carrier, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of electronic equipment, the density of wiring layers of wiring boards used has been rapidly increased. Therefore, a build-up type multilayer printed wiring board in which insulating layers and wiring layers are alternately stacked on the surface of a multilayer printed circuit board serving as a core, or a tape carrier that forms wiring layers on both sides of a tape such as a polyimide tape. In recent years, a large number of wiring boards have been produced.
Conduction between the wiring layers of these wiring boards is performed by via holes in which conductors are formed in the via hole holes. In the conventional via hole, a conductor layer made of copper was formed on the wall surface of the hole for the via hole by applying electroless copper plating and electrolytic copper plating technology, but in this method, the inside of the hole remains open. In addition, since it is difficult to form a via hole on the via hole, there is a problem that the degree of freedom in designing a wiring pattern is impaired. In addition, since air bubbles are formed inside the hole, there is a possibility that the reliability of the wiring board may be impaired, such as expansion and rupture of the air bubbles in a process such as component mounting and disconnection. Therefore, a method called a filled via in which the inside of the via hole is filled with copper so that the via hole can be stacked on the via hole and there is no risk of impairing the reliability of the wiring board is attracting attention.

[0003] A via hole is formed in a multilayer printed wiring board of a build-up type by first forming an insulating resin on a wiring layer by means such as coating and sticking, and exposing and developing the insulating resin or by laser processing. An insulating layer is formed by forming a via hole. After that, it is general that a conductive layer having a predetermined thickness is formed by electrolytic copper plating after imparting conductivity to the side surface of the via hole by catalytic treatment or the like by electroless copper plating. In the case of a tape carrier, prepare a polyimide tape with a conductor layer formed on one side, form a via hole hole by laser processing or polyimide etching from the other side, and then use a non-electrolytic copper plating for a via hole. After imparting conductivity to the side surface of the hole by catalytic treatment or the like, a conductor layer having a predetermined thickness is formed by electrolytic copper plating.

[0004]

When a filled via is formed from these wiring boards, the diameter of the via hole is 50 μm or more, and the aspect ratio (diameter / depth) is increased.
It can be satisfactorily buried in a hole having a diameter of less than 1, but it is apparent that complete burying is not performed in a fine via hole having a diameter of less than 50 μm and an aspect ratio of 1 or more. became. This is because in the case of electrolytic copper plating, the current tends to concentrate at the entrance of the fine via hole, and the entrance of the via hole is blocked before the copper is completely deposited in the via hole. .

[0005] For this reason, a method of embedding a conductor in a via-hole has been actively developed by using a special additive to prevent the entrance from being blocked, and although there is a certain effect, the via-hole is more effective. This method is not sufficient for finer patterns.

The present invention has been devised in view of the above problems, and an object is to completely fill a fine via hole (a hole diameter of 50 μm or less and an aspect ratio of 1 or more) with a conductor. It is an object of the present invention to provide a highly reliable wiring board and a method for manufacturing the same.

[0007]

In order to solve the above-mentioned problems in the present invention, in claim 1, the wiring layer is electrically connected to the wiring layer via the insulating layer, and one end of the via hole is connected to the wiring layer. In a wiring board which is closed with a wiring layer and the inside of a via hole is filled with a metal conductor, the via hole is replaced by a catalyst on the side of the insulating layer of the wiring layer portion which closes one end thereof, and is filled by electroless plating. It is characterized by being done.

According to a second aspect of the present invention, there is provided a method of manufacturing a wiring board, wherein the conductor at the bottom of the via hole is formed of a material whose bottom is closed by the conductor. It is characterized in that the via hole is filled by performing a substitution reaction with a catalyst and performing electroless plating.

[0009] In a third aspect of the present invention, in the method for manufacturing a wiring board according to the second aspect, the substitution reaction is performed using a catalyst solution containing divalent palladium ion. According to a fourth aspect of the present invention, in the method for manufacturing a wiring board according to the third aspect,
The catalyst solution containing a valence palladium ion contains at least hydrochloric acid, palladium chloride, and hydrazine hydrochloride.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a metal conductor is deposited by electroless plating on a conductor at the bottom of a via hole, for example, a copper wiring layer or a copper layer before wiring is patterned by electroless plating. The catalyst application treatment is performed in advance only on the exposed conductor at the bottom of the via hole, and preferably, a catalyst solution containing divalent palladium ion is used. This catalyst solution is composed of a solution containing at least hydrochloric acid, palladium chloride, and hydrazine hydrochloride.
0-200 mg / L, hydrochloric acid (35%) concentration 20-15
0 mL / L, hydrazine hydrochloride is 10 to 1000 mg / L
Is preferred.

Furthermore, a metal conductor is deposited from the conductor surface at the bottom of the via hole by electroless plating to form a filled via hole. Electroless plating is advantageous because it is not necessary to consider the concentration of current at the hole, which is a problem in electrolytic plating. In addition, there is no problem of film thickness variation due to uneven current distribution, and it is easy to reduce the film thickness variation.

Hereinafter, embodiments of the present invention will be described in more detail. 1A to 1D show an example of an embodiment of the present invention. First, an insulating layer 3 is formed on both surfaces of an insulating substrate 1 (see FIG. 1A) having a wiring layer 2a and a wiring layer 2b formed on both surfaces (see FIG. 1B). Next, a via hole 4a and a via hole 4b are formed at predetermined positions of the insulating layer 3 by laser processing or the like, and the via hole 4a and the via hole 4b are subjected to a substitution reaction process using a catalyst solution. Catalyst nuclei are formed on the exposed surfaces of the wiring layers 2a and 2b at the bottoms in the holes 4a and the via holes 4b (see FIG. 1 (c)). Further, electroless plating is performed to deposit a metal conductor from the surface of the wiring layer in the via hole 4a and the via hole 4b to form the via holes 5a and 5b (see FIG. 1D).

Since the purpose of the via holes 5a and 5b is to electrically connect the lower and upper wiring layers, the via hole 4a and the via hole 4b must be connected to the lower wiring layer 2a and the wiring layer 2b. Provided above,
Copper, which is a material of the wiring layer, is exposed at the bottoms of the via hole 4a and the via hole 4b. The exposed copper surfaces of the via hole holes 4a and the via hole holes 4b undergo a substitution reaction using a catalyst solution, so that conductor deposition by electroless plating starts from the surface of the wiring layer at the bottom of the hole provided with the catalyst nuclei. The via hole 5a and the via hole 5
b is formed.

In the conventional method, the catalyst application treatment is performed not only on the bottom of the hole but also on the wall surface of the via hole, so that the electroless plating grows not only from the bottom of the hole but also from the side. . In the case of electroless plating, the problem of concentration of metal conductor deposition at the entrance of the via hole is reduced as compared with electrolytic plating, but the supply rate of the plating solution component is lower at the entrance of the via hole. Due to the high temperature, the deposition rate is slightly increased, and it is inevitable that voids remain in the fine via hole.

Via hole 4a and via hole 4
As electroless plating for depositing a conductor on b, electroless copper plating is generally used from the viewpoint of electrical conductivity, but from the viewpoint of operability, considering the stability of the resin in the plating solution. Electroless Ni plating can also be used. When performing electroless plating, the solution is sufficiently agitated so that ions to be reacted are sufficiently supplied into the fine via hole. As the stirring method, a conventionally used method such as a method using air stirring or a pump circulation can be adopted. In addition, by circulating and filtering the plating solution, fine particles present in the plating solution are removed, and abnormal precipitation that occurs as a nucleus thereof is prevented.

Via hole 4a and via hole 4
b can be formed by a conventionally known method using a laser beam. Further, the inside of the via hole is cleaned by a desmear process. This is to prevent the smear remaining in the via hole from deteriorating the reliability of the connection between the layers.

Hereinafter, an example of manufacturing a multilayer printed wiring board of a build-up system using the manufacturing method of the present invention will be described. 2A to 2D show an example of manufacturing a build-up type multilayer printed wiring board using the manufacturing method of the present invention, and FIGS. 3A to 3F show the manufacturing method of the present invention. FIGS. 4A to 4F show still another example of manufacturing a build-up multilayer printed wiring board using the manufacturing method of the present invention. Shown respectively.

<Case 1> First, a wiring layer 12a and a wiring layer 12b are formed on both surfaces of an insulating substrate 11 (see FIG. 2A). Next, an insulating layer 13 is formed on both surfaces of the insulating substrate 11 on which the wiring layers 12a and 12b are formed.
Via holes 14a and 14b are formed at predetermined positions of the insulating layer 13 on the wiring layer 12a and the wiring layer 12b by laser processing, and the via holes 14a and the via holes are formed with a catalyst solution containing divalent palladium ions. 14b
Is subjected to a substitution reaction treatment to form catalyst nuclei on the surfaces of the wiring layers 12a and 12b in the via hole holes 14a and the via hole holes 14b (see FIG. 2B).

Then, copper is deposited in the via hole 14a and the via hole 14b by electroless copper plating to form the via holes 15a and 15b (see FIG. 2C). Next, a wiring layer 16a and a wiring layer 16b are formed on both surfaces by a known method, and a predetermined wiring layer 12a is formed.
a and the wiring layer 12b and the wiring layer 16a and the wiring layer 16b are electrically connected to each other via the via holes 15a and the via holes 15b to obtain a four-layer build-up multilayer printed wiring board (see FIG. 2D). Further, if necessary, by repeating the above steps, a build-up multilayer printed wiring board having a desired number of layers can be obtained.

<Case 2> First, a wiring layer 22a and a wiring layer 22b are formed on both surfaces of an insulating substrate 21 (see FIG. 3A). Next, an insulating layer 23 and a conductor layer 24 are formed on both surfaces of the insulating substrate 21 on which the wiring layers 22a and 22b are formed (see FIG. 3B). Next, the conductor layer 24 is patterned to form openings 25 for forming via holes at predetermined positions of the conductor layer 24 (see FIG. 3C).

Next, a laser beam is irradiated from the opening 25 using the conductor layer 24 as a mask, and a desmear process is performed to form a via hole 26a and a via hole 26b.
Furthermore, the via hole 26a and the via hole 26
b, a resist layer 27 is formed on the conductor layer 24 except for
The via hole 26a and the via hole 26b are replaced with a catalyst solution containing valence palladium ions to form catalyst nuclei on the surfaces of the wiring layer 22a and the wiring layer 22b in the via hole 26a and the via hole 26b. (See FIG. 3D).

Next, copper is deposited in the via hole 26a and the via hole 26b by electroless copper plating.
Via holes 28a and 28b are formed (see FIG. 3E).

Next, the resist layer 27 is peeled off, and the conductor layer 24 is patterned to form wiring layers 24a and 24b.
b and the wiring layer 24a and the wiring layer 24b
Then, a four-layer build-up multilayer printed wiring board electrically connected by the via hole 28a and the via hole 28b is obtained (see FIG. 3F). Further, if necessary, by repeating the above steps, a build-up multilayer printed wiring board having a desired number of layers can be obtained.

<Case 3> First, a wiring layer 32a and a wiring layer 32b are formed on both surfaces of an insulating substrate 31 (see FIG. 4A). Next, a copper foil with a resin layer is laminated on both sides of the insulating substrate 31 on which the wiring layer 32a and the wiring layer 32b are formed to form the insulating layer 33 and the conductor layer 34 (FIG. 4B).
reference). Next, the conductor layer 34 is subjected to a patterning process so that the opening 3 for forming a via hole is formed at a predetermined position of the conductor layer 34.
5 (see FIG. 4C).

Next, a laser is irradiated from the opening 35 using the conductor layer 34 as a mask, and desmearing is performed to form a via hole 36a and a via hole 36b. Further, the via-hole 36a and the via-hole 36b are subjected to a substitution reaction treatment with a catalyst solution containing divalent palladium ion, and the via-hole 36a and the via-hole 3 are removed.
Catalyst nuclei are formed on the surfaces of the wiring layer 32a and the wiring layer 32b in 6b (see FIG. 4D).

Next, copper is deposited in the via hole 36a and the via hole 36b by electroless copper plating.
A via hole 38a and a via hole 38b are formed (see FIG. 4E).

Next, the conductor layer 34 is patterned to form a wiring layer 34a and a wiring layer 34b, and the predetermined wiring layers 32a and 32b and the wiring layers 34a and 34a are formed.
Thus, a four-layer build-up multilayer printed wiring board electrically connected to the via hole 38a and the via hole 38b is obtained (see FIG. 4F). In addition, if necessary,
By repeating the above steps, a desired number of build-up multilayer printed wiring boards can be obtained.

The electroless plating solution for forming the via hole is not particularly limited, but is not limited to a general bath using formalin as a reducing agent in electroless copper plating, and a reducing agent such as glyoxylic acid or cobalt (II) salt. The bath used as can also be used. In the electroless Ni plating, a medium phosphorus type bath using hypophosphite as a reducing agent is easily used in terms of deposition rate, stability and the like, but a bath using boron or hydrazine as a reducing agent is also available. Can be used.

By using the manufacturing method of the present invention to manufacture a build-up type multilayer printed wiring board,
It is possible to manufacture a build-up type multilayer printed wiring board having a via hole in which a metal conductor is completely embedded in a fine via hole hole having a diameter of less than 50 μm and an aspect ratio of 1 or more.

[0030]

The present invention will be described in detail with reference to the following examples. <Embodiment 1> In the manufacturing process shown in FIGS.
First, the wiring layer 12a and the wiring layer 1 are formed on both surfaces of the insulating substrate 11.
The insulating layer 13 having a thickness of 35 μm is formed on the two-layer laminate on which the second layer 2b is formed.
Is formed, and a predetermined position of the insulating layer 13 is perforated by laser processing, desmearing and neutralization are performed.
Hole diameter 20μm, depth 35μm (aspect ratio 1.75)
Via hole 14a and hole diameter 50 μm, depth 35 μm
Via holes 14b of m (aspect ratio 0.7) were formed.

Next, a degreasing treatment was performed using sodium persulfate (10%).
0 g / L) and sulfuric acid (20 mL / L) in a soft etching and a 2% sulfuric acid solution in via holes 14.
a and palladium chloride (50 mg / L as Pd), 35% hydrochloric acid (80 mL / L) and hydrazine hydrochloride (200 mg / L) by subjecting the wiring layer 12a and the wiring layer 12b in the via hole hole 14b to a surface treatment. The wiring layer 12a and the wiring layer 12b in the via hole 14a and the via hole 14b are treated with a processing solution at 25 ° C. for 5 minutes.
A catalyst nucleus was formed on the surface.

Next, an electroless copper plating solution KC-5 at 70 ° C.
Via holes 15a and 15b were formed by electroless copper plating on the via hole holes 14a and 14b using 00 (Nikko Metal Plating).

Next, the surface of the insulating layer 13 and the via hole are treated with a cataposit 44 (manufactured by Shipley) using a colloid catalyst, and further treated by an accelerator 19 (manufactured by Shipley). A conductor layer having a thickness of 35 μm was formed by performing copper plating, patterning was performed, and the wiring layer 16a and the wiring layer 16b were formed. Thus, a four-layer printed wiring board of Example 1 was produced by a build-up method.

<Embodiment 2> In the manufacturing steps shown in FIGS. 3A to 3F, first, the wiring layers 22a are formed on both surfaces of the insulating substrate 21.
Then, an insulating layer 23 and a conductor layer 24 were formed, and the conductor layer 24 was subjected to patterning processing to form an opening 25 for forming a via hole in a predetermined position of the conductor layer 24.

Next, a laser beam is radiated from the opening 25 using the conductor layer 24 as a mask to form a hole in the insulating layer 23, and a desmear treatment and a neutralization treatment are performed.
A via hole 26a having a depth of 35 μm (aspect ratio 1.75) and a via hole 26b having a hole diameter of 50 μm and a depth of 35 μm (aspect ratio 0.7) were formed.

Next, in the same manner as in Example 1, degreasing, soft etching, and surface treatment of the wiring layer 22a and the wiring layer 22b in the via hole hole 26a and the via hole hole 26b are performed to obtain palladium chloride (Pd). 50mg /
L), a treatment solution containing 35% hydrochloric acid (80 mL / L) and hydrazine hydrochloride (200 mg / L) at 25 ° C. for 5 minutes to form via-hole 26 a and via-hole 2.
Catalyst nuclei were formed on the surfaces of the wiring layer 22a and the wiring layer 22b in 6b.

Next, an electroless copper plating solution KC-5 at 70 ° C.
Electroless copper plating was performed on the via hole holes 26a and the via hole holes 26b using 00 (Nikko Metal Plating) to form the via holes 28a and 28b.

Next, the wiring layer 24a and the wiring layer 24b were formed by patterning the conductor layer 24, and the four-layer printed wiring board of Example 2 was produced by the build-up method.

<Embodiment 3> In the manufacturing process shown in FIGS. 4A to 4F, first, the wiring layers 32a are formed on both surfaces of the insulating substrate 31.
And a wiring layer 32b, and further, laminating a copper foil with a resin layer to form an insulating layer 33 and a conductor layer 34, patterning the conductor layer 34, and forming a via hole hole at a predetermined position of the conductor layer 34. An opening 35 for formation was formed.

Next, a laser beam is radiated from the opening 35 using the conductor layer 34 as a mask, a hole is formed in the insulating layer 33, and a desmear treatment and a neutralization treatment are performed.
A via hole 36a having a depth of 35 μm (aspect ratio 1.75) and a via hole 36b having a hole diameter of 50 μm and a depth of 35 μm (aspect ratio 0.7) were formed.

Next, in the same manner as in Example 1, degreasing, soft etching, and surface treatment of the wiring layer 32a and the wiring layer 32b in the via-hole 36a and the via-hole 36b were performed to obtain palladium chloride (Pd). 50mg /
L), a treatment solution consisting of 35% hydrochloric acid (80 mL / L) and hydrazine hydrochloride (200 mg / L) at 25 ° C. for 5 minutes to form a via hole 36 a and a via hole 3.
Catalyst nuclei were formed on the surfaces of the wiring layer 32a and the wiring layer 32b in 6b.

Next, an electroless copper plating solution KC-5 at 70 ° C.
Using 00 (Nikko Metal Plating), the via holes 36a and 36b were subjected to electroless copper plating to form via holes 38a and 38b.

Next, the conductor layer 34 was patterned to form a wiring layer 34a and a wiring layer 34b, thereby producing a four-layer printed wiring board of Example 3 by a build-up method.

<Comparative Example 1> In the manufacturing steps shown in FIGS. 5A to 5D, first, the wiring layers 42a are formed on both surfaces of the insulating substrate 41.
An insulating layer 43 having a thickness of 35 μm is formed on the two-layer laminate on which the wiring layer 42b is formed, and a predetermined position of the insulating layer 43 is drilled by laser processing, desmearing and neutralization are performed. Via hole hole 44a having a diameter of 20 μm and a depth of 35 μm (aspect ratio 1.75) and a hole diameter of 50 μm
A via hole 44b having a depth of 35 μm (aspect ratio 0.7) was formed.

Next, a degreasing treatment was performed using sodium persulfate (10%).
0 g / L) and sulfuric acid (20 mL / L) in a soft etching and a 2% sulfuric acid solution for via holes 44.
a and the surface of the wiring layer 42a and the wiring layer 42b in the via hole hole 44b are subjected to a surface treatment, and the surface of the insulating layer 43 and the inside of the via hole hole 14a and the inside of the via hole hole 14b are treated with a cataposit 44 (manufactured by Shipley). After applying a colloid catalyst and further processing with an accelerator 19 (manufactured by Shipley), a 1 μm thick copper thin film conductor layer is formed in the via hole holes 44 a and the via hole holes 44 b and on the surface of the insulating layer 43 by electroless copper plating. The via hole 45a, the via hole 45b and the conductor layer 46 having a thickness of 35 μm were formed by performing electrolytic copper plating.

Next, the conductor layer 46 was patterned to form a wiring layer 46a and a wiring layer 46b, thereby producing a four-layer printed wiring board of Comparative Example 1 by a build-up method.

<Comparative Example 2> In the manufacturing steps shown in FIGS. 5A to 5D, first, the wiring layers 42a
An insulating layer 43 having a thickness of 35 μm is formed on the two-layer laminate on which the wiring layer 42b is formed, and a predetermined position of the insulating layer 43 is drilled by laser processing, desmearing and neutralization are performed. Via hole hole 44a having a diameter of 20 μm and a depth of 35 μm (aspect ratio 1.75) and a hole diameter of 50 μm
A via hole 44b having a depth of 35 μm (aspect ratio 0.7) was formed.

Next, a degreasing treatment was performed using sodium persulfate (10%).
0 g / L) and sulfuric acid (20 mL / L) in a soft etching and a 2% sulfuric acid solution for via holes 44.
a and the surface of the insulating layer 43 and the inside of the via hole 14a and the inside of the via hole 14b are subjected to a surface treatment of the wiring layer 42a and the wiring layer 42b in the via hole hole 44b, and a colloid catalyst is applied with a cataposit (shiplay) treatment liquid. Then, by electroless copper plating, via holes 45a,
A via hole 45b and a conductor layer 46 having a thickness of 35 μm were formed.

Next, the conductor layer 46 was patterned to form a wiring layer 46a and a wiring layer 46b, thereby producing a four-layer printed wiring board of Comparative Example 2 by a build-up method.

The cross section of the via hole was observed on the four-layer printed wiring boards obtained in the above Examples and Comparative Examples in a cross section, and the state of embedding of the copper conductor was observed. Table 1 shows the results. The number of observations was 100 via holes.

[0051]

[Table 1]

As can be seen from the results shown in Table 1, the via holes of the fine via hole holes (hole diameter 20 μm) formed by the via hole forming method of the present invention are completely filled with copper conductors, and generation of voids is observed at all. Did not. On the other hand, the fine via hole hole (hole diameter 2
(0 μm), a considerable number of voids were observed in the via hole. As described above, it is clear that the metal is completely buried in the fine via hole hole formed by the via hole forming method of the present invention, and the reliability of the filled via can be improved.

[0053]

As described above, according to the present invention, since the fine via hole is completely filled by electroless plating, the reliability of the filled via can be improved without generation of bubbles and the like. A via hole can be stacked on the via hole with high reliability, and an excellent wiring board can be provided which does not impair the flexibility of the wiring pattern. In addition, such a wiring board can be manufactured with high reliability, and an excellent practical effect is exhibited.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing an example of a manufacturing method of the present invention.

FIGS. 2A to 2D are cross-sectional views showing an example of a manufacturing process for manufacturing a build-up type multilayer printed wiring board using the manufacturing method of the present invention.

FIGS. 3A to 3F are sectional views showing another example of a manufacturing process for manufacturing a build-up type multilayer printed wiring board using the manufacturing method of the present invention.

FIGS. 4A to 4F are sectional views showing still another example of a manufacturing process for manufacturing a build-up type multilayer printed wiring board using the manufacturing method of the present invention.

FIGS. 5A to 5D are cross-sectional views showing an example of a manufacturing process for manufacturing a conventional build-up type multilayer printed wiring board.

[Explanation of symbols]

1,, 11, 21, 31, 41 ... Insulating substrate 2a, 2b, 12a, 12b, 22a, 22b, 32
a, 32b, 42a, 42b ... wiring layers 3, 13, 13, 23, 33, 43 ... insulating layers 4a, 4b, 14a, 14b, 26a, 26b, 36
a, 36b, 44a, 44b... Via hole holes 5a, 5b, 15a, 15b, 28a, 28b, 38
a, 38b, 45a, 45b... Via holes 16a, 16b, 24a, 24b, 34a, 34b, 4
6a, 46b Wiring layer 24, 34, 46 Conductor layer 25, 35 Opening 27 Resist layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E317 AA24 BB12 CC25 CC32 CD27 GG17 5E343 AA07 BB24 BB67 CC73 CC74 DD43 GG13 5E346 AA41 CC32 DD23 FF03 FF07 FF13 FF22 FF24 GG15 HH07

Claims (4)

[Claims] 1. A wiring board in which a wiring layer is electrically connected via a via hole via an insulating layer, one end of the via hole is closed by the wiring layer, and the inside of the via hole is filled with a metal conductor. Wherein the side surface of the insulating layer of the wiring layer portion, which closes one end, is replaced by a catalyst and filled by electroless plating. 2. A method in which a conductor at the bottom of a via hole is subjected to a substitution reaction with a catalyst for a material in which the bottom of the insulating layer in which the via hole is formed is closed by a conductor, and the via hole is formed by electroless plating. A method for manufacturing a wiring board, wherein the inside is filled. 3. The method according to claim 2, wherein the substitution reaction is performed using a catalyst solution containing divalent palladium ions. 4. The method according to claim 3, wherein the catalyst solution containing divalent palladium ions contains at least hydrochloric acid, palladium chloride and hydrazine hydrochloride.