JP4383219B2 - Method for manufacturing printed wiring board - Google Patents

Description

  The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board that is advantageous for high density wiring.

  A circuit formation method for a printed wiring board includes: a subtractive method of forming an etching resist pattern on a metal foil such as a copper foil, and etching the metal foil exposed from the etching resist pattern to form a wiring circuit; An additive method is roughly classified into two methods, in which a plating resist having a reverse pattern is formed and plating is deposited in the plating resist opening to form a wiring circuit.

  Since the subtractive method is easier to manufacture than the additive method, the subtractive method can be manufactured at a very low cost. However, through holes, blind via holes, etc. (hereinafter referred to as via holes) are formed. At this time, since it is necessary to perform electroless plating and electrolytic plating treatment on the entire insulating substrate, the thickness of the conductor to be etched (metal foil + plating) becomes very thick, making it difficult to form a good wiring circuit. In particular, this method is not suitable for forming a fine wiring circuit having a pattern width / pattern gap = 75 μm / 75 μm or less.

  In contrast, the additive method is advantageous for the formation of fine wiring circuits. However, in order to form a wiring circuit by depositing plating on the insulating layer, a metal foil is originally laminated on the insulating layer as in the subtractive method. Compared to processing the insulated substrate, there were problems such as poor adhesion of the wiring circuit.

  Furthermore, because of the design of the printed wiring board, the wiring circuit is formed unevenly on the substrate surface. Therefore, when the wiring circuit is formed by selective plating as in the additive method, the current is more than necessary in the rough portion of the wiring circuit. As a result, the thickness variation of the wiring circuit is increased, and as a result, there are problems such as difficulty in impedance matching.

  As a solution to such a problem, a printed wiring board having a configuration as shown in FIGS. 9 to 10 has already been reported (see, for example, Patent Document 1).

  9 to 10 show an example in which a build-up wiring layer is formed on an inner core substrate (not shown). First, as shown in FIG. 9A, the lower wiring circuit 4b formed in the inner layer. The interlayer insulating layer 1 and a metal foil 2 such as a copper foil are sequentially laminated on the formation layer (for example, a copper foil with resin is laminated), and then, as shown in FIG. Upper layer wiring circuit 4a is formed. Next, a non-through hole 6 for forming a via hole is drilled at a predetermined interval from the hole vicinity portion 4c in the upper layer wiring circuit 4a (see FIG. 9C). Next, as shown in FIG. 9D, the electroless plating 11 is formed on the formation layer of the upper wiring layer circuit 4a including the non-through hole 6, and then, as shown in FIG. 9E. Then, a plating resist 12 having the non-through hole 6 and an opening 12a exposing the periphery thereof is formed. Next, the electrolytic plating process is performed to deposit electrolytic plating 7a in the opening (see FIG. 9F), and then the plating resist 12 is peeled off (see FIG. 10G). Finally, the unnecessary electroless plating 11 is removed by soft etching to obtain the printed wiring board 10 shown in FIG. 10H provided with the via holes 9a.

  Thus, since the upper wiring pattern is formed before the electroplating process, a fine wiring circuit can be easily formed even by a subtractive method.

  However, the method of depositing plating only on the via hole forming portion as described above has the following problems.

  First of all, when the plating process is performed by the panel plating method which is a standard plating method, the panel plating method in which the plating is originally deposited on the entire insulating substrate has an area ratio of about 1% of the entire insulating substrate. It is very difficult to deposit plating only on the via-hole forming portion which is only present in terms of plating control.

  Secondly, via holes are unevenly arranged in the board surface due to the design of the printed wiring board. Where a small number or a single hole exists, the current is concentrated more than necessary, and the plating deposition shape appears on the board surface. It was very unstable inside.

  By the way, in order to achieve high density wiring in a multilayer printed wiring board, an upper layer via hole may be disposed on a via hole in a double-sided core or a multilayer core. In this case, it is necessary to smooth the via hole surface of the core. Therefore, after filling the via hole with insulating resin or conductive resin, a method of flattening by forming lid plating on the via hole or filling the via hole with plating is used. In recent years, since the hole diameter has become very small due to the demand for high-density wiring, it is difficult to fill the resin, and as a result, the number of cases in which plating is filled is increasing.

  As described above, a method for manufacturing a printed wiring board having a structure as shown in FIG. 11 has already been reported as filling a via hole with plating (see, for example, Patent Document 2).

  FIG. 11 is a schematic cross-sectional process diagram of the printed wiring board described above. First, an insulating substrate 3 in which metal foils 2a and 2b are laminated on the upper and lower sides of an insulating base 1a is prepared, and the upper metal foil 2a to the lower metal foil 2b are prepared. The non-through-hole 6 reaching to is drilled (see FIG. 11A). Next, electrolytic plating is performed using the lower layer metal foil 2b as a power feeding layer, and the non-through holes 6 are filled with plating 7 (see FIG. 11B). At this time, since no power is supplied to the upper metal foil 2a, the upper metal foil 2a is eluted, the thickness is gradually reduced, and the lower metal foil 2b serving as the power supply layer is exposed. Precipitate and increase in thickness. Next, as shown in FIG. 11C, when the plating 7 in the non-through hole 6 reaches the upper metal foil 2a, the upper metal foil 2a is also supplied with power, and the plating 7 is gradually deposited. And as shown in FIG.11 (d), by stopping electric power supply timely, the thickness of the upper and lower metal foils 2a and 2b is made into desired thickness.

As described above, the non-through hole is filled with plating and the surface of the lower metal foil (that is, the power feeding layer) is also deposited (that is, the plating area ratio is increased), so that it is stable. Thus, plating can be deposited in the non-through holes.
JP 2001-308530 A JP 2000-188471 A

  However, in the above configuration, since the thickness of the metal foil is controlled by stopping the feeding of the electrolytic plating in a timely manner, the thickness adjustment of the metal foil is insufficient. Further, as another manufacturing method of Patent Document 2, a thickness of the lower layer metal foil is obtained by forming a plating resist on the surface of the lower layer metal foil that is a power feeding layer and not depositing plating on the lower layer metal foil surface. However, in the end, the plating area ratio becomes extremely low (the plating formation of only the non-through holes for via holes) and the density of the via holes is increased. However, it is very difficult to uniformly fill the non-through holes with plating.

  The present invention can stably (uniformly) deposit (or fill) plating in forming a via hole for interlayer connection into a through hole or a non-through hole, and a metal foil (or It is an object of the present invention to provide a method for manufacturing a printed wiring board capable of easily forming a fine wiring circuit and impedance matching while keeping the thickness of the wiring circuit) constant.

In order to achieve the above object, the present invention according to claim 1 is a method for manufacturing a printed wiring board having via holes for interlayer connection, and at least before the plating process for forming the via holes, the outer layer of the insulating substrate. In order to prevent the wiring circuit and / or the metal foil from being etched on the exposed surface of the formed wiring circuit and / or the metal foil by an etching process at the time of subsequent circuit formation of the via hole portion, A step of providing a barrier metal layer made of a metal thin film having different etching conditions from electrolytic plating and electroless plating in forming a via hole, and a step of depositing plating on the barrier metal layer by plating for forming a via hole; Etching the plating to expose the barrier metal layer, forming a via hole and its land, and the exposed bar. It is characterized in that a step of removing the A metal layer is etched.

  Thereby, plating can be stably deposited (or filled) in the via hole forming portion, and a fine wiring circuit having a certain thickness can be easily formed on the outer layer.

Further, in the present invention according to claim 2, in the invention according to claim 1, after providing the barrier metal layer, the plating process for forming the via hole is formed on the bottom side of the non-through hole for the via hole. A method of manufacturing a printed wiring board, characterized in that it is performed by an electrolytic plating process using a barrier metal layer as a power feeding layer, and the electrolytic plating is filled in via holes for via holes and deposited on the surface of the power feeding layer. is there.

  Accordingly, the plating can be stably filled from the one-side power feeding layer, and a fine wiring circuit having a certain thickness can be easily formed on the outer layer.

  By manufacturing a printed wiring board having via holes for interlayer connection by the manufacturing method of the present invention, plating can be stably deposited (or filled) in the via holes, and a metal foil (or wiring pattern) ) Can be kept constant, and fine pattern formation and impedance matching can be easily performed.

  A first embodiment of the present invention will be described with reference to FIGS.

  1 to 2 show an example of forming a build-up wiring layer on an inner core substrate (not shown) (filling a via hole with plating), similar to the example shown in FIGS. 9 to 10. As shown in FIG. 1A, an interlayer insulating layer 1 and a metal foil 2 such as a copper foil are sequentially laminated on the formation layer of the lower layer wiring circuit 4b formed in the inner layer (for example, a copper foil with resin is used). Then, as shown in FIG. 1B, an upper wiring circuit 4a is formed by etching. Next, as shown in FIG. 1C, a metal thin film having etching conditions different from those of the electroplating 7 in the later formation of the via hole and the electroless plating (not shown) on the entire outer layer including the upper wiring circuit 4a. A barrier metal layer 5 is formed. The barrier metal layer 5 may be any metal as long as the upper wiring circuit 4a is not etched during the subsequent formation of the via hole circuit. Examples thereof include Ni, Sn, Ag, and the like by electroless plating. It is done. The barrier metal layer 5 is preferably selected in consideration of releasability in terms of the manufacturing process. For example, taking Ni as an example, peeling is easy with Ni or Ni-B plating, but with Ni-P plating, peeling becomes difficult when the phosphorus concentration is high. It is preferable. Next, as shown in FIG. 1D, after the non-through hole 6 reaching the lower wiring circuit 4b is drilled by laser irradiation, desmear processing in the non-through hole 6 is performed, and then the non-through hole Electroless plating (for example, electroless copper plating) (not shown) is formed on the entire outer layer including the holes 6, and electrolytic plating (for example, electrolytic copper plating using a filled via plating solution) is performed using the electroless plating as a power supply layer. And filling the non-through hole 6 with the plating 7 and depositing the plating 7 on the outer layer. Next, as shown in FIG. 2 (f), after the circuit formation of the via hole 9 and its land portion is performed, the barrier metal layer 5 exposed to the outer layer is removed by etching, whereby FIG. The printed wiring board 10 shown in FIG.

  Next, a second embodiment will be described with reference to FIGS.

3 to 4 show an example in which a build-up wiring layer is formed on an inner core substrate (not shown), as described above. First, as shown in FIG. Then, an interlayer insulating layer 1 and a metal foil 2 such as a copper foil are sequentially laminated on the formation layer of the lower wiring circuit 4b (for example, a copper foil with resin is laminated), and then reaches the lower wiring circuit 4b by laser irradiation. The through hole 6 is drilled (see FIG. 3B). Next, as shown in FIG. 3 (c), electrolytic plating or electroless plating (in this embodiment, an example using displacement plating is shown, and the front side surface of the metal foil 2 and the non-through hole 6 are shown. The barrier metal layer is formed on the surface of the lower layer wiring circuit 4b exposed from the surface of the metal foil 2. When the electrolytic plating is used, the barrier metal layer 5 is formed only on the front side surface of the metal foil 2. Next, an electroless plating (not shown) (for example, electroless copper plating) (not shown) is formed on the entire outer layer including the non-through holes 6, and then electroplating (for example, electrolytic copper plating using a plating solution for filled vias) Processing is performed to fill the non-through holes 6 with the plating 7 and deposit the plating 7 on the outer layer (see FIG. 3D). Next, as shown in FIG. 3E, after the via hole 9 and its land portion are formed, the barrier metal layer 5 exposed to the outer layer is formed as shown in FIG. Etching removed (Before removing the barrier metal layer 5, the via hole 9 and its land portion can be etched by about 5 to 10 μm to reduce the plating step between the via hole 9 and its land portion) Then, by forming a circuit on the exposed metal foil 2, the printed wiring board 10 of FIG. 4G in which the upper wiring circuit 4a is formed on the outer layer is obtained.

  By adopting the first and second embodiments, when the via hole is filled with plating, the plating is also deposited on the outer layer, so that the via hole can be filled with stability. Further, since the upper wiring circuit and the metal foil are protected by the barrier metal foil, a certain thickness can be secured, and as a result, a fine wiring circuit can be easily formed.

  In the first and second embodiments, the interlayer insulating layer 1 exposed to the outer layer does not exist at all in the desmear process of the non-through hole 6. Accordingly, in the configuration shown in FIGS. 9 to 10, the desmear treatment of the non-through hole 6 is also performed simultaneously with the desmear treatment of the wiring circuit non-formed portion (the surface of the interlayer insulating layer 1). However, in the first and second embodiments, contamination of the desmear treatment liquid can be suppressed to the minimum (only the non-through hole portion). There is also an advantage that it can be a life period that is the same as normal use.

  In the first and second embodiments, an example in which the via hole 9 is filled is shown. However, by performing an electrolytic plating process with a normal plating solution, the through hole 9b as shown in FIG. The printed wiring board 10 in which the plating 7a is formed only on the land portion, and the printed wiring board 10 in which the plating via 7a is formed only on the blind via hole 9a and the land portion as shown in FIG. .

  Next, a third embodiment will be described with reference to FIGS.

  7 to 8 show an example in which electrolytic plating (for example, electrolytic copper plating) is performed using the metal layer formed on the bottom side of the via hole as a power feeding layer, and the plating is filled in the non-through holes. First, as shown in FIG. 7A, an insulating substrate 3 provided with metal foil 2 such as copper foil is prepared above and below an insulating base 1a, and upper and lower wiring circuits 4a and 4b are formed by etching. (See FIG. 7B). Next, as shown in FIG. 7 (c), the barrier metal layer 5 having etching conditions different from those of the electroplating 8a and 8b and the electroless plating (not shown) in the subsequent formation of the via hole is formed on the entire outer layer, Then, the non-through hole 6 reaching the lower layer wiring circuit 4b is drilled by laser irradiation (see FIG. 7D). Here, the barrier metal layer 5 is also deposited on the end face of the printed wiring board, and power is also supplied to the upper layer in the subsequent electrolytic plating process. Therefore, before the electrolytic plating process (for example, FIG. After the step of), an end face cutting process or the like is performed, and the barrier metal layer 5 deposited on the end face is removed in advance. Next, after desmearing the non-through hole 6, electrolytic plating (for example, electrolytic copper plating) is performed using the barrier metal layer 5 formed on the lower wiring circuit 4 b side as a power supply layer, and the non-through hole 6 The first electrolytic plating 8a is filled in the middle of the process, and the first electrolytic plating 8a is also deposited on the surface of the barrier metal layer 5 as the power feeding layer (see FIG. 7E). Next, an electroless plating (not shown) (for example, electroless copper plating) (not shown) is formed on the entire outer layer including the non-through holes 6, and then an electrolytic plating (for example, electrolytic copper plating using a filled via plating solution) is performed. The remaining non-through holes 6 are filled with the second electrolytic plating 8b, and the second electrolytic plating 8b is deposited on the entire outer layer (see FIG. 8 (f)). Next, as shown in FIG. 8G, the via hole 9 and its land portion are formed, and at the same time, the excess first and second electrolytic platings 8a and 8b are removed, and then exposed to the outer layer. By removing the existing barrier metal layer 5 by etching, the printed wiring board 10 shown in FIG. 8H in which the wiring circuits 4a and 4b are formed above and below the insulating base 1a is obtained.

  As described above, the plating is deposited on the surface of the power feeding layer at the same time that the non-through hole is filled with plating (that is, the plating area ratio is widened and distributed uniformly), so that plating can be stably applied to the via holes. Can be filled. In addition, since the wiring circuits formed in the upper and lower layers are protected by the barrier metal layer, a certain thickness can be secured, and as a result, a fine wiring circuit can be easily formed.

  In the third embodiment, the example in which the barrier metal layer is formed after the wiring circuit is formed in advance has been described. However, after the circuit formation of the via hole portion is completed in accordance with FIGS. A wiring circuit can also be formed.

  Further, in the first and third embodiments in which the wiring circuit is formed in advance, an example in which the barrier metal layer is formed on the entire outer layer including the front side surface of the wiring circuit by the electroless plating process on the entire surface using palladium or the like. As described above, the configuration is not limited to this, and it is also possible to form a barrier metal layer only at least on the front side of the wiring circuit by substitutional electroless plating. However, in the case of this configuration, after the barrier metal layer is formed on the front side surface of the wiring circuit, in order to prevent the wiring circuit non-formed portion from being desmeared when the non-through hole is desmeared, It is necessary to form electroless plating (for example, electroless copper plating) on the entire outer layer including the layer. Therefore, since the electroless plating process is required twice in combination with the electroless plating formed after the drilling of the non-through hole and the desmear treatment, it is manufactured in comparison with the first and third implementation processes. There is a demerit that the process becomes slightly longer.

  In the third embodiment, an example in which plating is stably filled into a non-through hole having a plate thickness of 0.1 mm or more and a hole diameter of φ100 μm or less is shown. Therefore, although the process of performing the electrolytic plating process in two steps was shown, if the plate thickness is 0.06 mm or less, it is filled with a single electrolytic plating process as in the first and second embodiments. be able to.

  Furthermore, in the third embodiment, the description has been given by taking the double-sided printed wiring board having the metal foil on the front and back of the insulating base material as an example, but the same effect can be obtained even in the multilayer printed wiring board. Not too long.

Example 1
A built-up multilayer printed wiring board in which the printed wiring board 10 shown in FIGS. 7 to 8 is used as a core substrate and the build-up wiring layers shown in FIGS. Manufactured by.
First, prepare a glass epoxy copper-clad laminate (manufactured by Hitachi Chemical Co., Ltd .: MCL-E679F) with a 12 mm thick copper foil laminated on both sides of a 0.1 mm glass epoxy resin substrate impregnated with epoxy resin in glass fiber (Corresponding to FIG. 7A), a fine wiring circuit of L / S (wiring width / wiring gap) = 30 μm / 30 μm on both sides by a subtractive method using a 20 μm dry film (Asahi Kasei Co., Ltd .: SPG202). Was formed (corresponding to FIG. 7B).

  Next, a barrier metal layer was formed on the entire surface of the insulating substrate including the front side surface of the wiring circuit (corresponding to FIG. 7C). As the barrier metal layer, an electroless Ni—P plating (thickness 0.5 μm) using sodium hypophosphite as a reducing agent was formed after a palladium catalyst was applied to the entire surface of the insulating substrate.

Next, a carbon dioxide laser is irradiated to a desired position to drill non-through holes with a top diameter of φ95 μm and a bottom diameter of φ60 μm, and then the inner wall of the non-through holes is roughened by desmear treatment using a potassium permanganate solution. And removal of the resin residual film at the bottom (corresponding to FIG. 7D).
Next, the end face was slightly cut, the barrier metal layer deposited on the end face of the insulating substrate was removed, and the upper and lower wiring circuits were insulated.

  Next, a barrier metal layer formed on the surface of the lower wiring circuit was used as a power feeding layer, and an anode was disposed only on the barrier metal layer side, and electrolytic copper plating was performed in a high throw bath. At this time, the electrolytic copper plating was made to bottom up from the bottom of the non-through hole and also deposited on the surface of the barrier metal layer on the lower wiring circuit (corresponding to FIG. 7 (e)). The electrolytic copper plating was deposited to a thickness of 60 μm in both the non-through holes and the surface of the barrier metal layer. The electrolytic copper plating deposited on the barrier metal layer surface is a dummy plating for suppressing the concentration of current density in the non-through holes.

  Next, in order to make the upper and lower wiring circuits conductive, electroless copper plating with a thickness of 0.5 μm is applied to the entire surface of the insulating substrate, followed by electrolytic copper plating in a via filling bath, and plating in the non-through holes. Was completely filled (corresponding to FIG. 8F). The electrolytic copper plating treatment was set to deposit 15 μm on the outer layer.

  Next, an etching resist pattern is formed on the via hole on the laser irradiation side and the land forming portion thereof, and etching is performed with an alkaline etching solution (Meltex Co., Ltd .: A process) mainly composed of copper ammonium complex ions. The excess copper plating was removed until the barrier metal layer made of nickel was exposed. And after performing the said etching process, the said etching resist pattern was peeled and removed (equivalent to FIG.8 (g)).

  Next, a nickel substrate (manufactured by MEC: NH-1862) was used to peel the nickel (barrier metal layer) exposed on the surface to obtain a core substrate (corresponding to FIG. 8 (h)). .

  Next, 50 μm prepreg (manufactured by Hitachi Chemical Co., Ltd .: GEA-679F) and 12 μm copper foil were sequentially laminated on both surfaces of the core substrate (corresponding to FIG. 1A).

  Next, a wiring circuit having a fine wiring circuit of L / S = 30 μm / 30 μm on the outer layer (both sides) was formed by a subtractive method (corresponding to FIG. 1B) as in the manufacture of the core substrate. .

  Next, electroless nickel plating (corresponding to FIG. 1C), laser, and desmear treatment were performed under the same conditions as in the manufacture of the core substrate (corresponding to FIG. 1D). In addition, the non-through-hole diameter was made into top diameter (phi) 80micrometer and bottom diameter (phi) 50micrometer.

  Next, electroless copper plating (0.5 μm) was applied to the entire outer layer including non-through holes, and then electrolytic copper plating was performed in a via filling bath (corresponding to FIG. 1 (e)). The electrolytic copper plating conditions are the same as those for the core substrate.

  Next, an etching resist pattern was formed in the via hole and its land formation portion, and the via hole and its land were formed by alkali etching, and the excess copper plating was removed until the barrier metal layer made of nickel was exposed ( Corresponding to FIG.

  Then, after the etching process, the etching resist pattern is peeled and removed, and then the nickel exposed on the surface is peeled off, whereby build-up wiring layers are laminated one by one on the front and back of the core substrate on both sides. A build-up multilayer printed wiring board was obtained (corresponding to FIG. 2 (g)).

Example 2
The printed wiring board 10 shown in FIG. 5 has a four-layer multi-layer structure, and a core substrate in which a resin (conductive resin or insulating resin) is filled in the through hole 9b and the through hole is plated with a lid, The buildup multilayer printed wiring board of FIG. 12 in which the buildup wiring layers shown in FIGS. 1 and 2 were laminated on the front and back of the core substrate was manufactured by the following manufacturing method.

  First, a gasra epoxy copper-clad laminate (manufactured by Hitachi Chemical Co., Ltd .: MCL-E67) in which a copper foil with a thickness of 18 μm is laminated on both sides of a 0.2 mm glass epoxy resin substrate impregnated with epoxy resin in glass fiber. A wiring circuit having a fine wiring circuit of L / S (wiring width / wiring gap) = 30 μm / 30 μm on both surfaces was prepared by a subtractive method using a 20 μm dry film (manufactured by Asahi Kasei Corporation: SPG202).

  Next, a prepreg having a thickness of 100 μm (manufactured by Hitachi Chemical Co., Ltd .: GEA-67N) and a copper foil having a thickness of 12 μm were sequentially laminated on both surfaces of the double-sided substrate on which the wiring circuit was formed.

  Next, 0.2 mm drilling was performed on the laminate, and smears in the through holes were removed by desmearing using a potassium permanganate solution.

  Next, a wiring circuit having fine wiring circuits of L / S = 30 μm / 30 μm on both sides is formed by the subtractive method in the same manner as described above, and then the laminated substrate including the front side surface of the wiring circuit and the inside of the through hole Ni-P plating with a thickness of 0.5 μm was formed on the entire surface.

  Next, electrolytic copper plating with a thickness of 20 μm is formed on the entire surface of the laminated substrate by a high-throw bath, and then a step of 8 μm of electrolytic plating due to the wiring circuit is removed by buffing to make the surface flat. .

  Next, the resin is filled in the through hole, and after curing, the resin exposed from the through hole is removed by buffing, and then the entire surface of the multilayer substrate is subjected to electroless plating of 0.5 μm, An electrolytic copper plating having a thickness of 10 μm was formed on the entire surface of the multilayer substrate by a high-throw bath.

Next, an etching resist pattern is formed on the through hole and its land formation part, and the through hole lid plating and its land are formed by an alkali etching process, and excess copper plating is performed until the barrier metal layer made of nickel is exposed. Was removed. And after performing the said etching process, the said etching resist pattern was peeled and removed, and the core board | substrate shown in FIG. 12 was obtained by peeling the nickel exposed on the surface then.
Then, in accordance with Example 1, build-up multilayer printed wiring boards shown in FIG. 12 were obtained by forming build-up wiring layers on both surfaces of the core substrate.

BRIEF DESCRIPTION OF THE DRAWINGS The schematic cross-sectional process explanatory drawing which shows process (a)-(e) in 1st embodiment of this invention. Schematic cross-sectional process explanatory drawing which shows process (f)-(g) in 1st embodiment of this invention. Schematic cross-sectional process explanatory drawing which shows process (a)-(e) in 2nd embodiment of this invention. The schematic cross-sectional process explanatory drawing which shows process (f)-(g) in 2nd embodiment of this invention. Schematic cross-sectional explanatory drawing which shows the example of a printed wiring board obtained by the method of this invention which does not fill a through hole with plating. BRIEF DESCRIPTION OF THE DRAWINGS Schematic cross-sectional explanatory drawing which shows the example of the printed wiring board obtained by this invention method which does not fill a blind via hole with plating. The schematic cross-sectional process explanatory drawing which shows process (a)-(e) in 3rd embodiment of this invention. Schematic cross-sectional process explanatory drawing which shows process (f)-(h) in 3rd embodiment of this invention. Schematic cross-sectional process explanatory drawing which shows process (a)-(f) in the manufacturing method of the conventional printed wiring board. Schematic cross-sectional process explanatory drawing which shows process (g)-(h) in the manufacturing method of the conventional printed wiring board. Schematic cross-sectional process explanatory drawing which shows the manufacturing method of the other conventional printed wiring board. BRIEF DESCRIPTION OF THE DRAWINGS Schematic cross-section explanatory drawing which shows the example of the buildup multilayer printed wiring board obtained by this invention method.

Explanation of symbols

1: Interlayer insulating layer 1a: Insulating substrate 2: Metal foil 2a: Upper layer metal foil 2b: Lower layer metal foil 3: Insulating substrate 4a: Upper layer wiring circuit 4b: Lower layer wiring circuit 4c: Near hole portion 5: Barrier metal layer 6: Non-through holes 7, 7a: Electrolytic plating 8a: First electrolytic plating 8b: Second electrolytic plating 9, 9a: Via hole 9b: Through hole 10: Printed wiring board 11: Electroless plating 12: Plating resist 12a: Opening

Claims (2)

A method of manufacturing a printed wiring board provided with via holes for interlayer connection, at least on the exposed surface of a wiring circuit and / or metal foil formed on an outer layer of an insulating substrate before plating for forming via holes, In order to prevent the wiring circuit and / or the metal foil from being etched by the etching process in the subsequent via hole circuit formation, the electrolytic plating and the electroless plating in the subsequent via hole formation are the etching conditions. A step of providing a barrier metal layer made of a different metal thin film, a step of depositing a plating on the barrier metal layer by a plating process for forming a via hole, and etching the plating to expose the barrier metal layer, Forming via holes and lands, and removing the exposed barrier metal layer by etching; Method for manufacturing a printed wiring board characterized in that it has. After providing the barrier metal layer, a plating process for forming the via hole is performed by an electrolytic plating process using the barrier metal layer formed on the bottom side of the non-through hole for the via hole as a power feeding layer, and the electrolytic plating is performed on the via hole. The method for manufacturing a printed wiring board according to claim 1, wherein the non-through hole is filled and deposited on the surface of the power supply layer.

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