JP2004040064A5 - - Google Patents

Claims (13)

A first semiconductor region; a first gate insulating film including a bottom insulating film, an intermediate film, and a top insulating film sequentially stacked on the first semiconductor region; and the first gate insulating film provided on the first gate insulating film. Comprising at least a first conductive gate structure,
Furthermore, a discrete carrier trapping site is provided in at least one of the intermediate film, the intermediate film and the bottom insulating film interface, and the intermediate film and the top insulating film interface,
An electronic structure in which the bottom insulating film is configured such that the side in contact with the intermediate film is larger in the electron affinity than the side in contact with the first semiconductor region, thereby suppressing an increase in injection of electrons from the first semiconductor region A non-volatile memory characterized by facilitating electron emission from the discrete carrier trapping sites through the bottom insulating film. A first semiconductor region; a first gate insulating film including a bottom insulating film, an intermediate film, and a top insulating film sequentially stacked on the first semiconductor region; and the first gate insulating film provided on the first gate insulating film. Comprising at least a first conductive gate structure,
Furthermore, a discrete carrier trapping site is provided in at least one of the intermediate film, the intermediate film and the bottom insulating film interface, and the intermediate film and the top insulating film interface,
The bottom insulating film has a higher electron energy on the side in contact with the intermediate film with respect to the top surface of the valence band than on the side in contact with the first semiconductor region, thereby injecting holes from the first semiconductor region. A non-volatile memory characterized by facilitating the emission of holes from the discrete carrier trapping sites through the bottom insulating film with an electronic structure that suppresses an increase in the number of holes. The discretized carrier trapping site is an electronic trap level created when forming the first gate insulating film present in at least one of the intermediate film and the interface. The non-volatile memory according to claim 1 or 2. The non-volatile memory according to claim 1, wherein the trapping sites are fine particles insulated from each other having a higher conductivity than the intermediate film. The bottom insulating film is composed of a silicon oxide film, the intermediate film is composed of a silicon nitride film, and the top insulating film is composed of a silicon oxide film, and the bottom silicon oxide film is nitrided. 5. The non-volatile memory according to claim 1, wherein the non-volatile memory is larger than the semiconductor region side. 6. The nonvolatile memory according to claim 5, wherein the intermediate film is a silicon nitride film containing a bond of silicon and oxygen. The bottom insulating film is a silicon oxide film, the intermediate film is a film obtained by nitriding the silicon oxide film, and the top insulating film is a film obtained by further oxidizing a film obtained by nitriding the silicon oxide film. The non-volatile memory according to claim 1 or 2. 6. A nonvolatile memory comprising a transistor comprising the memory of claim 5, a fourth gate insulating film formed simultaneously with the top oxide film of the memory, and a fourth conductive gate formed simultaneously with the first conductive gate of the memory. Memory array. The bottom insulating film is a silicon oxide film, and the bottom insulating film is surface-nitrided at a temperature lower than 850 ° C. in at least one of a plasma atmosphere containing nitrogen atoms and an atmosphere containing nitrogen radical. 8. A method of manufacturing a memory according to claim 5, 6, or 7. The top insulating film is formed by surface oxidizing the intermediate film in at least one of a plasma atmosphere containing oxygen atoms and an atmosphere containing oxygen radical at a temperature lower than 850 ° C. 8. A method of manufacturing a memory according to claim 5, 6 to 7. The top insulating film is formed by oxidizing the surface of the intermediate film in at least one of a plasma atmosphere containing oxygen atoms and an atmosphere containing oxygen radical at a temperature lower than 850 ° C. 3. The method of manufacturing a memory according to claim 1, wherein the memory is formed by chemical vapor deposition at a low temperature. The top insulating film is chemically deposited on the intermediate film at a temperature lower than 850 ° C., and is then at least one of a plasma atmosphere containing oxygen atoms and an atmosphere containing oxygen radical and lower than 850 ° C. 3. The method of manufacturing a memory according to claim 1, wherein the memory is formed by annealing at a temperature. The fourth gate insulating film is formed at the same time as the top insulating film in at least one of a plasma atmosphere containing oxygen atoms and an atmosphere containing oxygen radical at a temperature lower than 850 ° C. A method of manufacturing a memory array according to claim 8.