JP2004022907A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2004022907A
JP2004022907A JP2002177674A JP2002177674A JP2004022907A JP 2004022907 A JP2004022907 A JP 2004022907A JP 2002177674 A JP2002177674 A JP 2002177674A JP 2002177674 A JP2002177674 A JP 2002177674A JP 2004022907 A JP2004022907 A JP 2004022907A
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semiconductor substrates
wiring
semiconductor device
main substrate
insulator
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Takashi Sakuta
作田　孝
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Seiko Epson Corp
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Seiko Epson Corp
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To perform wire connection at parts between a plurality of chips by using wires whose width is almost 10μm, without performing metal sputtering and etching, in a semiconductor device which is constituted by mounting a plurality of chips on one main substrate. <P>SOLUTION: This semiconductor device is provided with: a chip adapter 10 in which a plurality of trenches are formed and has insulation; a plurality of semiconductor substrates 11-13 on which I/O pads P and prescribed circuits are formed and which are inserted in the plurality of trenches of the chip adapter 10, respectively; and the wiring 20 which is formed on the plurality of semiconductor substrates and the chip adapter and electrically connects the I/O pads with each other in parts between the plurality of semiconductor substrates. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、一般的に半導体装置に関し、特に、パッケージ内に複数の半導体基板（以下、「チップ」ともいう）が実装されたシステムインパッケージ（Ｓｙｓｔｅｍｉｎ　Ｐａｃｋａｇｅ）と呼ばれる半導体装置に関する。さらに、本発明は、そのような半導体装置の製造方法に関する。
【０００２】
【従来の技術】
パッケージ内に複数のチップが実装されたシステムインパッケージと呼ばれる半導体装置においては、例えば、１つのメイン基板上に複数のチップを実装し、これらのチップに設けられたパッド間を配線することにより、システムが構成される。その際に用いられる配線技術としては、ワイアボンディングが主流であるが、半導体装置を小型化するために、メタルスパッタ及びエッチング処理によって配線をパターン形成することにより１０μｍ程度の線幅の配線で結線する方法（マイクロコネクト）も考えられる。
【０００３】
【発明が解決しようとする課題】
しかしながら、メタルスパッタ及びエッチング処理を行う場合には、高価な装置やクリーンルームが必要になると共に、製造工程も複雑になってしまう。また、試作段階において少数のシステムインパッケージを製造する際にも、量産する場合と同様の高価な装置やクリーンルームが必要になってしまう。
【０００４】
そこで、上記の点に鑑み、本発明は、１つのメイン基板上に複数のチップを実装することによって構成される半導体装置において、メタルスパッタやエッチング処理を行わずに複数のチップ間を１０μｍ程度の線幅の配線で結線することにより、半導体装置を小型化すると共に、製造工程を簡素化して製造コストを削減することを目的とする。
【０００５】
【課題を解決するための手段】
上記の課題を解決するために、本発明の第１の観点に係る半導体装置は、複数の溝が形成された絶縁性を有するチップアダプタと、入出力パッド及び所定の回路が形成され、チップアダプタの複数の溝にそれぞれ挿入された複数の半導体基板と、複数の半導体基板及びチップアダプタ上に形成され、複数の半導体基板間において入出力パッド同士を電気的に接続する配線とを具備する。
【０００６】
ここで、配線が、インクジェット方式のプリンタを用いて導電性材料を含むインクを複数の半導体基板及びチップアダプタ上に塗布することによって形成されたものであっても良い。
【０００７】
また、本発明の第２の観点に係る半導体装置は、メイン基板と、入出力パッド及び所定の回路が形成され、メイン基板上に固定された複数の半導体基板と、メイン基板の所定の領域に形成された絶縁体と、複数の半導体基板及び絶縁体又はメイン基板上に形成され、複数の半導体基板間において入出力パッド同士を電気的に接続する配線とを具備する。
【０００８】
ここで、配線が、インクジェット方式のプリンタを用いて導電性材料を含むインクを複数の半導体基板及び絶縁体又はメイン基板上に塗布することによって形成されたものであっても良い。
【０００９】
本発明の第１の観点に係る半導体装置の製造方法は、入出力パッド及び所定の回路が形成された複数の半導体基板を、絶縁性を有するチップアダプタに形成された複数の溝にそれぞれ挿入するステップ（ａ）と、複数の半導体基板及びチップアダプタ上に配線を形成し、複数の半導体基板間において入出力パッド同士を電気的に接続するステップ（ｂ）とを具備する。
【００１０】
ここで、ステップ（ｂ）が、インクジェット方式のプリンタを用いて導電性材料を含むインクを複数の半導体基板及びチップアダプタ上に塗布することによって配線を形成することを含んでも良い。
【００１１】
また、本発明の第２の観点に係る半導体装置の製造方法は、入出力パッド及び所定の回路が形成された複数の半導体基板をメイン基板上に固定するステップ（ａ）と、メイン基板の所定の領域に絶縁体を形成するステップ（ｂ）と、複数の半導体基板及び絶縁体又はメイン基板上に配線を形成し、複数の半導体基板間において入出力パッド同士を電気的に接続するステップ（ｃ）とを具備する。
【００１２】
ここで、ステップ（ｃ）が、インクジェット方式のプリンタを用いて導電性材料を含むインクを複数の半導体基板及び絶縁体又はメイン基板上に塗布することによって配線を形成することを含んでも良い。
【００１３】
本発明によれば、複数の溝が形成された絶縁性を有するチップアダプタを用いるか、あるいは、メイン基板上に絶縁体を形成することにより、チップアダプタ又は絶縁体の高さと複数の半導体基板の高さとを揃え、インクジェット方式のプリンタ等を用いて、複数のチップ間に１０μｍ程度の線幅の配線を容易に形成することができる。これにより、半導体装置を小型化すると共に、製造工程を短縮して製造コストを削減することが可能となる。
【００１４】
【発明の実施の形態】
以下に、本発明の実施の形態について、図面を参照しながら詳しく説明する。なお、同一の構成要素には同一の参照番号を付して、説明を省略する。
図１は、本発明の第１の実施形態に係る半導体装置の平面図であり、図２は、図１に示す２−２における断面図である。
【００１５】
図１及び図２に示すように、この半導体装置は、複数の溝が形成された絶縁性を有するチップアダプタ１０と、入出力パッドＰ及び所定の回路が形成され、チップアダプタ１０の複数の溝にそれぞれ挿入された複数のチップ（ＬＳＩ）１１〜１９と、これらのＬＳＩ及びチップアダプタ１０上に形成され、複数のＬＳＩ間において入出力パッド同士を電気的に接続する配線２０とを含んでいる。
【００１６】
本発明の第１の実施形態に係る半導体装置の製造方法について説明する。
まず、絶縁基板に、ＬＳＩ１１〜１９の厚さとほぼ等しい深さを有する複数の溝をそれぞれ形成することにより、チップアダプタ１０を作成する。次に、これらのＬＳＩを、チップアダプタ１０に形成された複数の溝にそれぞれ挿入して固定する。各々のＬＳＩには、入出力パッドＰ及び所定の回路が形成されており、図２に示すように、入出力パッドＰが上側を向くように、これらのＬＳＩが配置される。このようにして、各々のＬＳＩの高さとチップアダプタ１０の高さとの間に、なるべく段差を与えないようにする。
【００１７】
次に、インクジェット方式のプリンタを用いて、配線２０を印刷によって形成する。即ち、導電性材料を含むインクをＬＳＩ１１〜１９及びチップアダプタ１０上に塗布することにより、１０μｍ程度の線幅を有する配線２０を形成する。導電性材料としては、例えば、導電性ポリマやＡｇ−Ｐｄ（銀−パラジウム）合金を用いることができる。なお、Ａｇ−Ｐｄ合金を用いる場合には、印刷工程の後に、焼成工程を設けることが望ましい。配線２０の形成により、複数のＬＳＩ間において、入出力パッド同士が電気的に接続される。
【００１８】
本実施形態においては、配置・配線プログラムを用いて設計された半導体装置のパターンデータを、印刷による配線の形成にも利用している。これにより、コンピュータによって自動的にプリンタを操作することが可能となり、配線を形成するためのコストを省き、工程を大幅に短縮することができる。
【００１９】
次に、本発明の第２の実施形態に係る半導体装置について説明する。図３は、本発明の第２の実施形態に係る半導体装置の一部を示す断面図である。
図３に示すように、この半導体装置は、メイン基板３０と、入出力パッドＰ及び所定の回路が形成され、メイン基板３０上に固定された複数のチップ（ＬＳＩ）１２及び１３と、メイン基板３０の所定の領域に形成された絶縁体４０と、複数のＬＳＩ及び絶縁体４０上に形成され、複数のＬＳＩ間において入出力パッド同士を電気的に接続する配線５０とを含んでいる。なお、メイン基板３０は、絶縁性を有していても導電性を有していてもかまわない。
【００２０】
本発明の第２の実施形態に係る半導体装置の製造方法について説明する。
まず、メイン基板３０上において、ＬＳＩ１１〜１９の厚さとほぼ等しい厚さを有する絶縁体４０を所定の領域に形成する。例えば、ＬＳＩ１２及び１３の厚さが４００μｍである場合には、絶縁体４０の厚さも、ほぼ４００μｍとする。
次に、ＬＳＩ１２及び１３を、メイン基板３０上において絶縁体４０が形成されてない領域に固定する。なお、絶縁体を形成する工程とＬＳＩを固定する工程との順序は、逆にしても良い。各々のＬＳＩには、入出力パッドＰ及び所定の回路が形成されており、図３に示すように、入出力パッドＰが上側を向くように、これらのＬＳＩが配置される。このようにして、各々のＬＳＩの高さと絶縁体４０の高さとの間に、なるべく段差を与えないようにする。
【００２１】
次に、インクジェット方式のプリンタを用いて、配線５０を印刷によって形成する。即ち、導電性材料を含むインクをＬＳＩ１２及び１３と絶縁体４０上に塗布することにより、１０μｍ程度の線幅を有する配線５０を形成する。配線５０の形成により、複数のＬＳＩ間において、入出力パッド同士が電気的に接続される。
【００２２】
次に、本発明の第３の実施形態に係る半導体装置について説明する。図４は、本発明の第３の実施形態に係る半導体装置の一部を示す断面図である。本発明の第３の実施形態においては、絶縁体に滑らかなスロープを設けている点が、第２の実施形態と異なっている。
【００２３】
図４に示すように、本実施形態においては、メイン基板６０上において、ＬＳＩ１２及び１３の近傍における所定の領域のみに絶縁体７０が形成されている。
従って、配線８０は、これらのＬＳＩ及び絶縁体７０上のみならず、メイン基板６０上にも形成されることになる。そのため、メイン基板６０は、絶縁性を有する必要がある。
【００２４】
本発明の第３の実施形態に係る半導体装置の製造方法について説明する。
まず、ＬＳＩ１２及び１３を、メイン基板６０上の所定の領域に固定する。各々のＬＳＩには、入出力パッドＰ及び所定の回路が形成されており、図４に示すように、入出力パッドＰが上側を向くように、これらのＬＳＩが配置される。次に、メイン基板６０上において、これらのＬＳＩの近傍における所定の領域のみに絶縁体７０を形成する。
【００２５】
次に、インクジェット方式のプリンタを用いて、配線８０を印刷によって形成する。即ち、導電性材料を含むインクを、ＬＳＩ１２及び１３と、絶縁体７０と、メイン基板６０の上に塗布することにより、１０μｍ程度の線幅を有する配線８０を形成する。配線８０の形成により、複数のＬＳＩ間において、入出力パッド同士が電気的に接続される。
【００２６】
【発明の効果】
以上述べたように、本発明によれば、１つのメイン基板上に複数のチップを実装することによって構成される半導体装置において、メタルスパッタやエッチング処理を行わずに複数のチップ間を１０μｍ程度の線幅の配線で結線することができる。これにより、半導体装置を小型化すると共に、製造工程を短縮して製造コストを削減することが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体装置の平面図である。
【図２】図１に示す２−２における断面図である。
【図３】本発明の第２の実施形態に係る半導体装置の一部を示す断面図である。
【図４】本発明の第３の実施形態に係る半導体装置の一部を示す断面図である。
【符号の説明】
１０　チップアダプタ
１１〜１９　ＬＳＩ
２０、５０、８０　配線
３０、６０　メイン基板
４０、７０　絶縁体[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device called a system-in-package (System Package) in which a plurality of semiconductor substrates (hereinafter, also referred to as “chips”) are mounted in a package. Further, the present invention relates to a method for manufacturing such a semiconductor device.
[0002]
[Prior art]
In a semiconductor device called a system-in-package in which a plurality of chips are mounted in a package, for example, by mounting a plurality of chips on one main substrate and wiring between pads provided on these chips, The system is configured. As the wiring technique used at that time, wire bonding is the mainstream, but in order to reduce the size of the semiconductor device, the wiring is patterned by metal sputtering and etching to connect with a wiring having a line width of about 10 μm. A method (microconnect) is also conceivable.
[0003]
[Problems to be solved by the invention]
However, when performing metal sputtering and etching, expensive equipment and a clean room are required, and the manufacturing process becomes complicated. Also, when a small number of system-in-packages are manufactured at the prototype stage, expensive devices and clean rooms are required as in the case of mass production.
[0004]
In view of the above, the present invention provides a semiconductor device configured by mounting a plurality of chips on a single main substrate, in which the distance between the plurality of chips is about 10 μm without performing metal sputtering or etching. It is an object of the present invention to reduce the size of the semiconductor device and simplify the manufacturing process to reduce the manufacturing cost by connecting with a line width wiring.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device according to a first aspect of the present invention includes a chip adapter having an insulating chip adapter having a plurality of grooves, an input / output pad, and a predetermined circuit. And a wiring formed on the plurality of semiconductor substrates and the chip adapter and electrically connecting the input / output pads between the plurality of semiconductor substrates.
[0006]
Here, the wiring may be formed by applying an ink containing a conductive material to the plurality of semiconductor substrates and the chip adapter using an inkjet printer.
[0007]
In addition, a semiconductor device according to a second aspect of the present invention includes a main substrate, a plurality of semiconductor substrates on which input / output pads and a predetermined circuit are formed and fixed on the main substrate, and a predetermined region of the main substrate. The semiconductor device includes the formed insulator, and a plurality of semiconductor substrates and a wiring formed on the insulator or the main substrate and electrically connecting input / output pads between the plurality of semiconductor substrates.
[0008]
Here, the wiring may be formed by applying ink containing a conductive material to a plurality of semiconductor substrates and insulators or a main substrate using an inkjet printer.
[0009]
In a method of manufacturing a semiconductor device according to a first aspect of the present invention, a plurality of semiconductor substrates on which input / output pads and a predetermined circuit are formed are respectively inserted into a plurality of grooves formed in an insulating chip adapter. Step (a) and Step (b) of forming wiring on the plurality of semiconductor substrates and the chip adapter and electrically connecting the input / output pads between the plurality of semiconductor substrates.
[0010]
Here, the step (b) may include forming a wiring by applying an ink containing a conductive material to the plurality of semiconductor substrates and the chip adapter using an inkjet printer.
[0011]
Further, in the method of manufacturing a semiconductor device according to the second aspect of the present invention, a step (a) of fixing a plurality of semiconductor substrates on which input / output pads and predetermined circuits are formed on a main substrate; (B) forming an insulator in the region of (b) and forming wiring on the plurality of semiconductor substrates and the insulator or the main substrate, and electrically connecting input / output pads between the plurality of semiconductor substrates (c). ).
[0012]
Here, the step (c) may include forming a wiring by applying an ink containing a conductive material to a plurality of semiconductor substrates and insulators or a main substrate using an ink jet printer.
[0013]
According to the present invention, the height of the chip adapter or the insulator and the height of the plurality of semiconductor substrates are reduced by using an insulating chip adapter having a plurality of grooves or by forming an insulator on the main board. Wirings having a line width of about 10 μm can be easily formed between a plurality of chips by using an inkjet printer or the like with the same height. This makes it possible to reduce the size of the semiconductor device, shorten the manufacturing process, and reduce the manufacturing cost.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along a line 2-2 shown in FIG.
[0015]
As shown in FIGS. 1 and 2, the semiconductor device includes an insulating chip adapter 10 having a plurality of grooves, an input / output pad P, and a predetermined circuit. And a wiring 20 formed on the LSI and the chip adapter 10 and electrically connecting input / output pads among the plurality of LSIs. .
[0016]
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described.
First, the chip adapter 10 is formed by forming a plurality of grooves each having a depth substantially equal to the thickness of the LSIs 11 to 19 on the insulating substrate. Next, these LSIs are inserted and fixed in a plurality of grooves formed in the chip adapter 10, respectively. Each LSI is formed with an input / output pad P and a predetermined circuit, and these LSIs are arranged such that the input / output pad P faces upward as shown in FIG. In this way, a step is prevented as much as possible between the height of each LSI and the height of the chip adapter 10.
[0017]
Next, the wiring 20 is formed by printing using an inkjet printer. That is, the wiring 20 having a line width of about 10 μm is formed by applying an ink containing a conductive material onto the LSIs 11 to 19 and the chip adapter 10. As the conductive material, for example, a conductive polymer or an Ag-Pd (silver-palladium) alloy can be used. When an Ag-Pd alloy is used, it is desirable to provide a firing step after the printing step. By forming the wiring 20, the input / output pads are electrically connected between the plurality of LSIs.
[0018]
In the present embodiment, pattern data of a semiconductor device designed using an arrangement / wiring program is also used for forming wiring by printing. As a result, the printer can be automatically operated by the computer, the cost for forming the wiring can be omitted, and the process can be greatly reduced.
[0019]
Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 3 is a sectional view showing a part of the semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 3, the semiconductor device includes a main substrate 30, a plurality of chips (LSI) 12 and 13 on which input / output pads P and a predetermined circuit are formed and fixed on the main substrate 30, 30 includes an insulator 40 formed in a predetermined region, and a plurality of LSIs and a wiring 50 formed on the insulator 40 and electrically connecting input / output pads between the plurality of LSIs. The main substrate 30 may have either an insulating property or a conductive property.
[0020]
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described.
First, on the main substrate 30, an insulator 40 having a thickness substantially equal to the thickness of the LSIs 11 to 19 is formed in a predetermined region. For example, when the thickness of the LSIs 12 and 13 is 400 μm, the thickness of the insulator 40 is also approximately 400 μm.
Next, the LSIs 12 and 13 are fixed to a region on the main substrate 30 where the insulator 40 is not formed. Note that the order of the step of forming the insulator and the step of fixing the LSI may be reversed. Each of the LSIs is formed with an input / output pad P and a predetermined circuit, and these LSIs are arranged such that the input / output pad P faces upward as shown in FIG. In this way, a step is prevented as much as possible between the height of each LSI and the height of the insulator 40.
[0021]
Next, the wiring 50 is formed by printing using an inkjet printer. That is, the wiring 50 having a line width of about 10 μm is formed by applying ink containing a conductive material on the LSIs 12 and 13 and the insulator 40. By forming the wiring 50, the input / output pads are electrically connected between the plurality of LSIs.
[0022]
Next, a semiconductor device according to a third embodiment of the present invention will be described. FIG. 4 is a sectional view showing a part of the semiconductor device according to the third embodiment of the present invention. The third embodiment of the present invention is different from the second embodiment in that the insulator has a smooth slope.
[0023]
As shown in FIG. 4, in the present embodiment, the insulator 70 is formed only on a predetermined region near the LSIs 12 and 13 on the main substrate 60.
Therefore, the wiring 80 is formed not only on the LSI and the insulator 70 but also on the main substrate 60. Therefore, the main board 60 needs to have an insulating property.
[0024]
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described.
First, the LSIs 12 and 13 are fixed in a predetermined area on the main board 60. Each LSI has an input / output pad P and a predetermined circuit formed thereon, and these LSIs are arranged such that the input / output pad P faces upward as shown in FIG. Next, on the main substrate 60, the insulator 70 is formed only in a predetermined region near these LSIs.
[0025]
Next, the wiring 80 is formed by printing using an inkjet printer. That is, a wiring 80 having a line width of about 10 μm is formed by applying an ink containing a conductive material on the LSIs 12 and 13, the insulator 70, and the main substrate 60. By forming the wiring 80, the input / output pads are electrically connected between the plurality of LSIs.
[0026]
【The invention's effect】
As described above, according to the present invention, in a semiconductor device configured by mounting a plurality of chips on one main substrate, the distance between the plurality of chips is about 10 μm without performing metal sputtering or etching. Connection can be made with a wiring having a line width. This makes it possible to reduce the size of the semiconductor device, shorten the manufacturing process, and reduce the manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line 2-2 shown in FIG.
FIG. 3 is a sectional view showing a part of a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a sectional view showing a part of a semiconductor device according to a third embodiment of the present invention.
[Explanation of symbols]
10 Chip Adapter 11-19 LSI
20, 50, 80 Wiring 30, 60 Main substrate 40, 70 Insulator

Claims (8)

複数の溝が形成された絶縁性を有するチップアダプタと、
入出力パッド及び所定の回路が形成され、前記チップアダプタの複数の溝にそれぞれ挿入された複数の半導体基板と、
前記複数の半導体基板及び前記チップアダプタ上に形成され、前記複数の半導体基板間において入出力パッド同士を電気的に接続する配線と、
を具備する半導体装置。A chip adapter having an insulating property in which a plurality of grooves are formed,
I / O pads and a predetermined circuit are formed, a plurality of semiconductor substrates respectively inserted into a plurality of grooves of the chip adapter,
A wiring formed on the plurality of semiconductor substrates and the chip adapter and electrically connecting input / output pads between the plurality of semiconductor substrates;
A semiconductor device comprising: 前記配線が、インクジェット方式のプリンタを用いて導電性材料を含むインクを前記複数の半導体基板及び前記チップアダプタ上に塗布することによって形成されたことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the wiring is formed by applying an ink containing a conductive material onto the plurality of semiconductor substrates and the chip adapter using an ink jet printer. メイン基板と、
入出力パッド及び所定の回路が形成され、前記メイン基板上に固定された複数の半導体基板と、
前記メイン基板の所定の領域に形成された絶縁体と、
前記複数の半導体基板及び前記絶縁体又は前記メイン基板上に形成され、前記複数の半導体基板間において入出力パッド同士を電気的に接続する配線と、
を具備する半導体装置。A main board,
I / O pads and a predetermined circuit are formed, a plurality of semiconductor substrates fixed on the main substrate,
An insulator formed in a predetermined area of the main board,
A wiring formed on the plurality of semiconductor substrates and the insulator or the main substrate, and electrically connecting input / output pads between the plurality of semiconductor substrates;
A semiconductor device comprising: 前記配線が、インクジェット方式のプリンタを用いて導電性材料を含むインクを前記複数の半導体基板及び前記絶縁体又は前記メイン基板上に塗布することによって形成されたことを特徴とする請求項３記載の半導体装置。4. The wiring according to claim 3, wherein the wiring is formed by applying an ink containing a conductive material to the plurality of semiconductor substrates and the insulator or the main substrate using an inkjet printer. Semiconductor device. 入出力パッド及び所定の回路が形成された複数の半導体基板を、絶縁性を有するチップアダプタに形成された複数の溝にそれぞれ挿入するステップ（ａ）と、
前記複数の半導体基板及び前記チップアダプタ上に配線を形成し、前記複数の半導体基板間において入出力パッド同士を電気的に接続するステップ（ｂ）と、を具備する半導体装置の製造方法。(A) inserting a plurality of semiconductor substrates on which input / output pads and a predetermined circuit are formed into a plurality of grooves formed in a chip adapter having an insulating property;
Forming a wiring on the plurality of semiconductor substrates and the chip adapter, and electrically connecting input / output pads between the plurality of semiconductor substrates (b). ステップ（ｂ）が、インクジェット方式のプリンタを用いて導電性材料を含むインクを前記複数の半導体基板及び前記チップアダプタ上に塗布することによって前記配線を形成することを含む、請求項５記載の半導体装置の製造方法。6. The semiconductor according to claim 5, wherein step (b) includes forming the wiring by applying an ink containing a conductive material to the plurality of semiconductor substrates and the chip adapter using an inkjet printer. Device manufacturing method. 入出力パッド及び所定の回路が形成された複数の半導体基板をメイン基板上に固定するステップ（ａ）と、
前記メイン基板の所定の領域に絶縁体を形成するステップ（ｂ）と、
前記複数の半導体基板及び前記絶縁体又は前記メイン基板上に配線を形成し、前記複数の半導体基板間において入出力パッド同士を電気的に接続するステップ（ｃ）と、
を具備する半導体装置の製造方法。Fixing a plurality of semiconductor substrates on which input / output pads and a predetermined circuit are formed on a main substrate;
Forming an insulator in a predetermined region of the main substrate (b);
(C) forming wiring on the plurality of semiconductor substrates and the insulator or the main substrate, and electrically connecting input / output pads among the plurality of semiconductor substrates;
A method for manufacturing a semiconductor device comprising: ステップ（ｃ）が、インクジェット方式のプリンタを用いて導電性材料を含むインクを前記複数の半導体基板及び前記絶縁体又は前記メイン基板上に塗布することによって前記配線を形成することを含む、請求項７記載の半導体装置の製造方法。The step (c) includes forming the wiring by applying an ink containing a conductive material to the plurality of semiconductor substrates and the insulator or the main substrate using an inkjet printer. 8. The method for manufacturing a semiconductor device according to claim 7.
JP2002177674A 2002-06-18 2002-06-18 Semiconductor device and its manufacturing method Withdrawn JP2004022907A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100783276B1 (en) * 2006-08-29 2007-12-06 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof
KR100810889B1 (en) * 2006-12-27 2008-03-10 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof
KR100861223B1 (en) 2006-12-27 2008-09-30 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100783276B1 (en) * 2006-08-29 2007-12-06 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof
KR100810889B1 (en) * 2006-12-27 2008-03-10 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof
KR100861223B1 (en) 2006-12-27 2008-09-30 동부일렉트로닉스 주식회사 Semiconductor device and fabricating method thereof

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