JP2004006976A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting excellent high speed operational characteristics by depositing a metal film for forming silicide and then doping the source/drain. <P>SOLUTION: The semiconductor device comprises a semiconductor film formed on an insulated surface and having a pair of first impurity regions, a pair of second impurity regions formed between the pair of first impurity regions, and a channel forming region formed between the pair of second impurity regions; a gate insulating film formed on the semiconductor film; and a gate electrode formed on the gate insulating film. The first impurity region has a concentration higher than that of the second impurity region, the channel forming region and a part of the pair of second impurity regions are formed beneath the gate electrode through the gate insulating film. Silicide is formed on the surface of the pair of first impurity regions and connected with the metal wiring. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an insulated gate transistor (TFT) formed on an insulating surface such as an insulating material such as glass or a material obtained by forming an insulating film such as silicon oxide on a silicon wafer, and a method for manufacturing the same. The present invention is particularly effective for TFTs formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or less. The semiconductor device according to the present invention is used for a drive circuit such as an active matrix such as a liquid crystal display, an image sensor, or a three-dimensional integrated circuit.

Conventionally, it is widely known to form a TFT (thin film transistor) for the purpose of driving an active matrix type liquid crystal display device, an image sensor, or the like. In particular, recently, due to the need for high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed instead of an amorphous silicon TFT using amorphous silicon for an active layer. However, when more advanced characteristics are required, a structure (salicide structure, for example, a salicide structure such as a salicide structure, in which the source / drain used in the semiconductor integrated circuit technology is made of silicide to lower the sheet resistance of the silicide). H. Kaneko et al., IEEE Trans. Electron Devices, ED-33, 1702 (1986)).

However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, since an element is formed on an insulating surface and reactive ion anisotropic etching cannot be performed sufficiently, there is a great limitation that a fine pattern cannot be formed.
FIG. 6 shows a cross-sectional view of a typical process for producing salicide used so far. First, a base film 602 is formed on a substrate (which may be glass or a silicon wafer) 601, and an active layer is formed with crystalline silicon 603. Then, an insulating film 604 is formed on the active layer using a material such as silicon oxide. (FIG. 6 (A))

Next, the gate electrode 605 is formed of polycrystalline silicon (doped with impurities such as phosphorus), tantalum, titanium, aluminum, or the like. Further, using this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by means such as ion doping, and an impurity region 606 is formed in the active layer 603 in a self-aligned manner. The active layer region below the gate electrode into which the impurity has not been introduced becomes a channel formation region. (FIG. 6 (B))

Next, an insulating film 607 of silicon oxide or the like is formed by means such as plasma CVD or APCVD (FIG. 6C), and this is anisotropically etched to form a side wall 608 adjacent to the side surface of the gate electrode. Form. (FIG. 6 (D))
Then, a metal film for forming a silicide such as titanium, chromium, tungsten, or molybdenum is formed over the entire surface (FIG. 6E), and this is reacted with the impurity region 606 to form a silicide region 610. Since the silicide is not formed in the impurity region 606 below the side wall (width x), the impurity region 606 becomes a normal source / drain 611. (FIG. 6 (F))
Finally, an interlayer insulator 612 is formed, a contact hole is formed in the source / drain region through the interlayer insulator, and a wiring / electrode 613 connected to the source / drain is formed using a metal material such as aluminum. (FIG. 6 (G))

The above method directly follows the salicide production process in a conventional semiconductor integrated circuit, and is a step which is difficult to apply as it is to a TFT production process on a glass substrate, or a step which is not preferable in terms of productivity. There is.
First, the active layer surface must be etched after doping. It is known that a thinner active layer of a TFT provides better characteristics. Therefore, when forming the side wall 608 in the step (D) of FIG. 6, it is necessary to pay attention to over-etching of the active layer.

However, since the thickness of the active layer is 150 nm or less, preferably 80 nm or less, the thickness of the insulating film 607 for forming the side wall needs to be approximately the same as that of the gate electrode 605. It is 300-800 nm, and slight over-etching is inevitable. In addition, the active layer doped with impurities (doped silicon) is much easier to etch than intrinsic silicon. For this reason, there is a problem that the active layer is largely etched during the formation of the side wall under normal conditions, or the etching cannot be performed with good reproducibility.

Second, it is difficult to form a side wall. The thickness of the insulating film 607 is 500 to 2000 nm. Normally, the thickness of the base film 602 provided on the substrate is 100 to 300 nm. Therefore, in this etching step, the base film is erroneously etched and the substrate is often exposed, and the yield is reduced. . In particular, since a glass substrate used for manufacturing a TFT contains many elements harmful to a silicon semiconductor, it is necessary to avoid such over-etching.
It is also difficult to finish the width of the side wall uniformly. This is because, during plasma dry etching such as reactive ion etching (RIE), unlike a silicon substrate used in a semiconductor integrated circuit, delicate control of plasma was difficult due to the insulating surface of the substrate. It is.
An object of the present invention is to solve the above-mentioned problems and to provide a method for forming a salicide structure by further simplifying the process.

The present invention is characterized in that silicide is formed without using a side wall as conventionally used. That is, in the present invention, after forming a metal film for forming silicide, doping of the source / drain is basically performed.
According to the first aspect of the present invention, (A) a semiconductor active layer is formed on an insulating surface, a first insulating film is formed on the active layer, and a film of a gate electrode material is formed on the first insulating film using an anodizable material. (B) a step of forming a gate electrode selectively by providing a mask film on the gate electrode material and etching the gate electrode material using the mask film; and (C) forming an electrode on the gate electrode. A step of forming a porous first anodic oxide mainly on the side surface of the gate electrode by applying a current in a solution; a step of (D) removing the mask film; and (E) an electrolytic solution applied to the gate electrode. Forming a barrier-type second anodic oxide on the side and top surfaces of the gate electrode by applying a current therein (F) using the first anodic oxide as a mask to form the first insulating film Remove the etching Exposing the surface of the active layer and simultaneously forming a gate insulating film; (G) selectively removing the first anodic oxide; and (H) covering the gate electrode and the gate insulating film. Step of forming a metal film for forming silicide (I) Step of selectively introducing an N-type or P-type impurity element into the active layer through the metal film using the gate electrode and the gate insulating film as a mask And (J) selectively forming a silicide region in the active layer by selectively reacting the metal film with the active layer. (K) removing the metal film that has not reacted in the step (J). Process.

Among them, the order of the steps (A) to (H) cannot be changed, but the steps (I) to (K) can be changed, and the following two types of configurations are possible by combining them. . That is,
First configuration Step I → Step J → Step K
Second configuration Step J → Step I → Step K
It is. Here, in the first configuration, in the process J, the N-type or P-type impurity doped in the process I can be activated. However, in the second configuration, between the process I and the process K, Alternatively, it is desirable to provide an activation step separately after the step K.
In the step (J) or after the step, N-type or P-type impurities may be activated by irradiating a laser or an equivalent strong light. Further, the step (J) may be performed by thermal annealing at 300 to 500 ° C.

に お い て In the first aspect of the present invention, the barrier type anodic oxide is generally an anodic oxide obtained by gradually increasing an applied voltage in a substantially neutral electrolytic solution, and has a dense and high withstand voltage. On the other hand, a porous anodic oxide is an anodic oxide obtained by performing formation of an anodic oxide and local etching thereof in parallel, and generally, in an acidic electrolytic solution having a hydrogen ion concentration pH of less than 2, It is obtained by applying a constant low voltage.

Especially, so-called barrier type anodic oxide is difficult to etch, whereas porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, it is characterized in that other materials constituting the TFT, for example, silicon and silicon oxide can be treated without causing any damage. Further, in both the barrier type and the porous type, anodic oxide is extremely difficult to be etched by dry etching. In particular, the feature is that the selectivity is sufficiently large in etching with silicon oxide.

The second aspect of the present invention is that
(A) a step of forming a semiconductor active layer on an insulating surface; (b) a step of selectively providing a doping mask on the active layer; and (c) a metal for forming a silicide over the active layer and the doping mask. Forming a film; (d) selectively introducing an N-type or P-type impurity element into the active layer through the metal film; and (e) selectively reacting the metal film with the active layer. (F) a step of selectively forming a silicide region in the active layer; and (f) a step of removing a metal film that has not reacted in the step (e).

Among them, the order of the steps (a) to (c) cannot be changed, but the steps (d) to (f) can be changed, and the following two types of configurations are possible by combining them. . That is,
Third configuration Step d → Step e → Step f
Fourth configuration Step e → Step d → Step f
It is.
More generally, in the present invention, it is conditioned that step (c) is before steps (d) and (f) and that step (d) is before step (e). .
Here, in the third configuration, in the step e, the N-type or P-type impurity doped in the step d can be activated, but in the fourth configuration, the steps d and f It is desirable to provide an activation step separately during or after the step f.

In step (e) or after the step, N-type or P-type impurities may be activated by irradiating a laser or equivalent strong light. Further, the step (e) may be performed by thermal annealing at 300 to 500 ° C.

The second aspect of the present invention may be a bottom gate type TFT or a top gate type TFT. In particular, in the case of a top gate type TFT, the gate electrode and the gate insulating film may be used as the above-mentioned doping mask. On the other hand, in the bottom gate type TFT, it is preferable to use a mask for source / drain doping as a doping mask.
In the second step (d) of the present invention, the substrate is irradiated with ions containing an N-type or P-type impurity element with an inclination of 30 ° or more with respect to the substrate, so that a part of the lower part of the doping mask is irradiated. It is good to dope up to.

As described above, in the first and second embodiments of the present invention, a salicide structure can be obtained without using the side wall obtained by anisotropic etching. A feature of the present invention is that after forming a metal film, impurity ions are implanted through the metal film to form a source / drain. That is, since the gate insulating film containing silicon oxide as a main component is etched in the state of intrinsic silicon having a high etching selectivity with silicon oxide or the like, there is no over-etching of the active layer. Further, N-type / P-type impurities are implanted into the silicide region, so that an ohmic contact between the silicide region and the metal electrode can be obtained even at a lower concentration.

In the present invention, since there is no step of etching silicon oxide on the surface of doped silicon having a low selectivity with respect to silicon oxide, a TFT can be manufactured with high yield. The characteristics of the TFT obtained by the present invention are, of course, not inferior to those of the conventional TFT having a salicide structure.
In the present invention, the width of the source / drain (the region 113 in FIG. 1 and the region 310 in FIG. 3) is formed with extremely high precision by means such as anodic oxidation and oblique ion implantation. A TFT circuit is obtained.

Although the embodiments have been described mainly on TFTs on a glass substrate, the TFTs of the present invention can be formed on glass or organic resin even when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed. It is needless to say that the same is formed in any case, but in any case, it is formed on the insulating surface.

FIG. 1 shows this embodiment. First, a silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 102 on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 101. As a method of forming the oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film in which TEOS is decomposed and deposited by a plasma CVD method may be used.

(5) Thereafter, an amorphous silicon film was deposited in a thickness of 30 to 500 nm, preferably 50 to 100 nm by a plasma CVD method or an LPCVD method, and was left in a reducing atmosphere at 550 to 600 ° C. for 24 hours to be crystallized. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was patterned to form the island regions 103. Further, a silicon oxide film 104 having a thickness of 70 to 150 nm was formed thereon by a sputtering method.

Then, an aluminum (containing 1 to 5 wt% Zr (zirconium) or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 100 to 3000 nm was formed by an electron beam evaporation method or a sputtering method. Then, a photoresist (for example, OFPR800 / 30cp, manufactured by Tokyo Ohka) was formed by spin coating. As a material of the mask film, a material which can be etched with photosensitive polyimide or ordinary polyimide may be used.

If an aluminum oxide film having a thickness of 10 to 100 nm is formed on the surface by anodic oxidation before forming the photoresist, adhesion to the photoresist is good, and current leakage from the photoresist is suppressed. This was effective in forming the porous anodic oxide only on the side surfaces in the subsequent anodic oxidation step.
Thereafter, the photoresist and the aluminum film were patterned to form a mask 106, and the aluminum film was etched using the mask to form a gate electrode 105. The process was moved to the next step while leaving the mask 106 as it was. (Fig. 1 (A))

{Circle around (5)} Anodized by passing a current through the electrolytic solution to form an anodic oxide 107 having a thickness of 300 to 600 nm, for example, 500 nm. The anodic oxidation may be performed using a 3 to 20% aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and applying a constant current of 10 to 30 V to the gate electrode. It is desirable that the hydrogen ion concentration pH of the solution is less than 2. The optimum pH depends on the type of the electrolytic solution, but is 0.9 to 1.0 in the case of oxalic acid. In this case, a thick anodic oxide of 500 nm or more can be formed at a low voltage of about 10 to 30 V. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.) having a pH of 0.9 to 1.0, and anodic oxidation was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (FIG. 1 (B))

Next, the mask 106 was removed, and a current was again applied to the gate electrode in the electrolytic solution so that the voltage increased at 1 to 10 V / min. This time, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 containing at least one of 3 to 10% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. As a result, a barrier-type anodic oxide 108 was formed on the upper and side surfaces of the gate electrode. The thickness of the anodic oxide 108 was proportional to the applied voltage, and a 200 nm anodic oxide was formed at an applied voltage of 150 V. (Fig. 1 (C))

It should be noted that, although barrier type anodic oxidation is a later step, barrier type anodic oxide is not formed outside the porous anodic oxide, but barrier type anodic oxide 108 It is formed between the porous anodic oxide 107 and the gate electrode 105. For a phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more the etching rate of the barrier anodic oxide. For this reason, when etching the porous anodic oxide with a phosphoric acid-based etchant later, the inner gate electrode can be protected by the barrier type anodic oxide 108.

After that, the silicon oxide film 104 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by making the selectivity between silicon and silicon oxide sufficiently large. In the present invention, since the active layer is intrinsic silicon, the etching selectivity with silicon oxide is sufficiently large. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched, and only the silicon oxide film 104 is etched. The silicon oxide film (gate insulating film) 110 under the porous anodic oxide 107 remained without being etched. (Fig. 1 (D))

In this embodiment, the gate electrode is made of aluminum. However, even if the gate electrode is made of another material (for example, tantalum or titanium is used as a main component), if the insulating film 104 contains silicon oxide as a main component, a fluorine-based material is used. When dry etching is performed using an etching gas (for example, NF ₃ or SF ₆ ), the insulating film 104 made of silicon oxide is quickly etched, but the etching rates of tantalum oxide and titanium oxide are sufficiently small, so that the insulating film 104 can be selectively etched.

Further, wet etching can be used, and a hydrofluoric acid-based etchant such as 1/100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, titanium oxide, or the like is sufficiently small, so that the insulating film 104 can be selectively etched.
Thereafter, the porous anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid, and nitric acid. In this etching, only the anodic oxide 107 was etched, and the etching rate was about 60 nm / min. The gate insulating film 110 thereunder remained as it was.

Further, a coating of an appropriate metal, for example, titanium, chromium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 111 having a thickness of 20 to 200 nm was formed on the entire surface by sputtering. (FIG. 1 (E))
Then, an impurity was implanted into the active layer 103 of the TFT in a self-aligning manner by using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film 110 by ion doping.

In this embodiment, phosphine (PH ₃ ) was used as the doping gas. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 120 kV. For this reason, the doping impurities are mainly injected into the region 113 having the width y, and the region becomes an N-type impurity region. On the other hand, many impurities passed through the region 112, and the impurity concentration was rather lowered. Diborane (B ₂ H ₆ ) may be used as a doping gas to form a P-type impurity region. (FIG. 1 (F))

In this embodiment, the doping is performed only once. However, the doping may be performed twice by adjusting the voltage so that the region 112 is also doped. Further, the doping may be performed so that the impurity concentration of the region 113 is lower than the impurity concentration of the region 112 by 1 to 3 digits.
Thereafter, thermal annealing at 450 ° C. was performed for 1 to 5 hours. As a result, the doping impurities were activated, and the titanium film 111 and silicon in the region 112 reacted to form a silicide region 114. Since the doped silicon has high reactivity, silicidation was sufficiently performed even at a low temperature such as 450 ° C. On the other hand, the region 113 not in contact with the titanium film became the source / drain.

In this step, an infrared laser such as an Nd: YAG laser (preferably Q-switched pulse oscillation), a visible laser such as a second harmonic thereof, and various ultraviolet lasers using excimers such as KrF, XeCl, and ArF are used. Irradiation, a so-called optical annealing method, can also be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

ラ ン プ Alternatively, lamp annealing by irradiation of non-coherent visible light or near-infrared light may be used. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens seconds at 1000 ° C. so that the surface to be irradiated is about 600 to 1000 ° C. Annealing by near-infrared rays (for example, 1200 nm infrared rays) selectively absorbs near-infrared rays into a silicon semiconductor, does not heat the glass substrate so much, and shortens the irradiation time for one shot, thereby suppressing heating of the glass substrate. Can be very useful.

(4) After the silicide region 114 was formed as described above, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia, and water were mixed at a ratio of 5: 2: 2. The titanium film other than the portion in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film 110 and the anodic oxide film 108) remained in a metal state as it was, but could be removed by this etching. On the other hand, the titanium silicide in the silicide region 112 was not etched, and could be left.

(4) Finally, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 115 on the entire surface by a CVD method. Then, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 116 and 117 were formed. Thus, an N-channel TFT is completed. The contact portion of the aluminum wiring is made of titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so that a highly reliable contact was obtained.

Further, when titanium nitride, for example, is formed as a barrier metal between the aluminum electrodes 116 and 117 and the silicide region 114, the reliability can be further improved. In this embodiment, the sheet resistance in the silicide region was 10 to 50 Ω / □. As a result, a TFT having good frequency characteristics and little hot carrier deterioration even at a high drain voltage could be manufactured. (Fig. 1 (G))
According to the method disclosed in this embodiment, a P-channel TFT and a CMOS circuit can be similarly manufactured.

This embodiment will be described with reference to FIG. First, an underlying silicon oxide film 302 was deposited over a glass substrate 301, and an amorphous silicon film having a thickness of 50 nm was formed using crystalline silicon. Thereafter, this was left in a reducing atmosphere at 550 to 600 ° C. for 8 to 24 hours to be crystallized. At this time, a trace amount of a catalyst element such as nickel which promotes crystallization may be added. The crystallized silicon film was irradiated with a KrF excimer laser (wavelength: 248 nm) to further improve the crystallinity. Although the energy density of the laser depends on the crystallinity of the silicon film, favorable results were obtained at 200 to 350 mJ / cm ² . The optimum energy density also depends on the substrate temperature during laser irradiation. The crystalline silicon film thus obtained was etched to form an active layer 303.

Further, a gate insulating film 304 of silicon oxide having a thickness of 150 nm was formed to cover the active layer 303. Then, an aluminum film having a thickness of 500 nm and containing 0.1 to 0.3 wt% of Sc was formed by a sputtering method, and this was etched to form a gate electrode 305. Thereafter, this was anodized to form an anodic oxide 306 on its upper surface and side surfaces.
The anodic oxidation was performed by immersing the substrate in a 1-3% ethylene glycol tartrate solution adjusted to pH ≒ 7 with ammonia, using platinum as a cathode and an aluminum gate electrode 305 as an anode. The anodic oxidation was first completed by raising the voltage to a specific voltage at a constant current and maintaining the state for one hour. The thickness of the anodic oxide 306 was 200 nm. (FIG. 3A)

Next, the silicon oxide film 304 was etched using the gate electrode and the anodic oxide as a mask. A dry etching method was used for the etching, and CHF ₃ was used as an etching gas at that time. Aluminum oxide, which is an anodic oxide, is hardly etched by the dry etching method, and only the silicon oxide film is selectively etched. Of course, a wet etching method may be used. Thus, the active layer of the N-channel TFT was exposed. Then, a platinum (platinum) film 308 having a thickness of 20 to 200 nm was formed by a sputtering method. (FIG. 3 (B))

{Circle around (2)} Impurity ions were obliquely irradiated to form impurity regions 107. As a result, the impurity region also goes under the anodic oxide 306. The formation of the impurity region in each of the above steps is performed by irradiating the substrate with obliquely accelerated impurity ions. At that time, a method in which the substrate was rotated while being tilted with respect to the direction of the ion source (rotating oblique ion implantation method) was used.

The apparatus shown in FIG. 2 was used for the oblique rotation ion implantation. The apparatus shown in FIG. 2 includes a chamber 201, a sample holder (substrate holder) 202 disposed therein, an anode electrode 203, a power supply 204 for supplying a high voltage to the anode electrode 203, and a grid electrode 205. . The angle θ of the sample holder 202 can be freely changed so that ions can be implanted from an oblique direction. The sample holder has a rotation mechanism so that it can rotate during ion implantation. (Fig. 2)

Further, the anode electrode 203 is structured so that a high voltage can be applied. As the maximum voltage, for example, a voltage of 120 kV or more is applied. By the voltage applied to the anode, the impurity ions 206 ionized by RF discharge or the like near the grid electrode 205 are accelerated in the direction of the substrate 207 (sample) disposed on the sample holder 202. As a result, accelerated impurity ions are implanted into the substrate. (Fig. 2)

In this embodiment, the dose is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage is 60 to 120 kV. For example, the dose is 4 × 10 ¹³ atoms / cm ² and the acceleration voltage is 110 kV. As a result, an N-type impurity region 309 was formed, and this region was formed so as to overlap the gate electrode 305. (FIG. 3 (C))

ア ニ ー ル Then, annealing was performed at 400 to 550 ° C., for example, 450 ° C. for 1 hour. As a result, silicide was formed in a portion where the platinum film and the silicon film were in close contact with each other, and at the same time, the doped impurity was activated. Since the platinum film did not react with silicon oxide or aluminum oxide, the silicon oxide and the platinum film on the anodic oxide remained unreacted. This was easily removed. Thus, a silicide region 311 was formed in a portion corresponding to the source / drain. Further, in the N-type impurity region 309, a portion having a width x that did not become silicide remained as the source / drain region 310 in the gate electrode portion. (FIG. 3 (D))

(4) Next, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulating film 312 by a plasma CVD method. Then, the interlayer insulating film 312 was etched to form contact holes in the source / drain of the TFT. Then, an aluminum film was formed by a sputtering method, and patterning and etching were performed to form source / drain electrodes 313 and 314. (FIG. 3 (E))

In the above silicidation process, depending on how the silicide reaction proceeds, a case where silicide is formed to the bottom of the active layer as shown in FIGS. 3D and 3E, or a case where the active layer is formed as shown in FIG. May be formed only on the surface of the substrate. Naturally, the former has a smaller sheet resistance at the portion corresponding to the source / drain, but the latter has a sufficiently low resistance. Therefore, in any case, the sheet resistance of the source / drain is substantially determined by the width x of the impurity region 310.

In connection with the above, the thickness of the silicide is selected according to the sheet resistance required in the region corresponding to the source / drain. If a sheet resistance of 10 to 100 Ω / □ is to be achieved, the specific resistance of the silicide is 0.1 to 1 mΩ · cm, and therefore the appropriate thickness of the silicide is 10 to 1000 nm.
In addition, when forming silicide, in addition to thermal annealing, strong light such as laser may be applied to the metal film to react with the underlying silicon semiconductor film to form silicide. Further, the laser light may be applied from the substrate side. If a laser is used, a pulsed laser is preferred. Since the irradiation time of a continuous wave laser is long, there is a danger that the object to be irradiated is separated by expansion due to heat, and there is also thermal damage to the substrate.

This embodiment will be described with reference to FIG. A base film 402, an active layer 403, a silicon oxide film 404 functioning as a gate insulating film, and a gate electrode 405 capable of anodic oxidation are formed on a glass substrate 401, and the upper and side surfaces of the gate electrode are subjected to anodic oxidation. The product 406 was obtained.
Further, the silicon oxide film 404 was etched to obtain a gate insulating film 407. Then, a palladium film 408 having a thickness of 100 nm was entirely formed by a sputtering method. (FIG. 4 (B))

Then, using the apparatus shown in FIG. 2 with the gate electrode and the anodic oxide as a mask, impurity ions were obliquely irradiated to form impurity regions 409 in the active layer. At this time, the non-tree density was lower than that in the normal case. For example, the dose is set to 1 × 10 ^{12 to} 5 × 10 ¹⁴ atoms / cm ² . (FIG. 4 (C))
Next, ions of the same conductivity type were irradiated from almost the vertical direction, and the impurity concentration was made higher than that of the impurity region 409 previously formed. The dose at this time was suitably 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² . As a result, a low-concentration impurity region having a width x remained under the anodic oxide, and the other regions became high-concentration impurity regions 410. (FIG. 4 (D))

Thereafter, the palladium film and the impurity region were reacted to form a silicide region 412. However, the silicide reaction did not reach the impurity region 409 below the anodic oxide, and the impurity region remained. Further, since the metal film formed on the anodic oxide remained in a state where it hardly reacted, the unreacted palladium film 408 could be easily etched. (FIG. 4E)
Thereafter, an interlayer insulator 413 was deposited, a contact hole was formed in the silicide region, and metal wiring / electrodes 414 and 415 were formed to complete the TFT. (FIG. 4 (F))

In this embodiment, the source / drain regions are doped with low-concentration impurities. In a normal TFT, doping with such a low concentration of impurities reduces the electric field near the drain, reduces the deterioration due to hot carrier injection, and also reduces the source / drain leakage current. For example, in the case where the impurity region 310 in FIG. 3 is made to have a low concentration, since the impurity concentration is low, the NI junction (PI junction in the case of a P-channel type TFT) is shallow, and the distance between the silicide regions is small. Because of the short length, when the drain voltage is high, the leak current between the source and the drain tends to increase. In order to prevent this, it is effective to perform high concentration doping as shown in FIG.

FIG. 5 shows this embodiment. First, gate wiring / electrodes 502 and 503 were formed on a substrate (Corning 7059, 100 mm × 100 mm) 501. For the gate wiring and electrodes, tantalum having a thickness of 300 nm was used. The surface of the gate electrode may be treated by anodic oxidation to enhance the insulating properties.
After that, a silicon nitride film 504 having a thickness of 300 to 600 nm, for example, 400 nm was deposited by a plasma CVD method. This also functions as a gate insulating film. Then, an amorphous silicon film having a thickness of 30 to 100 nm, for example, 50 nm was formed by a plasma CVD method. Then, this was etched to form an active layer 505. (FIG. 5 (A))

Further, a silicon oxide film having a thickness of 300 to 600 nm, for example, 200 nm was deposited by a plasma CVD method. Then, a photoresist was applied to the entire surface and exposed from the back surface of the substrate, thereby performing patterning using the gate electrodes / wirings 502 and 503 as a mask. Then, using this pattern, the silicon oxide film was etched to form doping masks 506 and 507. (FIG. 5 (B))
Thereafter, a titanium film 508 having a thickness of 50 nm was formed by a sputtering method. (FIG. 5 (C))

Next, an N-type impurity was implanted into the active layer 505 by rotating oblique ion doping using the apparatus of FIG. 2 to form an N-type impurity region (source / drain region) 509. Phosphine (PH ₃ ) was used as a doping gas. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 90 kV. (FIG. 5 (D))

Then, by performing thermal annealing at 300 to 450 ° C., for example, at 350 ° C. for 10 to 60 minutes, titanium and silicon were reacted to form a silicide region 510. Thereafter, the remaining titanium film was etched. (FIG. 5E)
Further, an aluminum film having a thickness of 500 nm was formed on the entire surface by a sputtering method, and this was etched to form wirings 511 and 512. The wirings 511 and 512 contact the previously formed silicide region. Thus, the TFT was completed. (FIG. 5 (F))

FIG. 7 shows this embodiment. As in the first embodiment, a base oxide film 702, an island region 703 of a crystalline silicon film, a gate insulating film 704 of silicon oxide having a thickness of 150 nm on a glass substrate 701, aluminum (1 to 5 wt% Zr (zirconium ), A barrier anodic oxide 706 and a porous anodic oxide 707 were formed. (Corresponding to FIGS. 7A and 1D)
Thereafter, the porous anodic oxide 707 was etched using a mixed acid of phosphoric acid, acetic acid, and nitric acid. Further, a chromium film having a thickness of 20 to 200 nm was formed on the entire surface by a sputtering method. Chromium reacted with silicon in the active layer during the film formation by sputtering, and 2 to 10 nm of the surface of the active layer became silicide (not shown). (FIG. 7 (B))

Thereafter, thermal annealing at 450 ° C. was performed for 1 to 5 hours. As a result, the chromium film 708 and silicon in the active layer 703 reacted to form a silicide region 709. On the other hand, no silicide was formed in a region of the active layer not in contact with the chromium film. (FIG. 7 (C))
In this step, an infrared laser such as an Nd: YAG laser (preferably Q-switched pulse oscillation), a visible laser such as a second harmonic thereof, and various ultraviolet lasers using excimers such as KrF, XeCl, and ArF are used. Irradiation, a so-called optical annealing method, can also be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

ラ ン プ Alternatively, lamp annealing by irradiation of non-coherent visible light or near-infrared light may be used. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens seconds at 1000 ° C. so that the surface to be irradiated is about 600 to 1000 ° C. Annealing by near-infrared rays (for example, 1200 nm infrared rays) selectively absorbs near-infrared rays into a silicon semiconductor, does not heat the glass substrate so much, and shortens the irradiation time for one shot, thereby suppressing heating of the glass substrate. Can be very useful.

Then, impurities were implanted into the active layer 703 of the TFT in a self-aligning manner by using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film 704 as a mask by an ion doping method.
In this embodiment, phosphine (PH ₃ ) was used as the doping gas. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 120 kV. For this reason, the doping impurities are mainly injected into the active layer region 710 below the gate insulating film 704, and the region becomes an N-type impurity region. (FIG. 7 (D))

In this embodiment, the doping is performed only once. However, the doping may be performed twice by adjusting the voltage so that the region 709 is also doped. Further, doping may be performed such that the impurity concentration of the region 710 is lower by one to three orders of magnitude than the impurity concentration of the region 709.
Then, the doped impurities were activated. In this embodiment, thermal annealing at 300 to 500 ° C., for example, 450 ° C. is performed for 0.1 to 2 hours, for example, 1 hour. This step may be performed using the laser or the RTA method as described above. As described above, since the activation was performed while the chromium film was provided, the formation of silicide could be further promoted.

After that, the unreacted chromium film was etched, and a 300-nm-thick silicon oxide film was formed as an interlayer insulator 711 over the entire surface by a CVD method. Then, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 712 and 713 were formed. Thus, an N-channel TFT is completed.
In this embodiment, the activation of the doped impurity is performed before the chromium film is removed, but may be performed after the chromium film is removed. In this case, particularly when a laser or RTA method is used, it is not necessary to consider light reflection by the chromium film, so that activation can be performed effectively.

A method for manufacturing a TFT according to Example 1 will be described. The conceptual diagram of the doping apparatus used in Examples 2-4 is shown. A method for manufacturing a TFT according to Example 2 will be described. A method for manufacturing a TFT according to Example 3 will be described. A method for manufacturing a TFT according to Example 4 will be described. A method for manufacturing a TFT according to a conventional method will be described. A method for manufacturing a TFT according to Example 5 will be described.

Explanation of reference numerals

101 Insulating substrate 102 Base oxide film (silicon oxide)
103 active layer 104 insulating film (silicon oxide)
105 Gate electrode (aluminum)
106 Mask film (photoresist)
107 Anodic oxide (porous)
108 Anodic oxide (barrier type)
109 Edge of gate insulating film 110 Gate insulating film 111 Metal coating (titanium)
112, 113 N-type impurity region 114 Silicide region 115 Interlayer insulator 116, 117 Metal wiring / electrode (aluminum)

Claims (17)

Forming a silicon film on the insulating surface,
Forming an insulating film on the silicon film,
Forming a gate electrode on the insulating film,
Removing the insulating film to expose the silicon film,
Forming a metal film covering the silicon film and the gate electrode;
Forming impurity regions by selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate;
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
Removing the metal coating,
A method for manufacturing a semiconductor device, wherein a part of the impurity region overlaps below a gate electrode, and the impurity ions are introduced through the insulating film. Forming a silicon film on the insulating surface,
Forming an insulating film on the silicon film,
Forming a gate electrode on the insulating film,
Removing the insulating film to expose the silicon film,
Forming a metal film covering the silicon film and the gate electrode;
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
Forming impurity regions by selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate;
Removing the metal coating,
A method for manufacturing a semiconductor device, wherein a part of the impurity region overlaps below a gate electrode, and the impurity ions are introduced through the insulating film. Forming a silicon film on the insulating surface,
Forming an insulating film on the silicon film,
Forming a gate electrode on the insulating film,
Removing the insulating film to expose the silicon film,
Forming a metal film covering the silicon film and the gate electrode;
By selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate, a low-concentration impurity region is formed,
In the silicon film, a high-concentration impurity region is formed by selectively introducing impurity ions of the same conductivity type as the conductivity-type impurity ions perpendicularly to the substrate,
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
Removing the metal coating,
A method of manufacturing a semiconductor device, wherein a part of the low-concentration impurity region overlaps below a gate electrode, and the impurity ions are introduced through the insulating film. Forming a silicon film on the insulating surface,
Forming an insulating film on the silicon film,
Forming a gate electrode on the insulating film,
Removing the insulating film to expose the silicon film,
Forming a metal film covering the silicon film and the gate electrode;
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
By selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate, a low-concentration impurity region is formed,
By selectively introducing impurity ions of the same conductivity type as the impurity ions of the conductivity type into the silicon film perpendicularly to the substrate, a high-concentration impurity region is formed,
Removing the metal coating,
A method of manufacturing a semiconductor device, wherein a part of the low-concentration impurity region overlaps below a gate electrode, and the impurity ions are introduced through the insulating film. Forming a gate electrode on the insulating surface,
Forming a first insulating film on the gate electrode;
Forming a silicon film on the first insulating film;
Forming an active layer by selectively removing the silicon film;
Forming a second insulating film covering the active layer and the first insulating film;
Removing a part of the second insulating film to expose a part of the active layer;
Forming a metal film covering a part of the active layer, the first insulating film, and the second insulating film;
Forming impurity regions by selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate;
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
Removing the metal coating,
A method for manufacturing a semiconductor device, wherein a part of the impurity region overlaps a gate electrode, and the impurity ions are introduced through the second insulating film. Forming a gate electrode on the insulating surface,
Forming a first insulating film on the gate electrode;
Forming a silicon film on the first insulating film;
Forming an active layer by selectively removing the silicon film;
Forming a second insulating film covering the active layer and the first insulating film;
Removing a part of the second insulating film to expose a part of the active layer;
Forming a metal coating covering a part of the active layer, the first insulating film and the second insulating film,
Forming a silicide region selectively in the silicon film by selectively reacting the silicon film and the metal film by annealing;
Forming impurity regions by selectively introducing conductive impurity ions into the silicon film obliquely with respect to the substrate;
Removing the metal coating,
A method for manufacturing a semiconductor device, wherein a part of the impurity region overlaps a gate electrode, and the impurity ions are introduced through the second insulating film. (7) The method for manufacturing a semiconductor device according to any one of (1) to (6), wherein the conductivity type is N-type or P-type. A method according to any one of claims 1 to 7, wherein the annealing is any one of thermal annealing, optical annealing, and lamp annealing. A method according to any one of claims 1 to 8, wherein the impurity region is activated by light annealing or thermal annealing. (10) The method for manufacturing a semiconductor device according to any one of (1) to (9), wherein an incident angle at which the impurity ions are obliquely introduced into the substrate is 30 degrees or more. A pair of first impurity regions formed on an insulating surface, a pair of second impurity regions formed between the pair of first impurity regions, and between the pair of second impurity regions. A semiconductor film having a channel formation region formed;
A gate insulating film formed on the semiconductor film;
A gate electrode formed on the gate insulating film,
In a semiconductor device having
The concentration of the first impurity region is higher than the concentration of the second impurity region,
A part of the channel forming region and the pair of second impurity regions is formed below the gate electrode via the gate insulating film;
Silicide is formed on the surfaces of the pair of first impurity regions,
The semiconductor device, wherein the silicide is connected to a metal wiring. A pair of first impurity regions formed on an insulating surface, a pair of second impurity regions formed between the pair of first impurity regions, and between the pair of second impurity regions. A semiconductor film having a channel formation region formed;
A gate insulating film formed on the semiconductor film;
A gate electrode formed on the gate insulating film,
In a semiconductor device having
The concentration of the first impurity region is higher than the concentration of the second impurity region,
A part of the channel forming region and the pair of second impurity regions is formed below the gate electrode via the gate insulating film;
A silicide having a thickness of 10 to 1000 nm is formed on surfaces of the pair of first impurity regions,
The semiconductor device, wherein the silicide is connected to a metal wiring. The semiconductor device according to claim 11 or 12, wherein the silicide contains any one of titanium, chromium, nickel, molybdenum, tungsten, platinum, and palladium. 14. The semiconductor device according to claim 11, wherein the sheet resistance of the silicide is 10 to 100 Ω / □. The semiconductor device according to any one of claims 11 to 14, wherein the specific resistance of the silicide is 0.1 to 1 mΩ · cm. 16. The semiconductor device according to claim 11, wherein the silicide is connected to the metal wiring via a barrier metal. 17. The semiconductor device according to claim 16, wherein the barrier metal is titanium nitride.

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