JP2004006730A - Semiconductor memory element and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor memory capable of a high speed operation by fabricating TFTs and semiconductor elements on a substrate having an insulating surface. <P>SOLUTION: Strain or stress incident to crystallization can be concentrated to a region other than a recess by depositing a semiconductor film on an insulating film provided with a linear recess and irradiating the semiconductor film with a laser beam thereby pouring molten semiconductor into the recess. When the surface of crystalline semiconductor film is removed by etching, a crystalline semiconductor film having a side face covered with the sidewall of the recess and not containing a crystal grain boundary other than a twin is formed in the recess region. Since it can be employed as a channel region of a semiconductor element or a TFT, a highly reliable semiconductor element and a TFT exhibiting a high field effect mobility can be fabricated while suppressing variation in characteristics resulting in a highly reliable semiconductor memory capable of high speed operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, particularly to a thin film transistor having a charge storage layer. In addition, the present invention relates to a thin film transistor having a charge storage layer and a semiconductor memory device in which the thin film transistor is formed over a substrate having an insulating surface.
[0002]
[Prior art]
An EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory are known as memories representing a semiconductor nonvolatile memory. Since these are nonvolatile, unlike DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), which are representative of semiconductor memories, data is not lost even when the power is turned off. Further, when compared with a magnetic disk representing another nonvolatile memory, the magnetic disk has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like.
[0003]
As described above, the semiconductor non-volatile memory has characteristics suitable for portable devices, and application development to portable devices is being promoted. In particular, flash memories with a high integration density have been widely applied, and in recent years, multi-value memories with further improved integration have begun to be commercialized. Of course, these are nonvolatile memories on a single crystal silicon substrate (for example, see Non-Patent Document 1).
[0004]
[Non-patent document 1]
Fujio Masuzoka, 7 others, "Flash Memory Technology Forum 2000", Science Forum Co., Ltd., July 18, 2000
[0005]
On the other hand, with the spread of mobile devices having a display unit such as a mobile phone, a demand for a system-on-panel in which a display unit and a logic circuit unit are integrally formed on a substrate having an insulating surface is increasing. Accordingly, a technique for manufacturing a nonvolatile memory on a substrate having an insulating surface has been required.
[0006]
[Problems to be solved by the invention]
When a nonvolatile memory is manufactured over a substrate having an insulating surface, a memory cell array is composed of semiconductor memory elements, and peripheral circuits such as a decoder circuit for selecting a memory cell and a write / read circuit are thin film transistors (hereinafter, referred to as TFTs). Is possible.
[0007]
Note that, in the present invention, a semiconductor memory element refers to a thin film transistor having a charge storage layer surrounded by an insulating film between a semiconductor active layer and a gate electrode, such as a structure having a floating gate electrode, an MNOS structure, A thin film transistor having a structure is included in the category.
[0008]
When considering such a non-volatile memory, it is important to improve the reliability of a semiconductor storage element involving charge injection and discharge into a charge storage layer, and to improve the operation speed of peripheral circuits.
[0009]
First, there is the following structural problem regarding the reliability of the semiconductor memory element. FIG. 2 shows a structure of a typical semiconductor memory element manufactured on a substrate having an insulating surface, where (A), (B), and (C) are a plan view, a cross-sectional view in a channel length direction, respectively. And a cross-sectional view in the channel width direction. In FIG. 2, in the semiconductor memory element, a semiconductor active layer 202, a first gate insulating film 203, a floating gate electrode 204, a second gate insulating film 205, and a control gate electrode 206 are stacked on a substrate 201 having an insulating surface. It has a structure. The semiconductor active layer 202 includes a channel region 207 and a high-concentration impurity region 208 to which an impurity of one conductivity type is added.
[0010]
Note that the floating gate electrode 204 is one form of a charge storage layer. Further, one of the high-concentration impurity regions 208 may partially overlap with the floating gate electrode 204 with the first gate insulating film 203 interposed therebetween.
[0011]
What matters with respect to the reliability of the semiconductor memory element is the shape of the end portion 209 of the semiconductor active layer. In the case of the semiconductor active layer shape as shown in FIG. 2, when a potential difference is applied between the control gate electrode and the active layer, an electric field is concentrated at a corner portion of the semiconductor active layer end portion, and a local portion at the semiconductor active layer end portion 209 is formed. Charge injection / release occurs. As a result, the first gate insulating film is intensively deteriorated at the semiconductor active layer end 209, and the reliability is reduced.
[0012]
In order to prevent local degradation of the first gate insulating film due to concentration of an electric field, it is effective to realize a structure of a semiconductor memory element having no region where the electric field concentrates, such as the semiconductor active layer end 209. is there.
[0013]
Next, with respect to the operation speed of the memory, it is important to manufacture TFTs and semiconductor storage elements with high characteristics on a substrate having an insulating surface.
[0014]
The technology for forming a TFT on a substrate having an insulating surface has been greatly advanced mainly through research and development of semiconductor display devices (typically, liquid crystal display devices and EL display devices). For example, a TFT using a polycrystalline silicon film has higher field-effect mobility (also referred to as mobility) than a TFT using an amorphous silicon film, and control of a display portion conventionally performed by a driving circuit outside the substrate is performed. Can be performed by a drive circuit formed on the same substrate as the pixels.
[0015]
In the future, from the viewpoint of the system-on-panel, further high-speed operation needs to be realized, and TFTs with higher characteristics are required.
[0016]
2. Description of the Related Art In recent years, as one of the notable techniques for forming a TFT over a substrate having an insulating surface, there is a method for forming a crystalline semiconductor film by irradiation with laser light. As the laser oscillation device, a gas laser typified by an excimer laser or a solid laser typified by a YAG laser is usually used. In particular, in Japanese Patent Application Laid-Open No. 2001-144027, Nd: YVO ₄ A solid-state laser oscillator such as a laser is used to irradiate the amorphous semiconductor film with laser light that is the second harmonic thereof to form a crystalline semiconductor film having a larger crystal grain size as compared with the conventional one, thereby manufacturing a TFT. The technology is disclosed.
[0017]
However, when an amorphous semiconductor film formed on a flat surface is crystallized by irradiating a laser beam, the crystal becomes polycrystalline, and the position of a crystal grain boundary including a crystal defect cannot be controlled. . In addition, distortions and cracks occur due to volume shrinkage of the semiconductor film accompanying the crystallization, thermal stress with the base, lattice mismatch, and the like, but this position could not be controlled.
[0018]
As a result, the crystallinity of the channel region of the TFT cannot be controlled, and eventually, individual device characteristics vary due to crystal grain boundaries and crystal defects contained in the channel region.
[0019]
That is, when a crystalline semiconductor film is formed by laser light irradiation, it is important to control the position of the crystal grain boundary and control the crystallinity of the channel region of the TFT.
[0020]
When realizing a high-speed operation of a memory, it is important to improve not only the TFT characteristics but also the characteristics of the semiconductor storage element at the same time. That is, the operation speed of the peripheral circuit is improved by the improvement of the TFT characteristics, and the driving capability of the semiconductor storage device is increased by the improvement of the characteristics of the semiconductor storage device, so that the read speed is improved.
[0021]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and realizes a semiconductor memory element having a structure in which electric field concentration does not occur at an end portion of an active layer in a channel region. By controlling TFTs, a TFT and a semiconductor memory device having high field-effect mobility and small variation without including crystal grain boundaries other than twins in the channel region can realize a highly reliable nonvolatile memory. It is an object of the present invention to provide a high-speed semiconductor memory device having the operation.
[0022]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory element according to the present invention comprises an insulating film having a linear concave portion formed on a substrate having an insulating surface, and an amorphous semiconductor film or a polycrystalline film formed on the insulating film. A semiconductor film is formed, a semiconductor film is melted and poured into a concave portion of the insulating film to form a crystalline semiconductor film that is crystallized, and a thickness of the crystalline semiconductor film is at least a depth of the concave portion at a portion where a channel region is formed. Etching the surface of the crystalline semiconductor film so as to form a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode which are in contact with the upper surface of the crystalline semiconductor film. It is assumed that.
[0023]
Further, the semiconductor memory device of the present invention has a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array has a plurality of linear concave portions arranged in a stripe shape on a substrate having an insulating surface. An insulating film provided with stripe-shaped concave portions is formed, an amorphous semiconductor film or a polycrystalline semiconductor film is formed over the insulating film, and the semiconductor film is melted and poured into the concave portions of the insulating film and crystallized. A semiconductor film is formed, and the surface of the crystalline semiconductor film is removed by etching so that the thickness of the crystalline semiconductor film is equal to or less than the depth of the concave portion at least in a portion where a channel region is formed. An unnecessary region of the crystalline semiconductor film is removed by etching, and a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode in contact with the upper surface of the crystalline semiconductor film are removed. It is characterized in that to form the.
[0024]
A semiconductor memory device having another structure of the present invention has a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array has a plurality of linear concave portions formed on a substrate having an insulating surface by stripes. Forming an insulating film provided with stripe-shaped concave portions arranged in a shape and inter-strip concave portions connecting between the stripe-shaped concave portions, forming an amorphous semiconductor film or a polycrystalline semiconductor film on the insulating film; A crystalline semiconductor film is formed by melting and pouring a semiconductor film into a concave portion of the film to form a crystalline semiconductor film, and the crystalline semiconductor film is formed so that the thickness of the crystalline semiconductor film is not more than the depth of the concave portion at least at a portion where a channel region is formed. The surface of the film is removed by etching, and unnecessary regions of the crystalline semiconductor film are removed by etching in accordance with the arrangement of the semiconductor storage elements and the connection between the semiconductor storage elements. The first gate insulating film in contact with the upper surface of the conductive film, a floating gate electrode, the second gate insulating film, and is characterized in forming a control gate electrode. In this configuration, the semiconductor film wiring connecting the semiconductor memory elements is formed by the crystalline semiconductor film formed in the recess between the stripes.
[0025]
A semiconductor memory device having another structure of the present invention has a memory cell array in which semiconductor memory elements are arranged in a matrix, and the memory cell array has a plurality of linear concave portions formed on a substrate having an insulating surface by stripes. Forming an insulating film provided with stripe-shaped concave portions arranged in a matrix, forming an amorphous semiconductor film or a polycrystalline semiconductor film on the insulating film, and melting and pouring the semiconductor film into the concave portions of the insulating film for crystallization; In a state where a crystalline semiconductor film is formed and a region serving as a semiconductor film wiring connecting a semiconductor memory element is masked with a photoresist, the thickness of the crystalline semiconductor film is at least the depth of the concave portion at a portion where a channel region is formed. The surface of the crystalline semiconductor film is removed by etching so as to be as follows, and the connection is made in accordance with the arrangement of the semiconductor storage elements and the arrangement of the semiconductor film wiring connecting the semiconductor storage elements. An unnecessary region of the crystalline semiconductor film is removed by etching to form a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode which are in contact with the upper surface of the crystalline semiconductor film. It is. In this structure, the semiconductor film wiring connecting the semiconductor memory elements is formed by the crystalline semiconductor film connected over the stripe-shaped concave portions without etching the surface of the crystalline semiconductor film.
[0026]
Note that a semiconductor memory device refers to a nonvolatile memory such as an electrically erasable and programmable read only memory (EEPROM) or a flash memory, and a general semiconductor device including such a nonvolatile memory as a semiconductor memory portion. For example, a microprocessor including a non-volatile memory as a semiconductor storage portion, a semiconductor display device (typically, a liquid crystal display device and an EL display device), and a device including these are included in the category.
[0027]
Note that the term “amorphous semiconductor film” in the present invention means not only a film having a completely amorphous structure in a narrow sense, but also a state in which fine crystal grains are contained, or a so-called microcrystalline semiconductor film, Includes a semiconductor film having a crystal structure. Typically, an amorphous silicon film is applied. In addition, an amorphous silicon germanium film, an amorphous silicon carbide film, or the like can be used. The polycrystalline semiconductor film is obtained by crystallizing these amorphous semiconductor films by a known method.
[0028]
FIG. 1 shows a typical structure of a semiconductor memory element constituting the above-described semiconductor memory device of the present invention, wherein (1), (2) and (3) are a plan view and a sectional view in the channel length direction, respectively. And a cross-sectional view in the channel width direction. In FIG. 1, a semiconductor memory element includes a crystalline semiconductor active layer 102 formed in a linear recess provided by insulating films 109 and 110, a first gate insulating film 103, a floating gate, on a substrate 101 having an insulating surface. It has a structure in which an electrode 104, a second gate insulating film 105, and a control gate electrode 106 are stacked. The crystalline semiconductor active layer 102 includes a channel region 107 and a high-concentration impurity region 108 to which an impurity of one conductivity type is added.
[0029]
Note that one of the high-concentration impurity regions 108 may partially overlap with the floating gate electrode 104 with the first gate insulating film 103 interposed therebetween.
[0030]
In the semiconductor memory element of the present invention, the channel region is formed by the step of etching and removing the surface of the crystalline semiconductor film so that the thickness of the crystalline semiconductor film is at least equal to or less than the depth of the recess at the portion where the channel region is formed. It is characterized in that the side surfaces of the crystalline semiconductor film are completely covered by the concave side walls.
[0031]
As shown in FIG. 1, the thickness of the crystalline semiconductor active layer may be smaller than the thickness of the insulating films 109 and 110, and the thickness of the crystalline semiconductor active layer may be smaller than the thickness of the insulating films 109 and 110. It may be the same.
[0032]
In the cross-sectional structure of the semiconductor memory element, since there is no corner at the interface between the semiconductor active layer and the first gate insulating film and the plane is flat, an electric field is concentrated at the edge of the semiconductor active layer, and charge injection / emission is locally caused. It doesn't happen. As a result, local deterioration of the first gate insulating film can be prevented, and high reliability can be realized.
[0033]
Note that the semiconductor memory device described above may include, on a substrate on which a memory cell is formed, a peripheral circuit such as a decoder circuit for selecting a memory cell, a write / read circuit, and another semiconductor integrated circuit. In that case, in order to realize high-speed operation of the memory, it is preferable that TFTs included in a peripheral circuit and another semiconductor integrated circuit be manufactured using the crystalline semiconductor film formed by the above-described method.
[0034]
The method for forming the crystalline semiconductor film will be further described.
[0035]
The above-described linear concave portions or stripe-shaped concave portions are provided to extend in the channel length direction. The concave portion has a width (channel width in the case of forming a channel forming region) of 0.01 μm or more and 2 μm or less, preferably 0.1-1 μm, and has a depth of 0.01 μm or more and 3 μm or less, preferably 0.1 μm. It is formed with a thickness of not less than 2 μm.
[0036]
As a means for melting and crystallizing the crystalline semiconductor film, a pulsed or continuous wave laser beam using a gas laser oscillator or a solid laser oscillator as a light source is used. The laser light to be irradiated is linearly condensed by an optical system, and its intensity distribution has a uniform region in the longitudinal direction and may have a distribution in the lateral direction. As the oscillation device, a rectangular beam solid laser oscillation device is applied, and particularly preferably, a slab laser oscillation device is applied.
[0037]
The amorphous semiconductor film or the polycrystalline semiconductor film is irradiated with laser light or intense light that is condensed in a linear shape and extended in the longitudinal direction, and the irradiation position of the laser light and the substrate on which the semiconductor film is formed are relatively positioned. Then, the laser beam scans a part or the whole surface to melt the semiconductor film, and crystallization or recrystallization is performed through that state. Laser light is scanned in a direction parallel to a linear concave portion formed in the insulating film or along a channel length direction of the transistor. Thereby, the crystal grows along the scanning direction of the laser beam, and it is possible to prevent the crystal grain boundary from intersecting with the channel length direction.
[0038]
When the depth of the concave portion is approximately equal to or greater than the thickness of the semiconductor film, the semiconductor melted by irradiation with laser light or strong light is aggregated and solidified in the concave portion by surface tension. At this time, by causing the crystal to grow from the bottom end of the concave portion, the strain generated due to the crystallization is concentrated in a region other than the concave portion. On the other hand, the crystalline semiconductor film formed so as to fill the concave portion can be released from the distortion. Then, the crystalline semiconductor film remaining around the recess including the crystal grain boundaries and crystal defects is removed by etching.
[0039]
The semiconductor memory element manufactured as described above is provided with a crystalline semiconductor film that does not include a crystal grain boundary other than a twin in a linear concave portion provided on an insulating surface.
[0040]
According to the present invention, in a semiconductor memory element and a TFT, it is possible to form a crystalline semiconductor film that does not include a crystal grain boundary other than a twin by specifying the location of a channel formation region. That is, by controlling the crystallinity of the channel region of the TFT and increasing the crystallinity of the channel region, a semiconductor memory element and a TFT with high field-effect mobility and small characteristic variations can be manufactured. As a result, it is possible to realize a semiconductor memory device that achieves a high-speed operation by increasing the peripheral circuit speed by improving the TFT characteristics and increasing the reading speed by improving the semiconductor memory element characteristics.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
As an embodiment of a semiconductor memory device of the present invention, a circuit configuration and an operation method of a nonvolatile memory will be described.
[0042]
The present invention is characterized by the structure of a semiconductor memory element, a semiconductor active layer, and the structure of a TFT and a semiconductor active layer constituting a peripheral circuit. The circuit configuration and operation method of a memory cell may use a known technique. In this embodiment, a circuit configuration and an operation method of a NOR flash memory as a typical nonvolatile memory will be briefly described.
[0043]
FIG. 7 is a block circuit diagram of a NOR flash memory having a storage capacity of m × n bits. The NOR type flash memory shown in FIG. 7 includes a memory cell array 701 in which a plurality of memory cells (1, 1) to (n, m) are arranged in a matrix of m × n and an X address decoder 703. , A Y address decoder 702, a Y selector 704, and a write / read circuit 705. As another peripheral circuit, a booster circuit, an address buffer circuit, or the like may be provided.
[0044]
Each memory cell (representing a memory cell (i, j) as a representative, where i is an integer of 1 or more and n or less, and j is an integer of 1 or more and m or less) is configured by an n-channel type semiconductor memory element. You. Then, the drain electrode and the control gate electrode of the semiconductor memory element are connected to the bit line BL (i) and the word line WL (j), respectively. The bit lines BL (1) to BL (n) are connected to a Y address decoder 702, and the word lines WL (1) to WL (m) are connected to an X address decoder 703. Further, the source electrodes of all the semiconductor memory elements are connected to a common source line, and the source line potential Vs is given.
[0045]
Writing and reading of data are performed in the memory cells selected by the X address decoder 703 and the Y address decoder 702. A write operation and a read operation using hot electrons will be described taking the memory cell (1, 1) as an example.
[0046]
First, when writing data to the semiconductor memory element, the source line is dropped to GND, and a positive high voltage (for example, 16 V) is applied to the bit line BL (1) and the word line WL (1). Under such conditions, a high electric field near the drain of the semiconductor storage element causes impact ionization. Furthermore, since a high electric field is also generated in the gate direction, the generated hot electrons are injected into the floating gate electrode and writing is performed. The threshold voltage of the semiconductor storage element changes according to the amount of charge stored in the floating gate electrode.
[0047]
When reading data stored in the semiconductor memory element, the source line is dropped to GND, and a predetermined voltage is applied to the word line WL (1). The predetermined voltage may be set between a threshold voltage in a state where charge is stored in the floating gate electrode of the semiconductor storage element and a threshold voltage in a state where charge is not stored. As a result, by utilizing the fact that the semiconductor memory element in which the charge is stored in the floating gate electrode is turned off and the semiconductor memory element in which the charge is not stored is turned on, the charge is stored in the memory cell (1, 1). The read data is read from the bit line BL (1).
[0048]
For example, when the threshold voltages of the two states of the semiconductor memory element are 2 V or lower and 4 V or higher, respectively, 3 V can be used as the predetermined voltage.
[0049]
Data is erased from the selected memory cells at the same time. For example, when erasing the memory cells (1, 1) to (m, 1) in the first column, the source line and the word line WL (1) are dropped to GND, and a positive high voltage is applied to the bit line BL (1). (For example, 20 V). At this time, since a high potential difference is generated between the gate and the drain of the semiconductor memory element, electrons accumulated in the floating gate electrode are emitted to the drain region by a tunnel current, and erasing is performed. As described above, when the charge is extracted from the drain region of the semiconductor storage element, it is preferable that the high-concentration impurity region on the drain side and the floating gate electrode partially overlap each other via the first gate insulating film.
[0050]
Note that the potentials of the signal lines BL (2) to BL (n) and WL (2) to WL (m) which are not selected at the time of writing, reading, and erasing may all be 0V. In addition, the value of the operating voltage described above is an example, and is not limited to the value.
[0051]
In the present embodiment, the case where binary (1 bit) information is stored in one semiconductor memory element has been described, but a multi-valued nonvolatile memory that stores three or more levels of information in one semiconductor memory element has been described. It does not matter. Further, the present invention is not limited to a NOR flash memory, and can be similarly applied to a NAND flash memory and an AND flash memory. In addition, a nonvolatile memory of a type in which a memory cell is constituted by one semiconductor storage element and one selection TFT may be used, or a split gate having the roles of the selection TFT and the semiconductor storage element. A non-volatile memory of a type that forms a memory cell with a semiconductor memory element having a structure may be used.
[0052]
(Embodiment 2)
A method for forming a crystalline semiconductor film according to the present invention will be described. 3 to 6 are used for the description. The perspective view shown in FIG. 3 shows a mode in which a first insulating film 302 and second insulating films 303 to 306 are formed over a substrate 301, and stripe-shaped concave portions are provided by the insulating film. Although three straight concave portions are shown in FIG. 3, the number is not limited to the number.
[0053]
As the substrate, a commercially available alkali-free glass substrate, a quartz substrate, a sapphire substrate, a substrate in which the surface of a single crystal or polycrystalline semiconductor substrate is covered with an insulating film, and a substrate in which the surface of a metal substrate is covered with an insulating film can be used.
[0054]
In order to form a stripe-shaped concave portion with a submicron design rule, it is necessary to make the unevenness of the substrate surface and the undulation or twist of the substrate less than the focal depth of the exposure apparatus (particularly a stepper). It is desirable that the unevenness of the substrate surface in the exposure area, the undulation or twist of the substrate be 1 μm or less, preferably 0.5 μm or less.
[0055]
The width W2 of the second insulating films 303 to 306 is 0.1 to 10 μm (preferably 0.5 to 1 μm), and the interval W1 between adjacent second insulating films is 0.01 to 2 μm (preferably 0.1 to 1 μm). And the thickness d1 of the second insulating film is 0.01 to 3 μm (preferably 0.1 to 2 μm). The stripe pattern does not need to have a regular period, and may be arranged at predetermined intervals in accordance with the width of the island-shaped semiconductor film. There is no limitation on the length of the linear concave portion, and it is sufficient that the linear concave portion has such a length that a channel region of a TFT can be formed.
[0056]
The first insulating film is formed of a material selected from silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride in which the nitrogen content is larger than the oxygen content and has a thickness of 30 to 300 nm. Further, the second insulating film in which the concave portion is formed in a predetermined shape is formed of silicon oxide or silicon oxynitride so that the thickness d1 is 10 to 3000 nm, preferably 100 to 2000 nm. Silicon oxide is composed of tetraethyl orthosilicate (TEOS) and O ₂ Can be formed by a plasma CVD (Chemical Vapor Deposition) method. Silicon oxynitride film is SiH ₄ , NH ₃ , N ₂ O or SiH ₄ , N ₂ It can be formed by a plasma CVD method using O as a raw material.
[0057]
As shown in FIG. 3, when a linear stripe pattern is formed with two layers of insulating films, it is necessary to have a selectivity between the first insulating film and the second insulating film in the etching process. Actually, it is desirable to appropriately adjust the material and the film forming conditions so that the etching rate of the second insulating film is relatively higher than that of the first insulating film. As an etching method, etching using buffered hydrofluoric acid or CHF ₃ This is performed by dry etching using. At this time, the angle of the side surface of the concave portion formed by the second insulating film may be appropriately set in the range of 5 to 120 degrees, preferably 80 to 100 degrees.
[0058]
Note that here, the unevenness of the base for forming the crystalline semiconductor film is described as an example in which the first insulating film and the second insulating film are used. However, the present invention is not limited to this embodiment and has a similar shape. If there is, it can be replaced. For example, a concave portion may be directly formed by etching the surface of a quartz substrate to form an uneven shape.
[0059]
As shown in FIG. 4, the semiconductor film 401 is formed using silicon, a compound or alloy of silicon and germanium, or a compound or alloy of silicon and carbon to a thickness of 0.01 to 3 μm (preferably 0.1 to 1 μm). Form. That is, it is desirable that the thickness d2 of the semiconductor film 401 be equal to or greater than the depth of the concave portion formed by the second insulating film. As the semiconductor film 401, an amorphous semiconductor film or a polycrystalline semiconductor film formed by a plasma CVD method, a sputtering method, a low-pressure CVD method, a polycrystalline semiconductor film formed by solid-phase growth, or the like is used. As illustrated, the semiconductor film 401 is formed so as to cover the uneven structure formed by the underlying first and second insulating films. In addition, the influence of chemical contamination such as boron adhering to the surfaces of the first insulating film and the second insulating film is eliminated, and the amorphous semiconductor film is prevented from being in direct contact with the insulating surface. It is preferable that a silicon oxynitride film is continuously formed as a third insulating film on the lower layer side without being exposed to the air in the same film forming apparatus.
[0060]
Then, the semiconductor film 401 is instantaneously melted and crystallized. In this crystallization, laser light or radiation light from a lamp light source is condensed by an optical system to an energy density at which the semiconductor film is melted and irradiated. In this step, it is particularly preferable to apply laser light using a continuous wave laser oscillation device as a light source. The applied laser light is linearly condensed by the optical system and expanded in the longitudinal direction, and its intensity distribution has a uniform region in the longitudinal direction and has a distribution in the lateral direction. It is desirable.
[0061]
As the laser oscillation device, a rectangular beam solid laser oscillation device is applied, and particularly preferably, a slab laser oscillation device is applied. As the slab material, a crystal such as Nd: YAG, Nd: GGG (gadolinium gallium garnet), or Nd: GsGG (gadolinium scandium gallium garnet) is used. In the slab laser, the laser beam travels in a zigzag optical path in this plate-shaped laser medium while repeating total reflection. Alternatively, it is a solid-state laser oscillation device using a rod doped with Nd, Tm, and Ho, and in particular, YAG, YVO ₄ , YLF, YAlO ₃ A solid-state laser oscillation device using a crystal in which Nd, Tm, and Ho are doped into a crystal such as the above may be combined with a slab structure amplifier.
[0062]
The wavelength of the continuous wave laser light is desirably 400 to 700 nm in consideration of the light absorption coefficient of the semiconductor film. Light in such a wavelength band is obtained by extracting the second harmonic and the third harmonic of the fundamental wave using a wavelength conversion element. ADP (ammonium dihydrogen phosphate), Ba ₂ NaNb ₅ O _Fifteen (Sodium barium niobate), CdSe (selenium cadmium), KDP (potassium dihydrogen phosphate), LiNbO ₃ (Lithium niobate), Se, Te, LBO, BBO, KB ₅ Etc. are applied. It is particularly desirable to use LBO. A typical example is Nd: YVO ₄ A second harmonic (532 nm) of a laser oscillation device (fundamental wave 1064 nm) is used. In addition, a single mode that is a TEM00 mode is applied to a laser oscillation mode.
[0063]
Further, strong light similar to laser light may be applied. For example, the light emitted from a halogen lamp, a xenon lamp, a high-pressure mercury lamp, a metal halide lamp, or an excimer lamp may be a light having a high energy density collected by a reflecting mirror or a lens.
[0064]
For silicon, which is chosen as the most suitable material, the absorption coefficient is 10 ³ -10 ⁴ cm ^-1 Is substantially in the visible light range. When crystallizing a substrate having a high visible light transmittance such as glass and an amorphous semiconductor film formed with silicon to have a thickness of 30 to 200 nm, irradiation with light in a visible light region having a wavelength of 400 to 700 nm is performed. By selectively heating the semiconductor film, crystallization can be performed without damaging the base insulating film. Specifically, the penetration length of light having a wavelength of 532 nm into the amorphous silicon film is approximately 100 nm to 1000 nm, and can sufficiently reach the inside of the amorphous semiconductor film formed with a thickness of 30 nm to 200 nm. . That is, heating can be performed from the inside of the semiconductor film, and substantially the entire semiconductor film in the laser light irradiation region can be uniformly heated.
[0065]
The laser beam scans in a direction parallel to the direction of the linear concave portion, and the molten semiconductor flows into the concave portion due to surface tension and solidifies. In the solidified state, the surface becomes almost flat as shown in FIG. As a result, a crystalline semiconductor film 501 having a thickness d3 larger than the thickness d4 on the second insulating film on the concave portion is formed. The crystalline semiconductor film 501 thus formed has a feature that the crystal growth edge and the crystal grain boundary are formed on the second insulating film, and the concave region does not include any crystal grain boundary other than the twin crystal. .
[0066]
After that, heat treatment is preferably performed at 500 to 600 ° C. to remove strain accumulated in the crystalline semiconductor film. This distortion is caused by volume shrinkage of the semiconductor caused by crystallization, thermal stress with the base, lattice mismatch, and the like. This heat treatment may be performed using a normal heat treatment apparatus, but may be performed, for example, for 1 to 10 minutes using a gas heating type instantaneous thermal annealing (RTA) method. Note that this step is not an essential requirement in the present invention, and may be appropriately selected and performed.
[0067]
Thereafter, as shown in FIG. 6, the surface of the crystalline semiconductor film 501 is etched to selectively extract the crystalline semiconductor films 601, 602, and 603 embedded in the concave portions. By etching and removing a region including a crystal growth edge and a crystal grain boundary formed on the second insulating film, only a high-quality semiconductor region can be left. At this time, the side surfaces of the crystalline semiconductor films 601, 602, and 603 are completely covered with the concave side walls. That is, the thickness d5 of the crystalline semiconductor films 601, 602, and 603 is set to be equal to or less than the thickness d1 of the second insulating film.
[0068]
In order to obtain such a crystalline semiconductor film, a form in which the thickness (depth of the concave portion) d1 of the second insulating film is substantially equal to or larger than the thickness d2 of the semiconductor film 401 is most suitable. . When the thickness (depth of the recess) d1 of the second insulating film is smaller than the thickness d2 of the semiconductor film 401, the surface of the crystalline semiconductor film 501 is not sufficiently flattened because the recess is shallow. Note that when the thickness (depth of the concave portion) d1 of the second insulating film is sufficiently larger than the thickness d2 of the semiconductor film 401, the crystalline semiconductor film 501 flows into the concave portion, and is over the second insulating film 203. It is also possible to make it hardly remain. When the width W2 of the concave portion is larger than 1 μm, not only a crystal grain boundary is formed on the second insulating film, but also a crystal grain boundary tends to be generated near the center of the concave portion. . It is presumed that this is because the effect of stress relaxation is reduced by increasing the interval.
[0069]
A scanning electron microscope (SEM) photograph shown in FIG. 25 shows an example, in which a 150 nm amorphous silicon film is formed on a base insulating film provided with a step of 170 nm and a width and a space of a recess of 0.5 μm. This shows the result of crystallization. The surface of the crystalline semiconductor film has a Seco solution (HF: H ₂ O = 2: 1 K as additive ₂ Cr ₂ O ₇ Etching with a chemical solution prepared using
[0070]
FIG. 28 shows a sketch of the SEM photograph shown in FIG. In FIG. 28, a hatched portion 2802 is a region where the second insulating film shown in FIG. 3 is present, and a region 2803 sandwiched between the hatched portions 2802 is a concave region. A thick line 2801 represents a crack or a grain boundary. As is clear from FIGS. 28 and 25, the crystal grain boundaries are concentrated on the second insulating film, and it is found that no remarkable grain boundaries are observed in the concave region.
[0071]
In FIGS. 28 and 25, the scanning direction of the laser beam is from the bottom to the top of the drawing. At the lower end of the shaded portion 2802, the second insulating film is exposed. This is presumably because in the crystallization step by laser light irradiation, the melted silicon film moved in the laser light scanning direction and solidified.
[0072]
FIG. 26 shows the result of determining the orientation of the crystalline semiconductor film formed in the concave portion by using a backscattered electron diffraction pattern (EBSP). The EBSP is provided with a dedicated detector in a scanning electron microscope (SEM), irradiates the crystal surface with an electron beam, and allows the computer to recognize the crystal orientation from the Kikuchi line using a computer to recognize the microscopic image. The crystallinity is measured not only in the surface orientation but also in all directions of the crystal (hereinafter, this method is referred to as EBSP method for convenience).
[0073]
The data in FIG. 26 shows that crystals grow in the concave portion in a direction parallel to the scanning direction of the laser light condensed linearly. It is confirmed that the plane orientations of the growth are substantially uniform in the same linear concave portion.
[0074]
FIG. 27 shows a cross-sectional transmission electron microscope as a result of forming and crystallizing a 150 nm amorphous silicon film on a base insulating film provided with a step of 170 nm and a width and an interval of a recess of 0.5 μm. (Transmission Electron Microscope: TEM) A photograph is shown.
[0075]
In the photograph shown in FIG. 27, a cross section of a stripe pattern exists in the vertical direction of the center of the photograph. In the cross section of the stripe pattern, a dark gray region is a second insulating film, and a crystalline silicon film is formed in a concave portion formed between the second insulating films and a thin region on the second insulating film. A black region is seen in the crystalline silicon film on the second insulating film, which indicates that the crystal grain boundaries are concentrated on the second insulating film. It can be seen that the linear boundaries seen in the crystalline silicon film formed in the recesses are twins, and that the crystalline semiconductor film in the recesses does not contain any crystal grain boundaries other than twins.
[0076]
According to the above-described method, a crystalline semiconductor film in which the recesses do not include crystal grain boundaries other than twins and whose crystal orientations are substantially uniform can be left. Then, the active layer is cut out so that the high-quality crystalline semiconductor film in the concave portion becomes a channel region in accordance with the arrangement of the semiconductor memory element, and a first gate insulating film and a floating gate electrode are formed. By forming the semiconductor memory element of the present invention through these steps, it becomes possible to realize a semiconductor memory element with small characteristic variations and high current driving capability.
[0077]
At the same time, by completely covering the side surfaces of the crystalline semiconductor film with the side walls of the concave portion, it is possible to achieve a structure without electric field concentration at the edge of the active layer at the time of injection and discharge of charges to and from the floating gate electrode, A highly reliable semiconductor memory element can be realized.
[0078]
Further, by the above-described method, the active layer is cut out so that the high-quality crystalline semiconductor film in the concave portion becomes a channel region in accordance with the arrangement of the TFT, and the gate insulating film and the gate electrode are formed. Thus, it is possible to realize a TFT having a high current driving capability. By forming a memory cell and a peripheral circuit at the same time using the above-described semiconductor memory element and TFT, a highly reliable semiconductor memory device which can operate at high speed can be realized.
[0079]
(Embodiment 3)
Next, a mode for manufacturing a semiconductor memory element and a TFT in which a crystalline silicon film is formed over a base insulating film having a concave portion and a channel formation region is provided in a filling region filled in the concave portion with reference to the drawings. Will be explained. In each of the drawings according to the present embodiment, (1) shows a top view, and (2) to (5) show longitudinal sectional views of corresponding parts.
[0080]
In this embodiment mode, a memory cell array and a peripheral circuit are manufactured at the same time. A NOR type memory cell array in which semiconductor memory elements are arranged in a matrix is shown on the right side of the drawing, and a peripheral circuit is shown on the left side. As an example, a mode of manufacturing an inverter including an n-channel TFT and a p-channel TFT will be described.
[0081]
FIG. 8 shows a mode in which a first insulating film 802 and a second insulating film 803 are formed on a glass substrate 801 and stripe-shaped concave portions are formed on an insulating surface. The embodiment shown in FIG. 8 can be manufactured by the method described in the second embodiment. In this embodiment, the first insulating film 802 is formed using aluminum oxynitride having a thickness of 30 to 300 nm. The second insulating film 803 is made of TEOS and O by plasma CVD. ₂ At a reaction pressure of 40 Pa, a substrate temperature of 400 ° C., and a high frequency (13.56 MHz) power density of 0.6 W / cm. ² To deposit a silicon oxide film to a thickness of 10 to 3000 nm, preferably 100 to 2000 nm, and then form a recess by etching. The width of the concave portion is formed at 0.01 to 2 μm, preferably 0.1 to 1 μm, particularly at a place where the channel formation region is arranged.
[0082]
Thereafter, as shown in FIG. 9, a third insulating film 901 made of an oxide film or a silicon oxynitride film and an amorphous silicon film are formed on the first insulating film 802 and the second insulating film 803 using the same plasma CVD apparatus. Is continuously formed without touching the surface. The amorphous silicon film is formed of a semiconductor film containing silicon as a main component, and is made of SiH by a plasma CVD method. ₄ Is formed as a source gas. The amorphous silicon film has an uneven surface shape reflecting the step shape of the base.
[0083]
The crystallization is performed by irradiating continuous wave laser light. FIG. 9 shows the state after the crystallization. Crystallization conditions are YVO in continuous oscillation mode. ₄ Using a laser oscillator, the output of the second harmonic (wavelength: 532 nm) of 5 to 10 W is condensed by an optical system into a linear laser beam having a ratio of the longitudinal direction to the lateral direction of 10 or more, and the longitudinal direction. Light is condensed so as to have a uniform energy density distribution, and is crystallized by scanning at a speed of 10 to 200 cm / sec. Uniform energy density distribution does not exclude anything that is completely constant, and the allowable range of energy density distribution is ± 10%.
[0084]
FIG. 21 shows the relationship between the scanning direction of the linearly focused laser light and the arrangement of the concave portions. It is desirable that the intensity distribution of the laser light 2160 condensed linearly has a region where the intensity distribution is uniform in the longitudinal direction. The purpose of this is to make the temperature of the semiconductor to be heated keep the temperature of the irradiation area constant. This is because if a temperature distribution occurs in the longitudinal direction (direction intersecting the scanning direction) of the laser light condensed linearly, the crystal growth direction cannot be limited to the scanning direction of the laser light. By aligning the linear stripe pattern with the scanning direction of the laser light 2160 condensed linearly as shown in the figure, the crystal growth direction is aligned with the channel length direction of all transistors. Can be. Thus, variation in characteristics between the elements of the transistor can be reduced.
[0085]
Further, the crystallization by the laser light condensed linearly may be completed by only one scan (that is, in one direction), or may be performed by reciprocating scan to further improve the crystallinity. Furthermore, after crystallization by laser light, the surface of the silicon film is treated with an alkali solution such as removal of oxides by hydrofluoric acid or an ammonia hydrogen peroxide solution to selectively remove poor quality parts having a high etching rate. After removal, the same crystallization treatment may be performed again. Thus, crystallinity can be improved.
[0086]
By irradiating a laser beam under these conditions, the amorphous silicon film is instantaneously melted and crystallized. The crystallization proceeds while the melting zone moves substantially. The molten silicon is aggregated and solidified in the concave portions by the surface tension. As a result, a crystalline silicon film 902 having a flat surface is formed so as to fill the concave portions as shown in FIG.
[0087]
Thereafter, as shown in FIG. 10, the surface of the crystalline silicon film 902 is removed by etching while the region serving as the source / drain region and the region serving as the wiring using the crystalline silicon film are masked with a photoresist. At this time, an etching process is performed on a region not masked with the photoresist so as to leave only the crystalline silicon film embedded in the concave portion. As a result, at least in a portion to be a channel region, the side surface of the crystalline silicon film is completely covered with the insulating film forming the concave portion. By this etching process, the unmasked region is buried in the recess, and the masked region provides a crystalline silicon film 1001 in which the recesses are connected. The crystalline silicon film can be etched with selectivity to the underlying oxide film by using a fluorine-based gas and oxygen as an etching gas. For example, as an etching gas, CF ₄ And O ₂ Is applied.
[0088]
Further, island-shaped silicon films 1101 to 1103 shown in FIG. 11 are formed from the crystalline silicon film 1001 shown in FIG. As shown in the second embodiment, the island-shaped silicon film has a feature that it does not include a crystal grain boundary other than a twin. Note that FIG. 11 does not limitly show the shapes of the island-shaped silicon films 1101 to 1103, but may be freely designed within a range according to a predetermined design rule.
[0089]
In the present embodiment, the semiconductor memory element is formed using a crystalline silicon film formed in one linear recess so as to minimize the element area, and the source line connected to the semiconductor memory element is The structure is formed using a silicon film, and an island-shaped silicon film 1103 as shown in FIG. 11 is formed. On the other hand, a TFT constituting a peripheral circuit needs to design a channel width in accordance with a required current driving capability. By using a crystalline silicon film formed in a plurality of linear concave portions as a channel region, a plurality of TFTs can be formed. The TFT has a structure in which channel regions are arranged in parallel (referred to as a multi-channel TFT), and is an island-shaped silicon film 1101 or 1102 as shown in FIG.
[0090]
Thereafter, as shown in FIG. 12, a fourth insulating film 1201 which covers the upper surfaces of the island-shaped silicon films 1101 to 1103 and is used as the gate insulating film of the TFT and the first gate insulating film of the semiconductor memory element, and the gate electrode of the TFT And a conductive film 1202, 1203 used as a floating gate electrode of the semiconductor memory element, a fifth insulating film 1204 used as a second gate insulating film of the semiconductor memory element, and a conductive film 1205 used as a control gate electrode of the semiconductor memory element are formed in this order. I do. As the fourth insulating film 1201 and the fifth insulating film 1204, a silicon oxide film or a silicon oxynitride film having a thickness of 30 to 200 nm is formed by a known gas phase method (a plasma CVD method, a sputtering method, or the like). SiO as the fifth insulating film 1204 ₂ / SiN / SiO ₂ (Called an ONO film). The conductive films 1202, 1203, and 1205 are formed using tungsten or an alloy containing tungsten, aluminum or an aluminum alloy, polycrystalline silicon, or the like.
[0091]
Note that when a quartz substrate is used as the substrate having an insulating surface, the fourth insulating film 1201 used as the first gate insulating film of the semiconductor memory element may be formed by a thermal oxidation process. For example, a heat treatment at 950 ° C. is performed in an oxidizing atmosphere to form a thermal oxide film having a thickness of 10 to 200 nm. As a result, a high-quality oxide film and a semiconductor / insulating film interface with few interface levels can be obtained, and high reliability of the first gate insulating film can be obtained. Alternatively, the first gate insulating film may be formed by forming a silicon oxide film or a silicon oxynitride film, and then performing a thermal oxidation step to form a stacked structure of a deposited film and a thermal oxide film. Also in this case, a semiconductor / insulating film interface having a small interface state is obtained, and high reliability is obtained.
[0092]
In a semiconductor memory device having a conventional structure, if thermal oxidation is performed during the formation of the first gate insulating film, thermal oxidation proceeds near the edge of the active layer even at the bottom of the active layer, and the shape of the short portion of the active layer is distorted. In addition, there is a problem that the reliability is reduced due to the concentration of the electric field. In the semiconductor memory device of the present invention, since the side surface of the semiconductor active layer is covered by the side wall of the concave portion, thermal oxidation only proceeds at the upper surface of the active layer even near the edge of the active layer. There is no problem such as thermal oxidation.
[0093]
FIG. 13 shows a step of forming one conductivity type impurity regions 1301 to 1303 in the island-shaped semiconductor films 1101 to 1103. Here, n-type impurity regions 1302 and 1303 and a p-type impurity region 1301 are provided. These impurity regions may be formed in a self-aligned manner using the conductive film 1202 used as the gate electrode of the TFT and the conductive film 1205 used as the control gate electrode of the semiconductor memory element, or may be formed using a photoresist as a mask. good. The impurity regions 1301 to 1303 form source / drain regions, and a low-concentration drain region can be provided as needed.
[0094]
For the impurity regions 1301 to 1303, an ion implantation method or an ion doping method in which impurity ions are accelerated by an electric field and implanted into a semiconductor film is applied.
[0095]
Then, as shown in FIG. 14, a sixth insulating film 1401 made of a silicon nitride film or a silicon oxynitride film is formed, and a wiring 1402 which is in contact with an impurity region forming a source / drain region is formed. After that, heat treatment at 400 to 450 ° C. releases hydrogen contained in the silicon nitride film or the silicon oxynitride film, so that the island-shaped semiconductor film can be hydrogenated.
[0096]
Thus, as shown in FIG. 14, a NOR type memory cell array including the semiconductor storage elements 1405 and an inverter circuit including the n-channel type multi-channel TFT 1403 and the p-channel type multi-channel TFT 1404 typifying the peripheral circuit are formed. can do. Of course, the present invention is not limited to this configuration, and other known memory cell arrays, other CMOS circuits, or circuits composed of unipolar TFTs can be manufactured in the same manner as in the present embodiment. Further, the number of channel formation regions arranged in parallel is not limited, and an arbitrary number may be arranged as needed.
[0097]
As described above, according to the arrangement of the semiconductor storage element and the TFT, at least in the channel region of the semiconductor storage element, the side surface of the crystalline semiconductor film is covered by the side wall of the concave portion, and the high quality without the crystal grain boundary other than the twin crystal is included. An active layer is cut out such that a crystalline semiconductor film becomes a channel region. In a semiconductor memory device, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are used. By forming a film and a gate electrode respectively, it is possible to simultaneously fabricate a semiconductor memory device with high reliability, small characteristic variation and high current drive capability, and a TFT with small characteristic variation and high current drive capability. It becomes.
[0098]
As a result, it is possible to realize a highly reliable and high-speed semiconductor memory device in which a memory cell array in which semiconductor memory elements are arranged in a matrix and a peripheral circuit formed by TFTs are formed on the same substrate. It becomes possible.
[0099]
【Example】
(Example 1)
The present invention can be applied to various semiconductor storage elements having a charge storage layer between a semiconductor active layer and a control gate electrode. In particular, the present invention can be applied to a semiconductor storage element provided with a semiconductor cluster layer, a metal cluster layer, or a nitride film as an electrification accumulation layer. These semiconductor storage elements are characterized in that regions for storing electric charges are provided spatially discretely.
[0100]
FIG. 19A shows an example of a cross-sectional view in the channel length direction of a semiconductor memory element using a semiconductor or metal cluster layer as a region for storing charge. In the semiconductor memory element shown in FIG. 19A, a semiconductor active layer including a channel region 1901 and impurity regions 1902 and 1903 to which an impurity of one conductivity type is added, a first gate insulating film 1904, A cluster layer 1906, a second gate insulating film 1907, and a control gate electrode 1908 are sequentially stacked. The cluster layer 1906 is a layer formed of discrete massive semiconductors or metals (referred to as clusters), and the discrete clusters 1905 serve as charge trap centers.
[0101]
As a semiconductor memory element using a nitride film or the like as a region for storing electric charge, MNOS (Metal Nitride Oxide Semiconductor), MONOS (Metal Oxide Nitride Oxide Semiconductor) and the like are known. FIGS. 19B and 19C show examples of cross-sectional views in the channel length direction of MNOS and MONOS type semiconductor storage elements, respectively. The semiconductor memory element shown in FIG. 19B has a semiconductor active layer including a channel region 1911 and impurity regions 1912 and 1913 to which an impurity of one conductivity type is added, a first gate insulating film 1914, A film 1915 and a control gate electrode 1916 are sequentially stacked. The semiconductor memory element shown in FIG. 19C has a semiconductor active layer including a channel region 1921 and impurity regions 1922 and 1923 to which an impurity of one conductivity type is added, and a first gate insulating film 1924 on a substrate 1920. , A nitride film 1925, a second gate insulating film 1926, and a control gate electrode 1927 are sequentially stacked. In any case, spatially discrete impurity levels in the nitride film serve as charge trapping centers.
[0102]
When the present invention is applied to the above-described semiconductor storage element, the channel region is formed in a linear concave portion having an insulating surface, the side surface is completely covered by the concave portion side wall, and includes a grain boundary other than a twin crystal. It is only necessary to use a crystalline semiconductor film in which crystal orientations are almost uniformly arranged.
[0103]
When a charge storage layer in which regions for storing charges are provided discretely is used as a semiconductor memory element, there is an effect that charge retention characteristics are less likely to be affected by defects in the first gate insulating film and pinholes. In the case where a region for accumulating electric charges is continuously provided as in a semiconductor memory element having a floating gate electrode, if there is a pinhole even in one place in the first gate insulating film, the pinhole is accumulated in the floating gate electrode. All of the accumulated charge leaks from the pinhole, which greatly affects the charge retention characteristics of the semiconductor storage element. However, in the case of using a semiconductor memory element in which regions for accumulating charges are discretely provided, the region affected by the pinhole is limited, and many charge accumulation regions are not affected by the pinhole. Therefore, the influence on the charge retention characteristics of the semiconductor memory element is small.
[0104]
(Example 2)
In the formation of the crystalline semiconductor film in the present invention, in addition to the method of irradiating the amorphous semiconductor film with laser light to crystallize it as described in Embodiment 2, the laser light is further crystallized by solid phase growth. Irradiation may be performed to melt and recrystallize.
[0105]
For example, after forming the amorphous semiconductor film 401 in FIG. 4, a catalyst that promotes crystallization, such as lowering the crystallization temperature of the amorphous semiconductor film (for example, an amorphous silicon film) to improve the orientation, or the like. Ni is added as a functioning metal element. The method for adding Ni is not limited, and a spin coating method, an evaporation method, a sputtering method, or the like can be applied. In the case of spin coating, a 5 ppm aqueous solution of nickel acetate is applied to form a metal element-containing layer. Of course, the catalyst element is not limited to Ni, and other known materials may be used.
[0106]
After that, the amorphous semiconductor film 401 is crystallized by a heat treatment at 580 ° C. for 4 hours. The crystallized semiconductor film is irradiated with a laser beam or an equivalent strong light to be melted and recrystallized. Thus, a crystalline semiconductor film 501 whose surface is almost flattened as in FIG. 5 can be obtained. Similarly, the crystalline semiconductor film 501 has a growth end and a crystal grain boundary formed on the second insulating film 304.
[0107]
The advantage of using a crystallized semiconductor film as an object to be irradiated with laser light lies in the fluctuation rate of the light absorption coefficient of the semiconductor film. Even if the crystallized semiconductor film is irradiated with laser light and melted, the light absorption coefficient is almost zero. Does not fluctuate. Therefore, the margin of the laser irradiation condition can be widened.
[0108]
Although the metal element remains in the thus formed crystalline semiconductor film, it can be removed by gettering. For details of this technique, refer to Japanese Patent Application No. 2001-019367 (or Japanese Patent Application No. 2002-020801). Further, the heat treatment accompanying the gettering treatment also has an effect of alleviating distortion of the crystalline semiconductor film.
[0109]
After that, the crystalline semiconductor film in the concave portion is extracted as in the second embodiment. The extracted crystalline semiconductor film does not include crystal grain boundaries other than twins, has a feature that the crystal orientation is almost uniformly aligned, and has at least a side surface at a portion to be a channel region of the semiconductor memory element. It is covered by the side wall of the recess. Then, a semiconductor storage element and a TFT can be manufactured using the crystalline semiconductor.
[0110]
This embodiment can be applied to the semiconductor memory device described in the first embodiment.
[0111]
(Example 3)
In this embodiment, an example of a structure of a laser processing apparatus which can be applied for crystallization will be described.
[0112]
FIG. 20 shows laser oscillators 2001a and 2001b, a shutter 2002, high conversion mirrors 2003 to 2006, cylindrical lenses 2008 and 2009, a slit 2007, a mounting table 2011, and driving means 2012 and 2013 for displacing the mounting table 2011 in the X and Y directions. A front view and a side view of a configuration of a laser processing apparatus including a control means 2014 for controlling the driving means, a laser oscillation apparatus 2001 and an information processing means 2015 for sending a signal to the control means 2014 based on a program stored in advance. This is shown in the figure.
[0113]
As the laser oscillation device, a rectangular beam solid laser oscillation device is applied, and particularly preferably, a slab laser oscillation device is applied. Or YAG, YVO ₄ , YLF, YAlO ₃ A solid-state laser oscillation device using a crystal in which Nd, Tm, and Ho are doped into a crystal such as the above may be combined with a slab structure amplifier. As the slab material, a crystal such as Nd: YAG, Nd: GGG (gadolinium gallium garnet), or Nd: GsGG (gadolinium scandium gallium garnet) is used. In addition, a gas laser oscillation device and a solid laser oscillation device capable of continuous oscillation can be applied. YAG, YVO as continuous wave solid-state laser oscillators ₄ , YLF, YAlO ₃ A laser oscillation device using a crystal in which Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm is doped into such a crystal is applied. The fundamental wave of the oscillation wavelength varies depending on the material to be doped, but oscillates at a wavelength of 1 μm to 2 μm. In order to obtain a higher output of 5 W or more, a diode-pumped solid-state laser oscillator may be cascaded.
[0114]
The circular or rectangular laser light output from such a laser oscillation device is condensed linearly in the cross-sectional shape of the irradiation surface by the cylindrical lenses 2008 and 2009. Further, in order to prevent interference on the irradiation surface, the high conversion mirror is appropriately adjusted so that the light enters from an oblique direction at an angle of 10 to 80 degrees. If the cylindrical lenses 2008 and 2009 are made of synthetic quartz, a high transmittance can be obtained, and a coating applied to the lens surface is applied to achieve a transmittance of 99% or more with respect to the wavelength of laser light. Of course, the cross-sectional shape of the irradiation surface is not limited to a linear shape, and may be an arbitrary shape such as a rectangular shape, an elliptical shape, or an oval shape. In any case, the ratio of the short axis to the long axis is in the range of 1:10 to 1: 1100. Further, the wavelength conversion element 2010 is provided to obtain a harmonic with respect to the fundamental wave.
[0115]
Further, the laser processing of the substrate 2020 can be performed by moving the mounting table 2011 in two axial directions by the driving means 2012 and 2013. In the movement in one direction, a distance longer than the length of one side of the substrate 2020 can be continuously moved at a constant speed of 1 to 200 cm / sec, preferably 5 to 50 cm / sec. It is possible to step-discontinuously move the same distance as the longitudinal direction of the shaped beam. The oscillation of the laser oscillators 2001a and 2001b and the mounting table 2011 are operated in synchronization by the information processing means 2015 equipped with a microprocessor.
[0116]
The mounting table 2011 linearly moves in the X direction shown in the drawing, thereby enabling processing of the entire surface of the substrate with laser light emitted from a fixed optical system. The position detecting means 2016 detects that the substrate 2020 is at the irradiation position of the laser beam, transmits the signal to the information processing means 2015, and uses the information processing means 2015 to determine the timing with the oscillation operation of the laser oscillation devices 2001a and 2001b. Synchronized. That is, when the substrate 2020 is not located at the position irradiated with the laser beam, the laser oscillation is stopped to extend the life.
[0117]
The laser beam applied to the substrate 2020 by the laser irradiation apparatus having such a structure can process a desired region or the entire surface of the semiconductor film by relatively moving in the X direction or the Y direction shown in the drawing.
[0118]
This embodiment can be freely combined with any of the configurations of the first and second embodiments.
[0119]
(Example 4)
In the second and third embodiments, the case where the crystalline semiconductor film is formed on the base insulating film having the stripe-shaped concave portions has been described. The present invention is not limited to a complete stripe pattern, and is characterized in that at least a crystalline semiconductor film forming a channel region of a semiconductor storage element and a TFT is formed by a linear recess. For example, as the source / drain region and the wiring region using the semiconductor film, a crystalline semiconductor film formed by an inter-strip recess connecting the linear recesses may be used. Although such a crystalline semiconductor film may contain crystal grain boundaries and crystal defects, there is no particular problem when it is used as a source / drain region or a semiconductor film wiring.
[0120]
In this embodiment, a process for manufacturing a semiconductor memory element and a TFT using a base insulating film provided with a recess between stripes for connecting between stripe-shaped recesses in accordance with a source / drain region and a wiring region using a semiconductor film. explain. As for the details of the process, only differences from the third embodiment will be described with reference to FIGS.
[0121]
FIG. 15 shows a state in which a first insulating film 1501 and a second insulating film 1502 for forming a stripe-shaped recess and a recess between stripes are formed. A region 1503 surrounded by a dotted line in the drawing is a portion serving as a source wiring in the memory cell array, and a concave portion is provided in accordance with the region serving as the source wiring. Further, regions 1504 to 1507 surrounded by dotted lines in the drawing are portions to be source / drain regions of the TFT.
[0122]
Next, an amorphous semiconductor film is deposited thereon, and a crystalline semiconductor film is formed by irradiating the amorphous semiconductor film with linearly condensed laser light. After that, the crystalline semiconductor film on the second insulating film 1502 is removed. The crystalline semiconductor film is extracted by etching and filling the recess. FIG. 16 further shows that the crystalline semiconductor film is etched in accordance with the arrangement of the semiconductor film constituting the semiconductor memory element and the TFT and the arrangement of the semiconductor film wiring to form island-shaped semiconductor films 1601, 1602, and 1603. FIG.
[0123]
Then, the first gate insulating film, the floating gate electrode, the second gate insulating film, and the control gate electrode are formed in accordance with the arrangement of the semiconductor memory element, and the gate insulating film and the gate electrode are formed in accordance with the arrangement of the TFT. Thereafter, an n-type or p-type impurity region is formed, and various wirings are formed via an interlayer insulating film, so that a memory cell array and a peripheral circuit can be manufactured at the same time as in the third embodiment.
[0124]
As described above, by providing a concave portion corresponding to the source / drain region or the wiring region using the semiconductor film in the base insulating film in advance, the wiring region using the source / drain region or the semiconductor film described in the third embodiment can be formed. A mask to cover is not required, and the number of masks required for manufacturing a semiconductor memory device can be reduced by one.
[0125]
Note that this embodiment can be freely combined with any of the configurations of Embodiments 1 to 3.
[0126]
(Example 5)
In this embodiment, another method for simultaneously manufacturing a memory cell array and a peripheral circuit will be described. The semiconductor memory element according to the present invention is characterized in that the side surface of the crystalline semiconductor film forming the channel region is covered with a concave side wall, but a peripheral circuit such as a decoder circuit for selecting a memory cell and a write / read circuit is provided. TFTs on the same substrate that constitute another semiconductor integrated circuit need not have such a structure.
[0127]
In particular, by removing the concave side walls that cover the side surfaces of the crystalline semiconductor film that forms the channel region of the TFT that forms the peripheral circuit and other semiconductor integrated circuits, not only the top surface of the crystalline semiconductor film but also the side surface portions are removed. With such a structure as a region, a TFT having high current driving capability can be realized.
[0128]
As for the details of the process, only the differences from the third embodiment will be described with reference to FIGS.
[0129]
FIG. 17 shows a state in which the region (where the right half in the figure) where the semiconductor storage element is to be arranged is masked with a photoresist and the second insulating film is removed by etching after the fabrication up to FIG. Is shown. This etching treatment is performed by chemical treatment with buffered hydrofluoric acid or CHF ₃ It can be performed by dry etching using a method.
[0130]
As a result of this step, as shown in FIG. 17, the side surface portions and the upper surface portions of the island-shaped semiconductor films 1701 and 1702 serving as the channel regions of the TFT are exposed. By forming a gate in this portion, the side surface portion and the upper surface portion of the island-shaped semiconductor films 1701 and 1702 can be used as a channel formation region.
[0131]
In this embodiment, the etching is performed up to the first insulating film. However, the etching may be stopped in the middle of the second insulating film. By adjusting the etching depth, the depth of the channel formation region of the island-shaped semiconductor films 1701 and 1702 can be adjusted. That is, the crystallization region can be selected.
[0132]
Then, as shown in FIG. 18, the first gate insulating film, the floating gate electrode, the second gate insulating film, and the control gate electrode are superimposed on the upper surface of the crystalline semiconductor film in accordance with the arrangement of the semiconductor memory element. A gate insulating film and a gate electrode are formed so as to overlap with the side surface and the upper surface of the crystalline semiconductor film in accordance with the arrangement of the TFT.
[0133]
Thereafter, an n-type or p-type impurity region is formed, and various wirings are formed via an interlayer insulating film, so that a memory cell array and a peripheral circuit can be manufactured at the same time as in the third embodiment.
[0134]
With such a configuration, in the semiconductor memory element, the side surface of the crystalline semiconductor film forming the channel region is covered with the side wall of the concave portion, and the charge and the charge at the end of the active layer are injected into and released from the floating gate electrode. High reliability can be realized by adopting a structure without electric field concentration. In a TFT constituting a peripheral circuit, a channel is formed on a side surface and an upper surface of a crystalline semiconductor film, and an effective channel width is increased. By doing so, the current driving capability can be improved.
[0135]
Note that this embodiment can be freely combined with any of the configurations of Embodiments 1 to 4.
[0136]
(Example 6)
As an example of the semiconductor memory device of the present invention, a case where a nonvolatile memory is applied to a microprocessor such as an RISC processor and an ASIC processor integrated on one chip will be described.
[0137]
FIG. 22 illustrates an example of a microprocessor. The microprocessor typically includes a CPU core 2201, a flash memory 2204, a clock controller 2203, a cache memory 2202, a cache controller 2205, an interrupt controller 2206, an I / O port 2207, and the like. Needless to say, the microprocessor shown in FIG. 22 is a simplified example, and a variety of circuit designs are performed for an actual microprocessor depending on the application.
[0138]
The microprocessor shown in FIG. 22 is manufactured by the manufacturing method described in the embodiment mode or the example, forms a crystalline silicon film on a base insulating film having a concave portion, and forms a channel forming region in a filling region filled in the concave portion. Are constituted by a semiconductor memory element and a TFT. The semiconductor memory device of the present invention is used for the flash memory 2204. As the cache memory, for example, an SRAM is used.
[0139]
As described above, by applying the present invention to a microprocessor, a semiconductor memory device having a highly reliable nonvolatile memory and capable of operating at high speed can be realized. Although the operating speed depends on design rules and the like, a read cycle of the flash memory of 500 nsec or less and an operating frequency of the CPU of 5 MHz or more are realized.
[0140]
Note that this embodiment can be combined with any of the configurations of the embodiment mode and Embodiments 1 to 5.
[0141]
(Example 7)
In this embodiment, a form of a system-on-panel in which an image display portion (typically, a liquid crystal display portion or an EL display portion), a nonvolatile memory, and another semiconductor integrated circuit are integrally formed on a substrate having an insulating surface. An example of a semiconductor memory device that employs the following will be described with reference to FIG.
[0142]
In FIG. 23, a semiconductor memory device includes a pixel region 2300, a scan line driver circuit 2301, a signal line driver circuit 2302, a VRAM 2303, a flash memory 2304, a CPU 2305, an image processing circuit 2306, a work memory 2307, and an interface circuit 2308. And is integrally formed on a substrate 2310 having the same.
[0143]
The semiconductor memory device illustrated in FIG. 23 is a device that captures or produces image data, processes the image data, converts the format, and displays an image. As the semiconductor storage device, for example, a video camera, a car navigation, a personal computer, a game machine, and the like can be considered.
[0144]
The semiconductor memory device receives data serving as a basis of image data from an input terminal according to each mode. For example, in a broadcast receiver, it is input data from an antenna, and in a video camera, it is input data from a CCD. It may be input data from a DV tape or a memory card. In addition, an input signal from a keyboard or another control signal may be input from the input terminal. Data serving as the basis of the input image is stored in the flash memory 2304 via the interface circuit 2308 and the system bus, temporarily stored in the work memory 2307, or converted into an image signal by the image processing circuit 2306. It is converted and stored in VRAM. The image processing circuit 2306 performs decoding of image data that has been compression-encoded according to the MPEG standard or tape format, and image signal processing such as image interpolation and resizing. The input control signal is used for communication with the CPU and the image processing circuit, and is also input to a signal line driving circuit and a scanning line driving circuit.
[0145]
The CPU 2305 controls the flash memory 2304, the work memory 2307, the interface circuit 2308, and other circuits. In addition, it creates or processes data that is the basis of image data. The flash memory 2304 is used as a memory area for storing color data and character data required when creating or processing image data, or as a memory area for storing program data. The work memory 2307 is used as a memory area for storing image data and its underlying data, a work memory area for control by the CPU, and the like, and a DRAM or an SRAM is used.
[0146]
An image display portion including the signal line driver circuit 2302, the scan line driver circuit 2301, and the pixel region 2300 is a region for displaying an image. A control signal is externally input to the signal line driver circuit 2302 and the scanning line driver circuit 2301 via an interface circuit, and the signal line driver circuit 2302 outputs an image output from the image processing circuit 2306 and stored in the VRAM according to the control signal. Captures data and displays an image in the pixel area.
[0147]
As described above, a semiconductor memory device having a non-volatile memory that captures or produces image data and displays an image is configured. The semiconductor memory device shown in FIG. 23 is manufactured by the manufacturing method shown in the embodiment or the example, a crystalline silicon film is formed on a base insulating film having a concave portion, and a channel is formed in a filling region filling the concave portion. The region is constituted by a semiconductor memory element and a TFT provided therein. The semiconductor memory device of the present invention is used for the flash memory 2304.
[0148]
By applying the present invention to a semiconductor memory device as described above, a semiconductor memory device having a highly reliable nonvolatile memory and capable of operating at high speed can be realized. Note that the integrated formation has an effect of miniaturization and reduction of power consumption.
[0149]
Note that the image display portion including the signal line driver circuit 2302, the scan line driver circuit 2301, and the pixel region 2300, and the image processing portion including other circuits may be manufactured over different substrates. As a semiconductor storage device, a form such as a broadcast receiver or a game machine without a display unit can be constituted by a substrate constituting an image processing unit. Of course, the semiconductor memory device described above may be realized by mounting a plurality of substrates.
[0150]
This embodiment can be used in combination with Embodiments 1 to 5.
[0151]
(Example 8)
Various devices can be completed using the present invention. Examples include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a digital camera, a personal computer, a television receiver, a projection display device, and the like. One example of them is shown in FIG.
[0152]
FIG. 24A is an example in which a television receiver is completed by applying the present invention, and includes a housing 2401, a support 2402, a display portion 2403, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a television receiver having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0153]
FIG. 24B is an example in which a video camera is completed by applying the present invention, and includes a main body 2411, a display portion 2412, an audio input portion 2413, an operation switch 2414, a battery 2415, an image receiving portion 2416, and the like. . By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a video camera having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0154]
FIG. 24C illustrates an example in which a notebook personal computer is completed by applying the present invention, which includes a main body 2421, a housing 2422, a display portion 2423, a keyboard 2424, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a personal computer having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0155]
FIG. 24D shows an example in which a PDA (Personal Digital Assistant) is completed by applying the present invention, and includes a main body 2431, a stylus 2432, a display portion 2433, operation buttons 2434, an external interface 2435, and the like. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a PDA having a nonvolatile memory with high reliability and a high operation speed can be completed.
[0156]
FIG. 24E shows an example in which a sound reproducing device is completed by applying the present invention. Specifically, FIG. 24E shows an in-vehicle audio device which includes a main body 2441, a display portion 2442, operation switches 2443 and 2444, and the like. Have been. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, an audio device having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0157]
FIG. 24F illustrates an example of a completed digital camera to which the present invention is applied. A main body 2451, a display portion (A) 2452, an eyepiece portion 2453, an operation switch 2454, a display portion (B) 2455, and a battery 2456 are shown. Etc. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a digital camera having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0158]
FIG. 24G illustrates an example in which a mobile phone is completed by applying the present invention, which includes a main body 2461, an audio output portion 2462, an audio input portion 2463, a display portion 2464, operation switches 2465, an antenna 2466, and the like. I have. By using a semiconductor memory element manufactured over a glass substrate according to the present invention, a mobile phone having a highly reliable nonvolatile memory and a high operation speed can be completed.
[0159]
It should be noted that the device shown here is merely an example, and the present invention is not limited to these applications.
[0160]
This embodiment can be used in combination with Embodiments 1 to 5.
[0161]
【The invention's effect】
According to the present invention, it is possible to manufacture a crystalline semiconductor film in which a side surface is covered with a concave side wall in a portion where a channel region of a semiconductor memory element is formed.
[0162]
As a result, local degradation of the first gate insulating film due to the electric field concentration at the edge of the semiconductor active layer can be suppressed, and a highly reliable semiconductor memory element can be realized.
[0163]
According to the present invention, at the same time, strain or stress due to crystallization can be concentrated in a region other than the concave portion, and a high-quality crystalline semiconductor film containing no crystal grain boundary other than twin in the concave portion can be manufactured. Become.
[0164]
In this manner, by controlling the crystallinity of the channel region and increasing the crystallinity of the channel region, a semiconductor memory element and a TFT with high field-effect mobility and small variation in characteristics can be manufactured.
[0165]
By forming a memory cell and a peripheral circuit at the same time using the above-described semiconductor memory element and TFT, a highly reliable semiconductor memory device which can operate at high speed can be realized.
[Brief description of the drawings]
FIG. 1 is a top view and a cross-sectional view of a semiconductor storage element of the present invention.
FIG. 2 is a top view and a cross-sectional view of a conventional semiconductor memory element.
FIG. 3 is a perspective view illustrating a crystallization method of the present invention.
FIG. 4 is a perspective view illustrating a crystallization method of the present invention.
FIG. 5 is a perspective view illustrating a crystallization method according to the present invention.
FIG. 6 is a perspective view illustrating a crystallization method of the present invention.
FIG. 7 is a block circuit diagram of a NOR nonvolatile memory.
8A to 8C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
9A to 9C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
10A to 10C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
11A to 11C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
12A to 12C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
13A to 13C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
14A to 14C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
15A to 15C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
16A to 16C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
17A to 17C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
18A to 18C are a top view and cross-sectional views illustrating a manufacturing process of a semiconductor memory device of the present invention.
FIG. 19 is a sectional view of a semiconductor memory element to which the present invention is applied;
FIG. 20 is a layout view showing one embodiment of a laser irradiation apparatus applied to the present invention.
FIG. 21 is a view for explaining laser light condensed linearly in the present invention and its scanning direction.
FIG. 22 illustrates an example of a microprocessor.
FIG. 23 illustrates an example of a semiconductor memory device.
FIG. 24 illustrates an example of a semiconductor memory device.
FIG. 25 is a scanning electron microscope (SEM) photograph (after Secoetch) showing a surface state when an amorphous silicon film of 150 nm is formed and crystallized on a base insulating film provided with a stripe-shaped concave portion.
FIG. 26 is EBSP mapping data showing the orientation of a crystal formed in a concave portion.
FIG. 27 is a cross-sectional transmission electron microscope (TEM) photograph of a crystal formed in a concave portion.
FIG. 28 is a sketch of the scanning electron microscope (SEM) photograph shown in FIG. 25.

Claims (10)

A semiconductor memory element formed on a substrate having an insulating surface,
The insulating surface has a linear recess,
The semiconductor memory device includes a semiconductor active layer including a channel region and an impurity region doped with an impurity of one conductivity type, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. ,
The semiconductor memory, wherein the channel region is formed in the linear recess, a side surface is covered by a sidewall of the linear recess, and the channel region is formed of a crystalline semiconductor film that does not include a crystal grain boundary other than a twin. element. 2. The semiconductor memory element according to claim 1, wherein the crystalline semiconductor film forming the channel region has a channel width direction of 0.01 μm or more and 2 μm or less, and a thickness of 0.01 μm or more and 3 μm or less. A semiconductor memory device having a memory cell array in which semiconductor memory elements formed on a substrate having an insulating surface are arranged in a matrix,
The insulating surface has a stripe-shaped recess,
The semiconductor memory device includes a semiconductor active layer including a channel region and an impurity region doped with an impurity of one conductivity type, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. ,
The semiconductor memory is characterized in that the channel region is formed in the stripe-shaped recess, a side surface is covered by a sidewall of the stripe-shaped recess, and is formed of a crystalline semiconductor film that does not include a grain boundary other than a twin. apparatus. A semiconductor memory device having a memory cell array in which semiconductor memory elements formed on a substrate having an insulating surface are arranged in a matrix,
The insulating surface has a stripe-shaped concave portion, and an inter-striped concave portion connecting between the stripe-shaped concave portions,
The semiconductor memory device includes a semiconductor active layer including a channel region and an impurity region doped with an impurity of one conductivity type, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. ,
The channel region is formed in the stripe-shaped concave portion, a side surface is covered by a side wall of the stripe-shaped concave portion, and is formed of a crystalline semiconductor film that does not include a crystal grain boundary other than a twin.
The semiconductor memory device according to claim 1, wherein the connection between the semiconductor storage elements by the crystalline semiconductor film is made by the crystalline semiconductor film formed in the recess between the stripes. A semiconductor memory device having a memory cell array in which semiconductor memory elements formed on a substrate having an insulating surface are arranged in a matrix,
The insulating surface has a stripe-shaped recess,
The semiconductor memory device includes a semiconductor active layer including a channel region and an impurity region doped with an impurity of one conductivity type, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. ,
The channel region is formed in the stripe-shaped recess, a side surface is covered by a side wall of the stripe-shaped recess, and is formed of a crystalline semiconductor film that does not include a crystal grain boundary other than twin crystal,
The semiconductor memory device according to claim 1, wherein the connection between the semiconductor memory elements by the crystalline semiconductor film is performed over an insulating surface between the stripe-shaped concave portions. 6. The crystalline semiconductor film forming the channel region according to any one of claims 3 to 5, wherein a channel width direction is 0.01 μm or more and 2 μm or less, and a thickness is 0.01 μm or more and 3 μm or less. A semiconductor memory device characterized by the above-mentioned. In any one of claims 3 to 6,
The semiconductor storage device is configured by a thin film transistor formed over a substrate having the insulating surface, and includes a decoder circuit, a read circuit, or a write circuit for driving the memory cell array,
A semiconductor memory device, wherein a channel region of the thin film transistor is formed of a crystalline semiconductor film formed in the stripe-shaped concave portion and containing no crystal grain boundary other than twin. In claim 7,
The semiconductor storage device includes a CPU core, an image processing circuit, an SRAM, or a DRAM including a thin film transistor formed over a substrate having the insulating surface,
A semiconductor memory device, wherein a channel region of the thin film transistor is formed of a crystalline semiconductor film formed in the stripe-shaped recess and not including a crystal grain boundary other than a twin. In claim 7,
The semiconductor storage device has an image display unit including a thin film transistor formed over a substrate having the insulating surface,
A semiconductor memory device, wherein a channel region of the thin film transistor is formed of a crystalline semiconductor film formed in the stripe-shaped recess and not including a crystal grain boundary other than a twin. The semiconductor storage device according to any one of claims 3 to 9, wherein the semiconductor storage device is selected from a game machine, a video camera, a head-mounted display, a DVD player, a personal computer, a mobile phone, and a car audio. A semiconductor memory device.

Images