JP2004006516A - Inductor element and multi-layer substrate incorporating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inductor element whose fine adjustment of inductance can be performed readily and accurately and further to provide a multi-layer substrate incorporating the same. <P>SOLUTION: The inductor element is provided with linear adjustment regions 91a, 91b, 91c, 91d, 91e, 91f, 91g and 91h between adjacent spiral coils 81b and then the fine adjustment of the inductance is performed by cutting these linear regions with laser machining or the like. The inductance of each spiral coil is set slightly lower than the preset value when the adjustment regions are provided, so that the desired value of the inductance can be obtained while the adjustment regions are cut. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inductor element having adjustable inductance and a multilayer circuit board having the inductor element incorporated therein.
[0002]
[Prior art]
A conventional inductor element and a multilayer circuit board having the inductor element built therein will be described.
The term “multilayer circuit board” as used herein generally refers to a printed wiring board and an interposer board. The interposer board mediates between an IC chip or a semiconductor element and the printed wiring board, and includes a BGA board, an MCM board, An SCM substrate or the like is included.
Conventionally, when forming a coil by drawing a pattern on a multilayer circuit board or in a multilayer circuit slope, a wiring coil layer is divided into two or more layers, and a wiring coil of each layer is connected by via connection to form a solenoid coil. There is a method and a method of forming a spiral in a single layer on the wiring coil layer to form a spiral wound print solenoid coil.
[0003]
Regarding the spiral wound print solenoid coil, a method of finely adjusting the inductance by short-circuiting between adjacent wiring coils of the spiral wound coil is disclosed in U.S. Pat. S. Nothing is described in Patent No. 5,461,353, but a method of finely adjusting the inductance of the spirally wound print solenoid coil.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an inductor element capable of easily and precisely adjusting an inductance and a multilayer circuit board having the inductor element incorporated therein.
[0005]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, first, in claim 1, an inductor element having a spiral wound coil, wherein an adjusting area for adjusting inductance is provided between wiring coils adjacent to the spiral wound coil. In addition, the inductance element can be finely adjusted by processing the adjustment region.
[0006]
According to a second aspect of the present invention, there is provided a multilayer circuit board including at least the inductor element according to the first aspect.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
In the inductor element according to the first aspect of the present invention, an adjustment area for adjusting inductance is provided between adjacent wiring coils of the spiral coil of the inductor element, and fine adjustment of inductance can be performed by processing the adjustment area. It was done.
FIGS. 1A to 1C show an embodiment of the spiral wound coil of the inductor element according to the present invention.
2A to 2C show another embodiment of the spiral wound coil of the inductor element according to the first aspect of the present invention.
As shown in FIGS. 1A to 1C, the inductor element according to the first aspect of the present invention has a linear or planar adjustment region provided between adjacent wiring coils of a spiral coil. Fine adjustment of the inductance is performed by processing the linear or planar adjustment region by laser processing or the like.
The inductance of the spiral coil is set to be slightly lower than the set value at the stage where the adjustment region is provided, and a desired inductance can be obtained at the stage of cutting the adjustment region.
The shape of the spiral coil is generally circular, but is not particularly limited as long as it is a multiple winding type such as a square or a triangle.
[0008]
As shown in FIG. 1A, the specific shape of the spiral wound coil is such that linear adjustment regions 91a, 91b, and 91c are formed between adjacent wiring coils 81b on the outermost periphery of the spiral wound coil, and one of the outermost circumferential portions is formed. The spiral-shaped coil 10a is formed by providing a linear adjustment region 91h between adjacent wiring coils 81b on the inner side, and as shown in FIG. 1B, the outermost adjacent wiring of the spiral-wound coil is formed. The spiral coil 10b is formed by providing linear adjustment regions 91a, 91b, 91c, 91d, and 91e between the coils 81b. As shown in FIG. 1C, the spiral coil 10b is adjacent to the outermost periphery of the spiral coil. The spiral-shaped coil 10c is formed by providing linear adjustment regions 91a, 91b, 91c, 91d, 91e, 91f and 91g between the wiring coils 81b. a, 91b, 91c, 91d, 91e, 91f, by cutting by laser machining or the like 91g and 91h, is obtained so as to obtain a desired inductance. The spiral wound coil 10a shown in FIG. 1A has a larger inductance adjustment width than the spiral wound coils 10b and 10c shown in FIGS. 1B and 1C.
The linear adjustment region can be arranged at any place of the spiral coil, and is appropriately arranged according to the inductance value, the adjustment width, and the like.
[0009]
As shown in FIG. 2A, another specific shape of the spiral wound coil is, as shown in FIG. 2A, a planar adjustment region 92a between adjacent wiring coils 81b on the outermost periphery of the spiral wound coil, and one inside of the outermost periphery. The spiral coil 10d is formed by providing a planar adjustment region 92d between adjacent wiring coils 11 of FIG. 2, and as shown in FIG. 2B, the outermost adjacent wiring coil 81b of the spiral coil is formed. The spiral-shaped coil 10e is formed by providing a planar adjustment region 92b between them, and as shown in FIG. 2C, the planar-shaped adjustment region is provided between adjacent wiring coils 81b on the outermost periphery of the spiral coil. A spiral coil 10f is formed by providing a coil 92f, and a desired inductance can be obtained by processing the planar adjustment regions 91a, 91b, 91c and 91d by laser processing or the like. It has become. The spiral coil 10d shown in FIG. 2A has a larger inductance adjustment width than the spiral coils 10e and 10f shown in FIGS. 2B and 2C.
Since the planar adjustment region is formed by processing the planar region by laser processing or the like, finer inductance adjustment can be performed as compared to cutting the linear adjustment region.
Further, this planar adjustment region can be arranged at any place of the spiral coil, and is appropriately arranged according to the inductance value, the adjustment width and the like.
[0010]
One embodiment of the multilayer circuit board according to claim 2 is shown in FIG.
As shown in FIG. 3, the multilayer circuit board according to the second aspect of the present invention has a first wiring layer 21a, a first wiring layer 21b, a second wiring layer 41c, and a second wiring layer 41d on both surfaces of an insulating base material 11. The capacitor element 60 and the inductor element 80 are formed on the uppermost layer of a six-layer multilayer circuit board on which the third wiring layer 84c and the third wiring layer 82d are formed. In the example of the multilayer circuit board, since the inductor element 80 is formed in the uppermost layer, the inductance can be adjusted when the inductor element 80 is manufactured, but can be adjusted after the multilayer circuit board is manufactured.
[0011]
Hereinafter, a method for manufacturing a multilayer circuit board of the present invention according to claim 2 will be described.
4A to 4E, 5F to 5I, and 6J show an example of a method for manufacturing the multilayer circuit board.
First, a first wiring layer 21a and a first wiring layer 21b are formed on both surfaces of an insulating base material 11 in which nonwoven glass is impregnated with an epoxy resin by a known photoetching process (see FIG. 4A).
Next, a resin film or the like is attached on the insulating base material 11, the first wiring layer 21a, and the first wiring layer 21b to form the insulating layer 31 (see FIG. 4B).
Next, via holes 32 are formed at predetermined positions of the insulating layer 31 by laser processing or the like (see FIG. 4C).
[0012]
Next, a thin-film conductor layer (not particularly shown) is formed on the insulating layer 31 and in the via hole 32 by electroless copper plating or the like, electrolytic copper plating is performed using the thin-film conductor layer as a cathode, and a predetermined thickness is formed. The conductor layer 41 and the filled via 42 are formed (see FIG. 4D).
Next, the conductor layer 41 is patterned to form the capacitor lower electrode 41a, the second wiring layer 41b, and the second wiring layer 41c (see FIG. 4E).
[0013]
Next, an insulating layer 51 is formed on the capacitor lower electrode 41a, the second wiring layer 41b, and the second wiring layer 41c by applying a resin solution or attaching an insulating film (FIG. 5 (f) )reference).
[0014]
Next, a predetermined position of the insulating layer 51 is drilled by laser processing or the like, so that an opening 52 is formed in the insulating layer 51 on the capacitor lower electrode 41a and on the second wiring layer 41c and the second wiring layer 41d. A step of forming a via hole 53 in the insulating layer 51 (see FIG. 5G).
[0015]
Next, a resin solution mixed with a dielectric material is embedded in the opening 52 by screen printing or a dispenser or the like, and is dried, cured, and planarized to form a dielectric layer 61 (see FIG. 5H).
[0016]
Next, a thin film conductor layer (not particularly shown) is formed by electroless copper plating on the dielectric layer 61, the insulation layer 51, and in the via hole 54, and a photosensitive layer is formed on the thin film conductor layer. A series of patterning processes such as exposure and development are performed to form a resist pattern 54. Further, electrolytic copper plating is performed using the thin film conductor layer as a cathode to form a conductor layer 81 and a filled via 82 having a predetermined thickness on the thin film conductor layer (see FIG. 5 (i)).
[0017]
Next, the resist pattern 54 is stripped with a dedicated stripper, and the thin film conductor layer under the resist pattern is soft-etched with an aqueous solution of ammonium persulfate to form a capacitor upper electrode 81a. A linear or planar adjustment region is formed between adjacent wiring coils 81b on the outermost periphery of the coil, and the linear or planar adjustment region is cut by laser processing or the like to perform inductance adjustment, thereby forming the inductor element 80. Then, a third wiring layer 81c and a third wiring layer 81d are respectively formed to obtain a six-layer multilayer circuit board 100 on which the capacitor element 60 and the inductor element 80 are formed (see FIG. 6 (j)).
Here, the center of the spiral coil of the inductor element 80 is connected to the second wiring layer 41b via the filled via 82.
[0018]
【Example】
Hereinafter, the present invention will be described in detail with reference to examples.
First, using a copper-clad laminate in which 18 μm copper foil is bonded to both sides of an insulating base material 11 in which non-woven glass is impregnated with an epoxy resin, patterning is performed to form first wiring layers 21 a and 21 b, To form an insulating layer 31 having a thickness of 40 μm, and a via hole 32 was formed at a predetermined position of the insulating layer 31 by laser processing (see FIGS. 4A to 4C).
[0019]
Next, a thin film conductor layer is formed on the insulating layer 31 and in the via hole 32 by electroless copper plating, and electrolytic copper plating is performed using the thin film conductor layer as a cathode to form a 15 μm thick conductor layer 41 and a filled via 42. Then, the conductor layer 41 was patterned to form a capacitor lower electrode 41a, a second wiring layer 41b, and a second wiring layer 41c (see FIGS. 4D to 4E).
[0020]
Next, a 40 μm thick insulating layer 51 was formed by bonding a low dielectric constant epoxy-based film on the capacitor lower electrode 41a, the second wiring layer 41b, and the second wiring layer 41c (see FIG. 5F).
[0021]
Next, a predetermined position of the insulating layer 51 is drilled by laser processing so that an opening 52 is formed in the insulating layer 51 on the capacitor lower electrode 41a and the insulating layer 51 on the second wiring layer 41c and the second wiring layer 41d. Via holes 53 were formed in the layer 51 (see FIG. 5G).
[0022]
Next, a resin paste in which barium titanate powder was highly filled with an epoxy resin was embedded in the opening 52 with a dispenser, dried and cured, and the surface was polished to form a dielectric layer 61 having a thickness of 40 μm (FIG. 5 (h)). )reference).
[0023]
A thin film conductor layer is formed by electroless copper plating on the dielectric layer 61, the insulation layer 51 and the via hole 53, a photosensitive layer is formed on the thin film conductor layer, and a series of patterning processes such as exposure and development are performed. Was performed to form a resist pattern 54. Further, electrolytic copper plating was performed using the thin film conductor layer as a cathode to form a conductor layer 81 and a filled via 82 having a thickness of 20 μm (see FIG. 5 (i)).
Here, in forming the spiral coil of the inductor element, the spiral coil 10a of FIG.
[0024]
Next, the resist pattern 54 is stripped with a dedicated stripper, and the thin film conductor layer under the resist pattern is soft-etched with an aqueous solution of ammonium persulfate to form a capacitor upper electrode 81a. Linear adjustment regions 91a, 91b, 91c, and 91h are formed between adjacent wiring coils 181b on the outermost periphery of the coil, and the linear adjustment regions 91a, 91b, 91c, and 91h are cut by a UV-YAG laser. Inductance adjustment is performed to form the inductor element 80, the third wiring layer 81c and the third wiring layer 81d, respectively, and the three wiring layers, the capacitor element 60, and the inductor element 80 are formed on both surfaces of the insulating base material 11. A multilayer circuit board 100 was obtained (see FIG. 6 (j)).
[0025]
【The invention's effect】
In the inductor element of the present invention, since the adjustment region for adjusting the inductance is provided between the wiring coils adjacent to the spiral coil, fine adjustment of the inductance can be accurately performed by processing the adjustment region.
Since the multilayer circuit board incorporating the inductor element of the present invention can perform the fine adjustment of the inductance of the inductor element even in the state of the multilayer circuit board, it is possible to have a degree of freedom in designing the multilayer circuit board.
[Brief description of the drawings]
1 (a) to 1 (c) are schematic plan views showing one embodiment of a spiral coil of an inductor element according to the first aspect of the present invention.
FIGS. 2A to 2C are schematic plan views showing another embodiment of the spiral wound coil of the inductor element according to the first aspect of the present invention.
FIG. 3 is a schematic partial configuration sectional view showing one embodiment of the multilayer circuit board of the present invention according to claim 2;
4 (a) to 4 (e) are schematic partial sectional views showing a part of the steps in the method for manufacturing a multilayer circuit board according to the second aspect of the present invention.
5 (f) to 5 (i) are schematic partial sectional views showing a part of the steps in the method for manufacturing a multilayer circuit board according to the second aspect of the present invention.
FIG. 6 (j) is a schematic partial sectional view showing a part of the steps in the method for manufacturing a multilayer circuit board according to the second aspect of the present invention.
[Explanation of symbols]
10a, 10b, 10c, 10d, 10e, 10f ... spiral coil 11 ... insulating bases 21a, 21b ... first wiring layers 31, 51 ... insulating layers 32, 53 ... via holes 41, 81 ... ... Conductor layer 41a... Capacitor lower electrodes 41b and 41c... Second wiring layers 42 and 82... Filled via 52... Opening 54... Resist pattern 60... Capacitor element 61. Element 81a Capacitor upper electrode 81b Wiring coils 81c, 81d Third wiring layers 91a, 91b, 91c, 91d, 91e, 91f, 91g, 91h ... Linear adjustment regions 92a, 92b, 92c, 92d: planar adjustment area 100: multilayer circuit board

Claims (2)

An inductor element having a spiral wound coil, wherein an adjustment region for inductance adjustment is provided between wiring coils adjacent to the spiral coil, and fine adjustment of inductance can be performed by processing the adjustment region. Characteristic inductor element. A multilayer circuit board comprising at least the inductor element according to claim 1.

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