JP2003519833A5 - - Google Patents

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Publication number
JP2003519833A5
JP2003519833A5 JP2001550546A JP2001550546A JP2003519833A5 JP 2003519833 A5 JP2003519833 A5 JP 2003519833A5 JP 2001550546 A JP2001550546 A JP 2001550546A JP 2001550546 A JP2001550546 A JP 2001550546A JP 2003519833 A5 JP2003519833 A5 JP 2003519833A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001550546A
Other languages
Japanese (ja)
Other versions
JP2003519833A (ja
Filing date
Publication date
Priority claimed from US09/476,322 external-priority patent/US6564315B1/en
Priority claimed from US09/476,578 external-priority patent/US6542984B1/en
Priority claimed from US09/476,204 external-priority patent/US6622235B1/en
Application filed filed Critical
Priority claimed from PCT/US2000/022458 external-priority patent/WO2001050253A1/en
Publication of JP2003519833A publication Critical patent/JP2003519833A/ja
Publication of JP2003519833A5 publication Critical patent/JP2003519833A5/ja
Pending legal-status Critical Current

Links

JP2001550546A 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ Pending JP2003519833A (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US47657000A 2000-01-03 2000-01-03
US09/476,322 2000-01-03
US09/476,322 US6564315B1 (en) 2000-01-03 2000-01-03 Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
US09/476,204 2000-01-03
US09/476,570 2000-01-03
US09/476,578 US6542984B1 (en) 2000-01-03 2000-01-03 Scheduler capable of issuing and reissuing dependency chains
US09/476,204 US6622235B1 (en) 2000-01-03 2000-01-03 Scheduler which retries load/store hit situations
US09/476,578 2000-01-03
PCT/US2000/022458 WO2001050253A1 (en) 2000-01-03 2000-08-16 Scheduler capable of issuing and reissuing dependency chains

Publications (2)

Publication Number Publication Date
JP2003519833A JP2003519833A (ja) 2003-06-24
JP2003519833A5 true JP2003519833A5 (enExample) 2007-09-06

Family

ID=27504212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001550546A Pending JP2003519833A (ja) 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ

Country Status (6)

Country Link
EP (1) EP1244962B1 (enExample)
JP (1) JP2003519833A (enExample)
KR (1) KR100747128B1 (enExample)
CN (1) CN1210649C (enExample)
DE (1) DE60005860T2 (enExample)
WO (1) WO2001050253A1 (enExample)

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US7243200B2 (en) * 2004-07-15 2007-07-10 International Business Machines Corporation Establishing command order in an out of order DMA command queue
CN103646009B (zh) 2006-04-12 2016-08-17 索夫特机械公司 对载明并行和依赖运算的指令矩阵进行处理的装置和方法
EP2527972A3 (en) 2006-11-14 2014-08-06 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
EP3156896B1 (en) 2010-09-17 2020-04-08 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
TWI518504B (zh) 2011-03-25 2016-01-21 軟體機器公司 使用可分割引擎實體化的虛擬核心以支援程式碼區塊執行的暫存器檔案節段
KR101636602B1 (ko) 2011-03-25 2016-07-05 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
EP2689327B1 (en) 2011-03-25 2021-07-28 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
US9940134B2 (en) 2011-05-20 2018-04-10 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
KR101639854B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 상호접속 구조
WO2013077875A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. An accelerated code optimizer for a multiengine microprocessor
CN108427574B (zh) 2011-11-22 2022-06-07 英特尔公司 微处理器加速的代码优化器
US9400653B2 (en) * 2013-03-14 2016-07-26 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
EP2972794A4 (en) * 2013-03-15 2017-05-03 Soft Machines, Inc. A method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
JP7428689B2 (ja) 2021-12-17 2024-02-06 華邦電子股▲ふん▼有限公司 メモリシステム

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US5546554A (en) * 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5651124A (en) 1995-02-14 1997-07-22 Hal Computer Systems, Inc. Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
JP2002513486A (ja) * 1997-01-29 2002-05-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド スーパースカラマイクロプロセッサ用ライン指向型リオーダバッファ
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies
US6098166A (en) * 1998-04-10 2000-08-01 Compaq Computer Corporation Speculative issue of instructions under a load miss shadow
KR100611341B1 (ko) * 1998-08-24 2006-08-14 어드밴스드 마이크로 디바이시즈, 인코포레이티드 저장 어드레스 생성에 대한 적재 블록을 위한 메커니즘

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