JP2003519833A - 依存性連鎖の発行および再発行が可能なスケジューラ - Google Patents

依存性連鎖の発行および再発行が可能なスケジューラ

Info

Publication number
JP2003519833A
JP2003519833A JP2001550546A JP2001550546A JP2003519833A JP 2003519833 A JP2003519833 A JP 2003519833A JP 2001550546 A JP2001550546 A JP 2001550546A JP 2001550546 A JP2001550546 A JP 2001550546A JP 2003519833 A JP2003519833 A JP 2003519833A
Authority
JP
Japan
Prior art keywords
instruction
instruction operation
store
scheduler
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001550546A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003519833A5 (enExample
Inventor
ケラー,ジェイムズ・ビィ
ハダッド,ラムゼイ・ダブリュ
マイアー,ステファン・ジィ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/476,204 external-priority patent/US6622235B1/en
Priority claimed from US09/476,578 external-priority patent/US6542984B1/en
Priority claimed from US09/476,322 external-priority patent/US6564315B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003519833A publication Critical patent/JP2003519833A/ja
Publication of JP2003519833A5 publication Critical patent/JP2003519833A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858Result writeback, i.e. updating the architectural state or memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2001550546A 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ Pending JP2003519833A (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US47657000A 2000-01-03 2000-01-03
US09/476,204 US6622235B1 (en) 2000-01-03 2000-01-03 Scheduler which retries load/store hit situations
US09/476,578 2000-01-03
US09/476,578 US6542984B1 (en) 2000-01-03 2000-01-03 Scheduler capable of issuing and reissuing dependency chains
US09/476,204 2000-01-03
US09/476,570 2000-01-03
US09/476,322 US6564315B1 (en) 2000-01-03 2000-01-03 Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
US09/476,322 2000-01-03
PCT/US2000/022458 WO2001050253A1 (en) 2000-01-03 2000-08-16 Scheduler capable of issuing and reissuing dependency chains

Publications (2)

Publication Number Publication Date
JP2003519833A true JP2003519833A (ja) 2003-06-24
JP2003519833A5 JP2003519833A5 (enExample) 2007-09-06

Family

ID=27504212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001550546A Pending JP2003519833A (ja) 2000-01-03 2000-08-16 依存性連鎖の発行および再発行が可能なスケジューラ

Country Status (6)

Country Link
EP (1) EP1244962B1 (enExample)
JP (1) JP2003519833A (enExample)
KR (1) KR100747128B1 (enExample)
CN (1) CN1210649C (enExample)
DE (1) DE60005860T2 (enExample)
WO (1) WO2001050253A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007529833A (ja) * 2004-07-15 2007-10-25 株式会社ソニー・コンピュータエンタテインメント アウト・オブ・オーダーのdmaコマンドキューにおけるコマンド順序の設定に関する技術
KR20140113304A (ko) * 2013-03-14 2014-09-24 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020138714A1 (en) * 2001-03-22 2002-09-26 Sun Microsystems, Inc. Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution
US7165167B2 (en) 2003-06-10 2007-01-16 Advanced Micro Devices, Inc. Load store unit with replay mechanism
EP2011018B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
CN103635875B (zh) 2011-03-25 2018-02-16 英特尔公司 用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101639853B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당
TWI548994B (zh) 2011-05-20 2016-09-11 軟體機器公司 以複數個引擎支援指令序列的執行之互連結構
KR101703400B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 마이크로프로세서 가속 코드 최적화기
WO2013077875A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. An accelerated code optimizer for a multiengine microprocessor
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
KR101800948B1 (ko) * 2013-03-15 2017-11-23 인텔 코포레이션 레지스터 뷰, 소스 뷰, 명령어 뷰, 및 복수의 레지스터 템플릿을 가진 마이크로프로세서 아키텍처를 이용하여 명령어들의 블록들을 실행하는 방법
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
KR101708591B1 (ko) 2013-03-15 2017-02-20 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
JP7428689B2 (ja) 2021-12-17 2024-02-06 華邦電子股▲ふん▼有限公司 メモリシステム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033116A2 (en) * 1997-01-29 1998-07-30 Advanced Micro Devices, Inc. A line-oriented reorder buffer for a superscalar microprocessor
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546554A (en) * 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5644742A (en) 1995-02-14 1997-07-01 Hal Computer Systems, Inc. Processor structure and method for a time-out checkpoint
US5710902A (en) 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US6098166A (en) * 1998-04-10 2000-08-01 Compaq Computer Corporation Speculative issue of instructions under a load miss shadow
JP3866921B2 (ja) * 1998-08-24 2007-01-10 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ストアアドレス生成およびユニバーサルな依存性ベクトルに基づくロードブロックのためのメカニズム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033116A2 (en) * 1997-01-29 1998-07-30 Advanced Micro Devices, Inc. A line-oriented reorder buffer for a superscalar microprocessor
JP2002513486A (ja) * 1997-01-29 2002-05-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド スーパースカラマイクロプロセッサ用ライン指向型リオーダバッファ
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007529833A (ja) * 2004-07-15 2007-10-25 株式会社ソニー・コンピュータエンタテインメント アウト・オブ・オーダーのdmaコマンドキューにおけるコマンド順序の設定に関する技術
KR20140113304A (ko) * 2013-03-14 2014-09-24 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법
JP2014179101A (ja) * 2013-03-14 2014-09-25 Samsung Electronics Co Ltd ディペンデンシーを整理し、リビルディングするシステム及び方法
KR102010312B1 (ko) 2013-03-14 2019-08-13 삼성전자주식회사 디펜던시들을 정리하고 리빌딩하는 시스템 및 방법
US10552157B2 (en) 2013-03-14 2020-02-04 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies

Also Published As

Publication number Publication date
EP1244962B1 (en) 2003-10-08
KR20020097149A (ko) 2002-12-31
DE60005860T2 (de) 2004-08-05
CN1451115A (zh) 2003-10-22
KR100747128B1 (ko) 2007-08-09
DE60005860D1 (de) 2003-11-13
WO2001050253A1 (en) 2001-07-12
EP1244962A1 (en) 2002-10-02
CN1210649C (zh) 2005-07-13

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