KR100747128B1 - 발행 후에 명령의 비투기적 성질을 발견하고 상기 명령을 재발행하는 스케줄러 - Google Patents

발행 후에 명령의 비투기적 성질을 발견하고 상기 명령을 재발행하는 스케줄러 Download PDF

Info

Publication number
KR100747128B1
KR100747128B1 KR1020027008673A KR20027008673A KR100747128B1 KR 100747128 B1 KR100747128 B1 KR 100747128B1 KR 1020027008673 A KR1020027008673 A KR 1020027008673A KR 20027008673 A KR20027008673 A KR 20027008673A KR 100747128 B1 KR100747128 B1 KR 100747128B1
Authority
KR
South Korea
Prior art keywords
instruction operation
instruction
scheduler
execution
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020027008673A
Other languages
English (en)
Korean (ko)
Other versions
KR20020097149A (ko
Inventor
켈러제임스비.
하다드램세이더블유.
마이어스테판지.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/476,204 external-priority patent/US6622235B1/en
Priority claimed from US09/476,578 external-priority patent/US6542984B1/en
Priority claimed from US09/476,322 external-priority patent/US6564315B1/en
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20020097149A publication Critical patent/KR20020097149A/ko
Application granted granted Critical
Publication of KR100747128B1 publication Critical patent/KR100747128B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
KR1020027008673A 2000-01-03 2000-08-16 발행 후에 명령의 비투기적 성질을 발견하고 상기 명령을 재발행하는 스케줄러 Expired - Fee Related KR100747128B1 (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US47657000A 2000-01-03 2000-01-03
US09/476,204 US6622235B1 (en) 2000-01-03 2000-01-03 Scheduler which retries load/store hit situations
US09/476,578 2000-01-03
US09/476,578 US6542984B1 (en) 2000-01-03 2000-01-03 Scheduler capable of issuing and reissuing dependency chains
US09/476,204 2000-01-03
US09/476,570 2000-01-03
US09/476,322 US6564315B1 (en) 2000-01-03 2000-01-03 Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
US09/476,322 2000-01-03

Publications (2)

Publication Number Publication Date
KR20020097149A KR20020097149A (ko) 2002-12-31
KR100747128B1 true KR100747128B1 (ko) 2007-08-09

Family

ID=27504212

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027008673A Expired - Fee Related KR100747128B1 (ko) 2000-01-03 2000-08-16 발행 후에 명령의 비투기적 성질을 발견하고 상기 명령을 재발행하는 스케줄러

Country Status (6)

Country Link
EP (1) EP1244962B1 (enExample)
JP (1) JP2003519833A (enExample)
KR (1) KR100747128B1 (enExample)
CN (1) CN1210649C (enExample)
DE (1) DE60005860T2 (enExample)
WO (1) WO2001050253A1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020138714A1 (en) * 2001-03-22 2002-09-26 Sun Microsystems, Inc. Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution
US7165167B2 (en) 2003-06-10 2007-01-16 Advanced Micro Devices, Inc. Load store unit with replay mechanism
US7243200B2 (en) * 2004-07-15 2007-07-10 International Business Machines Corporation Establishing command order in an out of order DMA command queue
EP2011018B1 (en) 2006-04-12 2016-07-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
KR101685247B1 (ko) 2010-09-17 2016-12-09 소프트 머신즈, 인크. 조기 원거리 분기 예측을 위한 섀도우 캐시를 포함하는 단일 사이클 다중 분기 예측
CN103635875B (zh) 2011-03-25 2018-02-16 英特尔公司 用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101639853B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당
TWI548994B (zh) 2011-05-20 2016-09-11 軟體機器公司 以複數個引擎支援指令序列的執行之互連結構
KR101703400B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 마이크로프로세서 가속 코드 최적화기
WO2013077875A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. An accelerated code optimizer for a multiengine microprocessor
US9400653B2 (en) * 2013-03-14 2016-07-26 Samsung Electronics Co., Ltd. System and method to clear and rebuild dependencies
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
KR101800948B1 (ko) * 2013-03-15 2017-11-23 인텔 코포레이션 레지스터 뷰, 소스 뷰, 명령어 뷰, 및 복수의 레지스터 템플릿을 가진 마이크로프로세서 아키텍처를 이용하여 명령어들의 블록들을 실행하는 방법
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
KR101708591B1 (ko) 2013-03-15 2017-02-20 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
JP7428689B2 (ja) 2021-12-17 2024-02-06 華邦電子股▲ふん▼有限公司 メモリシステム

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950033859A (ko) * 1994-02-02 1995-12-26 리 페치 부동 소숫점 유니트에서의 다이나믹 레지스터 관리 장치 및 방법
US5710902A (en) 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US5751985A (en) 1995-02-14 1998-05-12 Hal Computer Systems, Inc. Processor structure and method for tracking instruction status to maintain precise state
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033116A2 (en) * 1997-01-29 1998-07-30 Advanced Micro Devices, Inc. A line-oriented reorder buffer for a superscalar microprocessor
US6098166A (en) * 1998-04-10 2000-08-01 Compaq Computer Corporation Speculative issue of instructions under a load miss shadow
JP3866921B2 (ja) * 1998-08-24 2007-01-10 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ストアアドレス生成およびユニバーサルな依存性ベクトルに基づくロードブロックのためのメカニズム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950033859A (ko) * 1994-02-02 1995-12-26 리 페치 부동 소숫점 유니트에서의 다이나믹 레지스터 관리 장치 및 방법
US5751985A (en) 1995-02-14 1998-05-12 Hal Computer Systems, Inc. Processor structure and method for tracking instruction status to maintain precise state
US5710902A (en) 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
US5987594A (en) * 1997-06-25 1999-11-16 Sun Microsystems, Inc. Apparatus for executing coded dependent instructions having variable latencies

Also Published As

Publication number Publication date
EP1244962B1 (en) 2003-10-08
JP2003519833A (ja) 2003-06-24
KR20020097149A (ko) 2002-12-31
DE60005860T2 (de) 2004-08-05
CN1451115A (zh) 2003-10-22
DE60005860D1 (de) 2003-11-13
WO2001050253A1 (en) 2001-07-12
EP1244962A1 (en) 2002-10-02
CN1210649C (zh) 2005-07-13

Similar Documents

Publication Publication Date Title
KR100747128B1 (ko) 발행 후에 명령의 비투기적 성질을 발견하고 상기 명령을 재발행하는 스케줄러
US6542984B1 (en) Scheduler capable of issuing and reissuing dependency chains
EP1228426B1 (en) Store buffer which forwards data based on index and optional way match
US5226130A (en) Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US6622237B1 (en) Store to load forward predictor training using delta tag
US6564315B1 (en) Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
US6694424B1 (en) Store load forward predictor training
US6212623B1 (en) Universal dependency vector/queue entry
EP1244961B1 (en) Store to load forwarding predictor with untraining
US6502185B1 (en) Pipeline elements which verify predecode information
US6122727A (en) Symmetrical instructions queue for high clock frequency scheduling
US6212622B1 (en) Mechanism for load block on store address generation
US6393536B1 (en) Load/store unit employing last-in-buffer indication for rapid load-hit-store
US6481251B1 (en) Store queue number assignment and tracking
US6622235B1 (en) Scheduler which retries load/store hit situations
EP1296229A2 (en) Scoreboarding mechanism in a pipeline that includes replays and redirects
US6721877B1 (en) Branch predictor that selects between predictions based on stored prediction selector and branch predictor index generation
US5649137A (en) Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
EP1121635B1 (en) Mechanism for load block on store address generation and universal dependency vector
US20070033385A1 (en) Call return stack way prediction repair
US6704854B1 (en) Determination of execution resource allocation based on concurrently executable misaligned memory operations
KR20020039689A (ko) 정렬정보를 캐쉬하는 장치 및 방법
US10983801B2 (en) Load/store ordering violation management
US6721876B1 (en) Branch predictor index generation using varied bit positions or bit order reversal

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

G170 Re-publication after modification of scope of protection [patent]
PG1701 Publication of correction

St.27 status event code: A-5-5-P10-P19-oth-PG1701

Patent document republication publication date: 20080422

Republication note text: Request for Correction Notice (Document Request)

Gazette number: 1007471280000

Gazette reference publication date: 20070809

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20120727

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20130723

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20140722

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20160630

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20170802

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20170802

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000