JP2003344448A - Voltage probe, inspection method of semiconductor device using it, and semiconductor device having monitor function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage probe capable of performing comfortable real- time trace at the development time, without disposing a special connection terminal for monitoring on an LSI itself, and without enlarging the LSI scale for mass production. <P>SOLUTION: This voltage probe is characterized by including a voltage probe chip 200 equipped with a sensor electrode 204 constituted allocatably so as to face to a signal wire 104 to be monitored on a semiconductor chip 100, for detecting a voltage change of the signal wire as an induced voltage by electrostatic induction. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage probe, a method for inspecting a semiconductor device using the same, and a semiconductor device with a monitor function, and more particularly to a technique for externally monitoring a system LSI internal signal in real time.

[0002]

2. Description of the Related Art Conventionally, in order to monitor a wide bus signal such as a microcomputer or a DSP, a method of forcibly forming an LSI terminal and outputting all or selectively outputting or The internal trace memory was built in and stored in the memory, and then read by serial communication. That is, in such a method, as shown in FIG. 17, a terminal 101 for connection is specially provided for tracing and the bonding wire 1 is formed by wire bonding.
It was necessary to connect either to the signal extraction terminal 102 via 02 or to provide a pad that can be probed with a needle only at the time of inspection. For this reason, it is difficult to increase the number of signals that can be traced, and since usually 8 signals are output, there is a problem that sufficient signal monitoring cannot be performed. In addition, as semiconductor chips become highly integrated and operate at higher speeds, the coupling capacitance C1 between wirings including bonding wires is larger than the gate input capacitance C2, and sufficient sensitivity cannot be obtained.

[0003]

As described above, according to the conventional method, it is necessary to dispose the connection terminals specially for the purpose of tracing, so that the area occupied by the LSI becomes large and the LSI for mass production becomes large. It is not economically desirable to install up to.
On the other hand, there is no problem if both the mass production LSI and the development LSI can be developed, but there is a problem that it cannot be applied to all the LSIs because of cost and time. A voltage probe including an integrated circuit chip using a semiconductor substrate has also been proposed (Japanese Patent Laid-Open No. 8-254545). This probe is composed of an input and an output, an analog amplifier connectable between them, and a circuit board having a probe ground including a ground plane. However, in this voltage probe, the input needs to be connected to one of the IC inputs, and the LSI itself to be monitored still needs a special connection terminal.

In order to solve such a situation, it is desirable that the development LSI can be directly brought into the mass production line. Therefore, LSI for development and LSI for mass production
Think of them as one, and develop LSI and L for mass production.
The same SI (common LSI) is used. Then, at the time of development, by using this common LSI in combination with a trace-dedicated LSI,
I itself does not require a special connection terminal for a monitor, does not increase the scale of the LSI for mass production, and intends to enable comfortable real-time trace during development.

That is, according to the present invention, a voltage probe capable of providing a comfortable real-time trace at the time of development without disposing a special connection terminal for monitoring on the LSI itself, increasing the scale of the LSI for mass production. The purpose is to provide.

Further, according to the present invention, the LSI itself is not provided with a special connection terminal for monitoring, the scale of the LSI for mass production is not increased, and a comfortable real-time trace can be performed at the time of development. It is an object to provide a method for inspecting a semiconductor device.

Furthermore, the present invention provides a semiconductor device with a monitor function that does not require a special connection terminal, does not increase the scale of an LSI for mass production, and enables comfortable real-time tracing during development. The purpose is to do. Moreover, it aims at providing the voltage probe which can monitor a high-speed signal.

[0008]

Therefore, in the present invention, the signal lines to be monitored on the semiconductor chip are arranged so as to be opposed to each other, and the voltage change of the signal lines is induced by electrostatic induction. It is characterized in that it is provided with a sensor unit for detecting it as a voltage.

According to this structure, since the signal line can be monitored in a non-contact manner, the semiconductor chip itself can be basically formed for monitoring without changing the design, and the cost can be reduced. It becomes possible to perform highly reliable signal monitoring. Further, since wire bonding is not necessary and the chip itself can be formed without adding a special additional circuit, parasitic capacitance does not occur, and high-speed and highly reliable monitoring is possible.

Preferably, the sensor section is connected to the signal line of the semiconductor chip, and is arranged so as to be capacitively coupled in a non-contact manner to a wiring pattern drawn near the surface. .

According to this structure, since the sensor section extracts the signal by non-contact capacitive coupling, a highly accurate and highly reliable monitor can be realized without any restriction on the design of the semiconductor chip. It will be possible.

Preferably, the sensor portion is connected to the signal line of the semiconductor chip, and is arranged so as to face each of a plurality of wiring patterns that are drawn out and arranged in the vicinity of the surface, and contact-free capacitance is provided. It is characterized by comprising a plurality of sensor units arranged so as to be coupled.

According to this structure, in addition to the above effects, it is possible to easily obtain a highly reliable monitor output even when there is a high-density signal wiring.

Preferably, the plurality of sensor units are provided with crosstalk preventing means.

According to this structure, in addition to the above effects, the crosstalk prevention means is provided, so that it is possible to obtain a highly reliable monitor output even in a region where high-density signal wiring exists. .

Preferably, the sensor portion is formed on the surface of the semiconductor substrate and includes a sensor electrode formed so as to be capacitively coupled to the wiring pattern via a dielectric layer between the sensor pattern and the wiring pattern. .

According to this structure, the sensor portion is formed on the surface of the semiconductor substrate and includes the sensor electrode formed so as to be capacitively coupled to the wiring pattern through the dielectric layer between the sensor pattern and the wiring pattern. Since it is configured, if the sensor electrode and the wiring pattern are capacitively coupled via the dielectric layer formed on the surface of either the semiconductor chip to be monitored or the sensor electrode of the chip that constitutes the voltage probe It is possible to obtain an output that is good, extremely easy to form, and highly reliable.

Preferably, the dielectric layer is a probe dielectric film formed on the surface of the sensor electrode.

According to this structure, the probe dielectric film is capacitively coupled through the probe dielectric film formed on the surface of the sensor electrode. Therefore, the probe dielectric film also effectively acts as a protective film of the sensor electrode, and the durability of the probe is improved. It is possible to improve the sex.

Preferably, the dielectric layer is a dielectric film formed on the surface of the wiring pattern to be measured.

According to this structure, since the wiring pattern of the semiconductor chip may be covered with the dielectric film without being exposed, the reliability of the semiconductor chip can be improved.

Preferably, the dielectric layer is a composite film of a probe dielectric film formed on the surface of the sensor electrode and a dielectric film formed on the surface of the wiring pattern to be measured. And

According to this structure, since the probe dielectric film formed on the surface of the sensor electrode and the dielectric film formed on the surface of the wiring pattern to be measured are capacitively coupled through the composite film, This composite dielectric film effectively acts as a protective film for the sensor electrode and the wiring pattern on the chip, and the durability of the semiconductor chip and the probe can be improved.

Preferably, the sensor section is formed on the surface of a semiconductor substrate, and a plurality of sensor electrodes formed so as to be capacitively coupled to the wiring pattern via a dielectric layer between the sensor pattern and the wiring pattern, And a crosstalk prevention unit formed of an insulating region formed between the sensor electrodes.

According to this structure, since the crosstalk preventing means is provided, it is possible to obtain a highly reliable monitor output even in a region where high-density signal wiring exists.

Preferably, the sensor section includes a plurality of sensor electrodes formed on the surface of the semiconductor substrate and capacitively coupled to the wiring pattern via a dielectric layer between the sensor pattern and the wiring pattern. The sensor electrodes are arranged at a pitch that is sufficiently narrower than a signal wiring portion that draws out a signal to be monitored in a wiring pattern near the chip surface.

According to this structure, the sensor electrodes are arranged at a pitch which is sufficiently narrower than the signal wiring portion which leads out the signal to be monitored to the wiring pattern close to the chip surface. Even if there is a positional deviation from the wiring pattern, the signal can be taken out by any of the sensor electrodes without causing leakage.

Further, since it does not have to have a one-to-one correspondence with the wiring pattern, a general-purpose monitor chip can be constructed.

Further, a signal processing circuit for selecting a sensor electrode having a maximum voltage induced from each of the sensor electrodes is provided, and a signal from the sensor electrode selected by the signal processing circuit is output to the signal line. It is characterized in that it is configured to be taken out as.

According to such a configuration, the signal processing circuit for selecting the sensor electrode having the maximum voltage induced from each of the sensor electrodes is provided, and the signal from the sensor electrode selected by the signal processing circuit is applied to Since the signal is output as the output of the signal line, even when the position of the semiconductor chip is displaced from the wiring pattern, the signal processing allows the signal to be output by any of the sensor electrodes without leakage. .

Further, since it does not have to have a one-to-one correspondence with the wiring pattern, a general-purpose monitor chip can be constructed.

Desirably, the sensor electrode is formed so as to be opposed to the signal line to be monitored on the semiconductor chip and is formed in a predetermined region on the surface of the semiconductor substrate as the monitor chip, and the sensor. It is characterized by comprising a sensor unit including a signal processing circuit that detects a voltage change of the signal line based on the output of the electrode as an induced voltage due to electrostatic induction and outputs a desired monitor signal.

According to this structure, since the probe is formed on the semiconductor substrate, it can be easily manufactured and miniaturized.

Preferably, the monitor chip is composed of a semiconductor substrate having substantially the same size as the semiconductor chip,
On the signal line to be monitored on the semiconductor chip,
A chip-on-chip connection is possible so that the sensor electrodes face each other and are electrostatically coupled.

According to this structure, since chip-on-chip connection is possible, the wiring length can be minimized and high-speed processing can be performed. In addition, the overall size can be reduced and the handling is easy.

Preferably, the monitor chip is a multi-layered substrate provided with a voltage sense amplifier arranged immediately below the monitor chip so as to correspond to the sensor electrode.

According to this structure, since the monitor chip is composed of the multi-layered structure substrate having the voltage sense amplifier arranged immediately below it corresponding to the sensor electrode, it is small and reliable. Is also high.
Also, since this voltage sense amplifier is configured to have an elongated shape, it is possible to reduce the input gate capacitance of the voltage sense amplifier with respect to the advertised capacitance of the sensor and wiring, thus increasing the input sensitivity. You can In addition, the wiring on the voltage sense amplifier side can be shortened, and the effect of inducing noise from the surroundings can be reduced.

Further, in the semiconductor device of the present invention, the semiconductor substrate has a first lead-out region formed so that the signal line to be monitored becomes a closest conductor layer from the outer surface of the chip. A semiconductor chip, a formed sensor electrode facing each other in the extraction region and electrostatically coupled to each other, a voltage change of the signal line based on the output of the sensor electrode, is detected as an induced voltage by electrostatic induction, A second semiconductor chip as a monitor chip having a sensor unit having a signal processing circuit for outputting a desired monitor signal is coupled to the second semiconductor chip.

According to this structure, since the monitor chip is coupled to the semiconductor chip requiring measurement, it can be formed without increasing the scale of mass production LSI. Further, it is possible to realize a semiconductor device with a monitor function capable of performing comfortable real-time trace during development.

Preferably, the monitor signal is the second signal.
From the semiconductor chip to the first chip,
It is characterized in that it is configured to be output from the first chip.

According to this structure, it can be realized by a conventional semiconductor device assembling method.

Preferably, the monitor signal is the second signal.
The semiconductor chip is configured to output from the sensor electrode formation surface side.

According to such a configuration, it is not necessary to form an output terminal for monitoring on the LSI, and it can be realized without increasing the area of the LSI.

Preferably, the monitor chip is formed thin enough to be folded back.

According to this structure, since the monitor chip can be bent and connected by wire bonding, the degree of freedom of connection is high and the workability of measurement is easy.

Preferably, the monitor signal is the second signal.
The semiconductor chip is configured so as to be output from the surface opposite to the surface on which the sensor electrode is formed.

According to this structure, it is not necessary to form an output terminal for a monitor on the LSI, and the LSI can be realized without increasing the area of the LSI. In addition, since the electrodes are taken out from the side opposite to the sensor electrode forming surface, the wiring can be easily drawn out.

Further, it is desirable that the monitor chip is completely folded.

According to such a configuration, the monitor chip 50
Even if the LSI substrate is large, it can be easily mounted by processing it to a thickness of about μm. The monitor chip is L
When pressure-bonding to the SI chip, some undulations on the surface can be absorbed, so good bonding is possible. Here, the curvature can be easily calculated from the elastic modulus and the thickness of the substrate.

In the present invention, the lead-out region is formed so that the signal line to be monitored is the closest conductor layer from the outer surface of the chip, and the signal line in the lead-out region is opposed to the signal line. A first semiconductor chip including a sensor electrode formed via a dielectric layer so as to be electrostatically coupled, a lead electrode in contact with the sensor electrode, and the lead electrode via the lead electrode. A signal processing circuit that outputs the output of the sensor electrode that is electrostatically coupled opposite to the region, detects a voltage change of the signal line as an induced voltage due to electrostatic induction, and outputs a desired monitor signal. And a second semiconductor chip serving as a monitor chip having a sensor section having the above.

According to this structure, it can be realized by a conventional semiconductor assembling method.

In the method of the present invention, the sensor electrodes are arranged so as to face each other on the signal line to be monitored on the semiconductor chip, and the voltage change of the signal line is detected as an induced voltage due to electrostatic induction. It is characterized by having done.

According to this structure, it is possible to perform a highly accurate and highly reliable monitor without any restrictions on the design of the semiconductor chip.

Desirably, a plurality of sensor electrodes are arranged on the signal line to be monitored on the semiconductor chip so as to face each other at a narrower pitch than the signal line, and a voltage change of the signal line is electrostatically induced. First detection step of detecting as an induced voltage by, a selection step of performing signal processing on the induced voltage and selecting a sensor electrode having the maximum output, and driving only the sensor electrode selected in the selection step, and a signal line A second detection step of detecting the voltage change of No. 2 as an induced voltage due to electrostatic induction, wherein the first detection step is a detection step using a lower frequency than the second detection step. Is characterized by.

According to this structure, if the low frequency processing is performed in the process for selecting the sensor electrode and the high frequency processing actually used in the actual monitoring process is performed, the monitor output with high reliability can be easily obtained. Can be obtained.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION A monitor device using a voltage probe of the present invention includes a signal line 104 forming a bus in an LSI chip 100 to be monitored and a voltage probe chip 200 as shown in an equivalent circuit of FIG. Sensor electrode 20
4 is capacitively coupled via a dielectric film, and is configured to monitor a change in a signal passing through each of the signal lines 104. Here, it is assumed that the coupling capacitance C1 between the signal line 104 and the sensor electrode 204 is sufficiently larger than the gate input capacitance C2. Hereinafter, embodiments of the present invention will be described.

(First Embodiment) FIG. 1 shows a basic configuration of the present invention. As shown in FIGS. 1 and 2, this voltage probe is connected to a signal line 104 to be monitored on an LSI chip 100 forming a system LSI,
The sensor units 204 are formed so as to face each other, and the voltage probe chip 200 configured to detect the voltage change of the signal line as an induced voltage due to electrostatic induction is arranged.

Here, the voltage probe chip includes a signal processing circuit section 202 such as an amplifier circuit formed on the surface of the silicon substrate 201, and the LSI chip 10 to be monitored.
The sensor section 204 arranged so as to face each other on the signal line above 0, and the film thickness t covering the surface of the sensor section 204.
= 0.5 μm silicate glass layer (dielectric layer) 205
It consists of and. This sensor unit 204 has a thickness of 0.6 μm.
Square square sensor units are arranged at a pitch L = 6 μm. Further, the silicate glass covering the surface of the sensor portion 204 is composed of a silicate glass layer 205 having a relative dielectric constant of 4 and a film thickness of 0.5 μm, and the surface is polished to be smooth.

This voltage probe chip is formed by a normal semiconductor process using a silicon wafer as a starting material. Here, from the viewpoint of preventing crosstalk, it is desirable to design the pitch L to be sufficiently larger than the film thickness t of the silicate glass layer 205. Strictly speaking, the dielectric film 205 formed near the sensor electrodes 204 is composed of an interlayer insulating film 205a arranged between the sensor electrodes and a dielectric film 205b formed on the sensor electrodes. In terms of manufacturing, it is desirable that the same film is used for forming silicate glass, but other films may be used. In that case, it is desirable to use, as the interlayer insulating film 205a arranged between the sensor electrodes, one having a higher dielectric constant than the dielectric film 205b formed on the sensor electrodes. This makes it possible to reduce crosstalk. For example, the insulator of the sensor electrode serving as an antenna is made of a dielectric material, and the space between the adjacent electrode is made of air, etc., so that the crosstalk is significantly reduced.

On the other hand, the LSI chip to be monitored has through holes (see FIG. 3) so that the signal lines are exposed at the surface of the silicon substrate 101 in which desired element regions are formed with the wiring layer 102 arranged at predetermined intervals. (Not shown) to form a so-called rearranged wiring structure, and monitor area 1
05 is configured. Therefore, the structure is such that the monitor region in which the sensor electrodes 104 are arranged is laminated on the element region via the interlayer insulating film 103, and basically the element area does not increase. This surface is also CMP
It is flattened by a (chemical mechanical polishing) method or the like.

The LSI chip 1 thus formed
00 and the voltage probe chip 200 are cleaned, then the sensor electrode 204 of the voltage probe chip 200 is positioned so as to lie on the monitor region 105 of the LSI chip 100, and pressure is applied while vacuum suction, and fixed by direct bonding. .

In this state, an actual voltage used at the time of use is applied to the external extraction terminal of the LSI chip to drive it. Then, the induced voltage at this time is detected by the sensor electrode 204 of the voltage probe, and is monitored via the signal processing circuit 202. For example, if there is a voltage change ΔV on the signal line 104, signal processing is performed in the signal processing circuit 202 and an output voltage ΔV ′ appears.

Here, the voltage probe chip 200 is
A sensor electrode 204 and a signal processing circuit 202 including a voltage amplifier circuit designed to have an extremely high input impedance are formed as an integrated circuit immediately below the sensor electrode. The signal line (bus signal line) 104 of the LSI chip 100 and the voltage probe chip 200
The sensor electrode 204 has a physically mirrored pattern, and the element surfaces of the LSI chip 100 and the voltage probe chip 200 are face-to-face face-to-face so that no positional deviation occurs after alignment. It is fixed by direct bonding to.

This signal line 104 and the sensor electrode 204
Are electrostatically coupled, amplified by a voltage amplifier mounted on the voltage probe chip 200, and subjected to signal processing by a signal processing circuit so as to withstand electric transmission from there to a measuring instrument.

As a result, the system LSI chip 100
Since it is possible to operate the whole by dividing it into voltage probe chips without mounting a circuit for tracing on, the two chips are bonded and used only during development, and only the system LSI chip 100 is used during mass production. It is extremely economical because it can be done.

Further, since the signal line can be monitored in a non-contact manner, basically the semiconductor chip itself can be formed without changing the design for monitoring, which is low cost and highly reliable. It becomes possible to perform signal monitoring.

Also, wire bonding is unnecessary,
Since the chip itself can be formed without adding a special additional circuit, parasitic capacitance does not occur and high-speed and highly reliable monitoring is possible.

Furthermore, since the sensor section extracts signals by non-contact capacitive coupling, it is possible to perform highly accurate and highly reliable signal monitoring without any restrictions on the design of the semiconductor chip. Is possible.

Further, even if there is a high-density signal wiring, it is possible to easily obtain a highly reliable monitor output. In the first embodiment, an example in which the voltage probe chips of the same size are mounted on the surface of the LSI chip has been described, but only a part of the monitor area is bonded as shown in a modified example of FIG. It goes without saying that the voltage probe chip 220 having such a configuration may be used, the voltage probe chip may be connected to the signal processing circuit chip 221, and the signal processing may be performed in the signal processing circuit chip 221.

(Second Embodiment) Next, a second embodiment of the present invention will be described. In the first embodiment, the silicate glass layer 20 having a relative dielectric constant of 4 and a film thickness of 0.5 μm formed on the sensor electrode surface of the voltage probe chip.
I tried to generate an induced voltage through 5b,
In this example, the surface of the LSI chip 100 side is also covered with the silicate glass layer 105. In this example, as shown in FIG. 4, the silicate glass layers 105 and 205S of the LSI chip and the voltage probe chip are used.
An induced voltage is generated through the adhesive layer 300 and the adhesive layer 300 therebetween.

The sensor electrode of this voltage probe chip is provided with a silicate glass layer 205S having a relative dielectric constant of 4 and a film thickness of 0.2 μm, while the surface of the signal line 104 of the LSI chip 100 has a relative dielectric constant of 4, An adhesive resin 300 covered with a silicate glass layer 105 having a film thickness of 0.2 μm and controlled to have a film thickness of 0.1 μm between them.
It is stuck in.

Here, since the LSI chip surface is also covered with the silicate glass layer, the reliability is improved as compared with the case of the first embodiment in which the signal line is exposed, but the film thickness of this adhesive resin 300. Must be controlled with high precision.

(Third Embodiment) Next, a third embodiment of the present invention will be described. In this embodiment, as shown in FIG. 5, as a measure against the crosstalk noise of the voltage induced in the sensor electrode 204, the peripheral potential is kept at the ground level so that the cross section is skewed between the sensor electrodes 204. A grounding electrode 207 for the purpose is inserted.

In this structure, the ground electrode 207 extends between the opposing signal lines and is formed so as to be flush with the tip of the silicate glass layer 205 which is the dielectric layer. For this reason, it is necessary to perform positioning and joining with high accuracy, and there is a high risk of short-circuiting if misalignment occurs. For this reason, it is easier to process the ground electrode 207 so that it is not exposed to the surface and formed to a depth such that the surface is covered with a thin silicate glass layer, if necessary. The other parts are formed in the same manner as in the first embodiment.

According to this structure, in addition to the effects of the first embodiment, it is possible to reduce crosstalk. Although the system LSI chip side is not provided with a ground electrode, if a physically permitted layout is possible, the signal lines are also separated from each other by a ground layer in the monitor area on the LSI chip side. It is possible to further reduce the talk noise.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. In this example, as shown in FIG. 6, the sensor electrode is provided with a plurality of sensor electrodes 214 formed so as to be capacitively joined to the signal lines in the monitor region of the LSI chip at a narrow pitch. That is,
Mechanical alignment is achieved by providing the sensor electrodes 214 in a number larger than the number of signal line patterns and by mounting a selector circuit that selectively uses only the sensor electrode having the strongest electrostatic coupling from a plurality of sensor electrode groups. It is the one that can be roughened. That is,
Even if a slight displacement occurs, in the signal processing circuit,
It suffices to make adjustment so that only the one with a large output signal is taken out, and for mechanical alignment, attention is paid only to the inclination of the signal line so that the signal line and the sensor electrode are arranged in parallel. Further, this voltage probe chip is not necessarily the same as the pitch of the signal lines in the monitor area of the LSI chip to be measured, and is therefore effective as a general-purpose voltage probe.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. In this embodiment, as shown in FIG. 7, sensor electrode units 224 composed of three small sensor electrodes 224S are arranged corresponding to each signal line, and an induced voltage due to a signal passing through each signal line is generated. Three
The small sensor electrode 224S of the book is used for detection and signal processing for noise removal is performed. That is, in this example, in order to suppress the crosstalk of the induced voltage, 3
By using the small sensor electrode 224S of the book, not only the center but also the signal levels on both sides are traced, and then the noise is reduced by the arithmetic processing.

For example, assuming that there are first to fourth signal wirings as shown in FIG. 7, the second monitor signal line 1 out of the monitor signal lines 104A to 104C on the second signal wiring.
When the detection signal by the sensor electrode unit 224 on 03A is obtained, the output of each of the three small sensor electrodes 224S also reads the signals of the adjacent monitor signal lines 104B and 104C. Therefore, in this example, the sensor signal resulting from the output of the adjacent signal line is sensed by using the three small sensor electrodes. First, the mutual electrode distances are obtained, the corresponding attenuation amount is determined, and then the opposite phases of the signals from the adjacent sensor electrodes are added. The calculation algorithm multiplies the signals of adjacent electrodes by a gain considering the distance and subtracts the original signal to cancel the noise.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described. In this embodiment, a voltage probe tip will be described. 8A and 8B show a voltage probe tip 20 provided with a sensor electrode.
The detailed structure is 0, and a gate with a long gate length L is constructed immediately below the sensor electrode line.
A voltage amplifier having an OS transistor as a front stage is formed. Further, a negative feedback high resistance 227 for self-bias is similarly constructed.

Here, the length of the sensor electrode 204 is larger than the gate capacitance by 10 times or more the electrostatic coupling capacitance between the bus signal line 104 and the sensor electrode line of the LSI chip 100 to be monitored as shown in FIG. Is designed to be.

The length of the sensor electrode can be reduced by reducing the distance at the time of electrostatic coupling, that is, the thickness of the dielectric layer between the signal line and the sensor electrode, but this is also a manufacturing limit. It is an important issue involved.

Here, the signal processing circuit 202 includes a source / drain region 220 formed on the surface of the silicon substrate 201.
221 and the gate electrode 2 formed between the source / drain regions 220 and 221 via the gate insulating film 225.
Transistors for amplification are arranged in an array, and the gate electrode 226 corresponds to the corresponding sensor electrode and the silicate glass film 2 as an interlayer insulating film.
It is formed through the contact formed in 05.
Here, in FIG. 8B, the silicate glass film as a dielectric film covering the surface of the sensor electrode is omitted.

As a modification of the embodiment of the present invention, an electrical contact is made between the system LSI chip and the voltage probe chip, and an electrostatic coupling portion is provided inside the system LSI chip. Is also effective.

According to this structure, if a contact can be established between the system LSI chip and the voltage probe chip, a dielectric film is formed inside the system LSI chip and electrostatic coupling is performed via this dielectric film. Since it may be performed, the film thickness of the dielectric film can be controlled to be uniform, and high-accuracy signal monitoring can be performed.

(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
The embodiment will be described. FIG. 9 shows an example of the structure of the signal extraction unit. In this example, a signal from a signal processing circuit 202 including a sensor electrode 204 and an amplifier circuit of a chip 200 formed by forming an integrated circuit on a silicon substrate 201 is electrode-formed. One connected to the pad 12 of the system LSI chip 100 via the bump 10 formed on the pad 15 and further taken out to the bonding wire 14 via the bonding pad 13 formed at the end of the system LSI chip 100. Is. Here, the detected signal is output from the system LSI chip 100 to the measuring device (not shown) via the bonding pad 13 and the wire 14.

(Eighth Embodiment) Next, the eighth embodiment of the present invention
The embodiment will be described. FIG. 10 shows an eighth embodiment of the present invention, in which a TAB cable (Tape automated bonding Ca) is passed from the element surface of the voltage probe chip 200 on which the sensor electrode is mounted via the pad 15.
ble) 16 is bump-connected and output to the measuring instrument.

(Ninth Embodiment) Next, the ninth embodiment of the present invention will be described.
The embodiment will be described. FIG. 11 shows a ninth embodiment, in which a through hole 17 is formed on the surface of the voltage probe chip 200 on which the sensor electrode is mounted, which surface is opposite to the element surface.
The signal is taken out via the bonding pad 15
Via a bump connection to the TAB cable 16 via the.

(Tenth Embodiment) Next, a tenth embodiment of the present invention will be described. In this example, FIG.
As shown in FIG. 2, the system LSI chip 100 and the voltage probe chip 200 are electrically contacted with each other, and an electrostatic coupling portion is provided inside the voltage probe chip 200.

That is, it has a structure in which the auxiliary electrode 208 is sandwiched in the basic structure described in the first embodiment, and the auxiliary electrode 208 is provided on the sensor electrode 204 of the voltage probe chip 200 with the dielectric film 209 interposed therebetween. The sensor electrode 20
4 is electrostatically coupled and electrically insulated. The signal line 104 is electrically connected to this auxiliary electrode 208. The contacting wiring pattern portion is plated with nickel / gold to stabilize the contact.

In this embodiment, the auxiliary electrode 208 is mounted on the chip 200 on which the sensor electrode is mounted. However, mounting the auxiliary electrode on the system LSI side as described above makes the bus of the system LSI bus. Is preferred for high speed devices due to the low load capacity for On the other hand, the manufacturing process of the system LSI becomes complicated, which is disadvantageous in terms of cost. Therefore, the example of this embodiment is more preferable in view of ease of manufacturing and cost.

(Eleventh Embodiment) Next, an eleventh embodiment of the present invention will be described. In this example, FIG.
As shown in FIG. 3, the detailed structure of the voltage probe chip 200 including the sensor electrode is shown. In this example, as described in the sixth embodiment described with reference to FIG. 8, a sensor electrode 226 having a voltage amplifier having P-ch and N-ch MOS transistors as a preceding stage is provided immediately below.
Are arranged in a matrix form. Further, a negative feedback high resistance 227 for self-bias is similarly constructed. According to this configuration, it is suitable for observation when the functional blocks are arranged on the array.

(Twelfth Embodiment) Next, a twelfth embodiment of the present invention will be described. In this example, FIG.
As shown in FIG. 4, the detailed structure of the voltage probe chip 200 including the sensor electrode is shown. In this example, as described in the sixth embodiment described with reference to FIG. 8, a sensor electrode 226 having a voltage amplifier having P-ch and N-ch MOS transistors as a preceding stage is provided immediately below.
Is arranged in a fan shape.

Further, a negative feedback high resistance 227 for self-bias is similarly constructed.
According to such a configuration, it is suitable for a high-speed circuit to the extent that it is necessary to arrange the functional blocks by providing equal-length wiring.

(Thirteenth Embodiment) Next, a thirteenth embodiment of the present invention will be described. FIG. 15 shows the thirteenth
In this embodiment, the voltage probe chip 200 on which the sensor electrode is mounted is thinly processed to about 50 μm so that the substrate can be bent and connected. Other parts are formed similarly to the voltage probe chip of the twelfth embodiment. If the voltage probe chip 200 can be bent more than the thickness of the extraction electrode, the effect that the connection is easy, the use place is not selected, and the flexibility is high is achieved.

Further, when the voltage probe chip having the sensor electrode mounted thereon is pressure-bonded, some undulations on the surface of the substrate to be measured can be absorbed, so that good bonding can be performed. This example is similar to the voltage probe chips of the eighth and ninth embodiments except that the substrate is thin.

(Fourteenth Embodiment) Next, a fourteenth embodiment of the present invention will be described. FIG. 16 shows the fourteenth
In this embodiment, the voltage probe chip 200 on which the sensor electrode is mounted is thinly processed to about 50 μm so that the substrate can be connected to such an extent that the substrate can be folded back. Other parts are formed in the same manner as the voltage probe chip of the ninth embodiment. If the voltage probe chip 200 can be bent to such an extent that it can be folded back, connection can be made by wire bonding, and the degree of freedom is improved.

[0097]

The LSI for development and the LSI for mass production are integrated into one, and at the time of development, the LS dedicated to the trace is used.
By using the voltage probe in combination with I, it is possible to provide a voltage probe that does not increase the scale of the LSI for mass production and can perform comfortable real-time trace during development.

Further, according to the method of the present invention, it is possible to provide a method for inspecting a semiconductor device which can monitor signals easily and with good workability.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a sectional configuration diagram showing a first embodiment of the present invention.

FIG. 3 is a basic configuration diagram showing a modification of the first embodiment of the present invention.

FIG. 4 is a basic configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a sectional configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a sectional configuration diagram showing a fourth embodiment of the present invention.

FIG. 7 is a sectional configuration diagram showing a fifth embodiment of the present invention.

FIG. 8 is an enlarged cross-sectional view and a top view illustrating a sixth embodiment of the present invention.

FIG. 9 is a cross-sectional configuration diagram showing a seventh embodiment of the present invention.

FIG. 10 is a sectional configuration diagram showing an eighth embodiment of the present invention.

FIG. 11 is a sectional configuration diagram showing a ninth embodiment of the present invention.

FIG. 12 is a sectional configuration diagram showing a tenth embodiment of the present invention.

FIG. 13 is a sectional configuration diagram showing an eleventh embodiment of the present invention.

FIG. 14 is a sectional configuration diagram showing a twelfth embodiment of the present invention.

FIG. 15 is a sectional configuration diagram showing a thirteenth embodiment of the present invention.

FIG. 16 is a sectional configuration diagram showing a fourteenth embodiment of the present invention.

FIG. 17 is an equivalent circuit diagram showing a conventional signal monitoring method.

[Explanation of symbols]

100 system LSI chip 200 voltage probe tip 104 signal line 204 sensor electrode (sensor part) 10 bumps 12, 13, 15 pads 14, 16 Bonding wire

Claims (23)

[Claims] 1. A sensor unit, which is arranged so as to be opposed to a signal line to be monitored on a semiconductor chip, and which detects a voltage change of the signal line as an induced voltage due to electrostatic induction. Voltage probe characterized by. 2. The sensor section is connected to the signal line of the semiconductor chip, and is arranged so as to be capacitively coupled in a non-contact manner to a wiring pattern drawn near the surface. The voltage probe according to item 1. 3. The sensor section is connected to the signal line of the semiconductor chip, and is arranged so as to face each of a plurality of wiring patterns that are drawn out and arranged in the vicinity of the surface,
The voltage probe according to claim 1, further comprising a plurality of sensor units arranged so as to be capacitively coupled in a non-contact manner. 4. The voltage probe according to claim 3, wherein the plurality of sensor units further include crosstalk preventing means. 5. The sensor unit includes a sensor electrode formed on the surface of a semiconductor substrate and formed so as to be capacitively coupled to the wiring pattern via a dielectric layer between the wiring pattern and the wiring pattern. The voltage probe according to claim 1, wherein 6. The voltage probe according to claim 4, wherein the dielectric layer is a probe dielectric film formed on the surface of the sensor electrode. 7. The voltage probe according to claim 4, wherein the dielectric layer is a dielectric film formed on the surface of the wiring pattern to be measured. 8. The dielectric layer is a composite film of a probe dielectric film formed on the surface of the sensor electrode and a dielectric film formed on the surface of the wiring pattern to be measured. The voltage probe according to claim 4. 9. The sensor section is formed on the surface of a semiconductor substrate, and a plurality of sensor electrodes formed so as to be capacitively coupled to the wiring pattern via a dielectric layer between the sensor pattern and the wiring pattern, and the sensor. The voltage probe according to claim 3, further comprising a crosstalk prevention unit formed of an insulating region formed between the electrodes. 10. The sensor unit includes a plurality of sensor electrodes formed on the surface of a semiconductor substrate and capacitively coupled to the wiring pattern via a dielectric layer between the sensor unit and the wiring pattern. 4. The sensor electrodes are arranged at a pitch, which is sufficiently narrower than a signal wiring portion that draws out a signal to be monitored in a wiring pattern near the chip surface. The voltage probe described in. 11. A signal processing circuit for selecting a sensor electrode having a maximum voltage induced from each of said sensor electrodes, wherein a signal from said sensor electrode selected by said signal processing circuit is supplied to said signal line. The voltage probe according to claim 10, wherein the voltage probe is configured to be taken out as an output of the voltage probe. 12. A sensor electrode formed on a surface of a semiconductor substrate as a monitor chip, the sensor electrode being arranged so as to be opposed to a signal line to be monitored on a semiconductor chip, and the sensor electrode. The voltage probe is provided with a signal processing circuit that detects a voltage change of the signal line as an induced voltage due to electrostatic induction on the basis of the output of 1. and outputs a desired monitor signal. 13. The monitor chip is composed of a semiconductor substrate having substantially the same size as the semiconductor chip, and the sensor electrodes face each other and are electrostatically coupled to a signal line to be monitored on the semiconductor chip. The voltage probe according to claim 12, wherein the voltage probe is configured to be chip-on-chip connectable. 14. The voltage probe according to claim 13, wherein the monitor chip is a multi-layer structure substrate including a voltage sense amplifier arranged immediately below the monitor chip so as to correspond to the sensor electrode. . 15. A first semiconductor chip having a lead-out region formed so that a signal line to be monitored is formed as a closest conductor layer from the outer surface of the chip, and is opposed to the first lead-out region. And a signal processing circuit that detects a voltage change of the signal line based on the output of the sensor electrode as an induced voltage due to electrostatic induction and outputs a desired monitor signal. And a second semiconductor chip as a monitor chip having a sensor section provided with the semiconductor device, the semiconductor device having a monitor function. 16. The monitor signal is further configured to be returned from the second semiconductor chip to the first chip and output from the first chip. A semiconductor device with a monitor function according to. 17. The semiconductor device with a monitor function according to claim 15, wherein the monitor signal is output from the sensor electrode formation surface side of the second semiconductor chip. 18. The semiconductor device with a monitor function according to claim 1, wherein the monitor chip is formed thin enough to be folded back. 19. The semiconductor device with a monitor function according to claim 15, wherein the monitor signal is output from a surface of the second semiconductor chip facing the sensor electrode formation surface. apparatus. 20. The semiconductor device with a monitor function according to claim 19, wherein the monitor chip is completely folded back. 21. A lead-out region is formed so that the signal line to be monitored is the closest conductor layer from the outer surface of the chip, and the signal line in the lead-out region is opposed to an electrostatic region. A first semiconductor chip comprising a sensor electrode formed via a dielectric layer so as to be bonded, a lead electrode in contact with the sensor electrode, and a lead electrode in the lead region via the lead electrode. A signal processing circuit is provided that takes out the output of the sensor electrodes that are oppositely and electrostatically coupled to each other, detects a voltage change of the signal line as an induced voltage due to electrostatic induction, and outputs a desired monitor signal. And a second semiconductor chip as a monitor chip having a sensor section, which is combined with the second semiconductor chip. 22. A sensor electrode is arranged so as to face each other on a signal line to be monitored on a semiconductor chip, and a voltage change of the signal line is detected as an induced voltage due to electrostatic induction. A characteristic semiconductor chip monitoring method. 23. A plurality of sensor electrodes are arranged on a signal line to be monitored on a semiconductor chip so as to face each other at a narrower pitch than the signal line, and a voltage change of the signal line is changed by electrostatic induction. A first detection step of detecting as an induced voltage, a selection step of performing signal processing on the induced voltage and selecting a sensor electrode having the maximum output, and driving only the sensor electrode selected in the selection step, A second detection step of detecting a voltage change as an induced voltage due to electrostatic induction, wherein the first detection step is a detection step using a low frequency as compared with the second detection step. Claim 2 characterized by the above-mentioned.
2. The method for monitoring a semiconductor chip according to 2.