CN111929571A

CN111929571A - LED chip test fixture, test method and test system

Info

Publication number: CN111929571A
Application number: CN202011114901.5A
Authority: CN
Inventors: 林智远; 闫晓林
Original assignee: Shenzhen TCL High-Tech Development Co Ltd
Current assignee: Shenzhen TCL High-Tech Development Co Ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2020-11-13
Anticipated expiration: 2040-10-19
Also published as: CN111929571B

Abstract

The application relates to an LED chip test fixture, a test method and a test system, wherein the LED chip test fixture provides a substrate paved with test electrodes, after an electrolyte layer on the substrate is attached to a chip film paved with LED chips arranged in an array, a positive test electrode and a negative test electrode can be respectively aligned with the corresponding electrodes of the LED chips to be tested, effective capacitive coupling is formed to supply power, and therefore the LED chips are subjected to photoelectric characteristic test.

Description

LED chip test fixture, test method and test system

Technical Field

The invention belongs to the technical field of Light Emitting Diode (LED) testing, and particularly relates to an LED chip testing jig, a testing method and a testing system.

Background

The Micro LED chip can be used for Direct-View (English: Direct View) display technology to form a light-emitting unit, and has the advantages of high brightness, wide color gamut, high stability, long service life, energy conservation, transparency and the like. However, the current miniaturized LED display technology has many technical difficulties to be solved in mass production, and the measurement of the photoelectric characteristics is one of the difficulties.

On the one hand, the repair cost of miniaturized Micro LED chips for direct-view display technology is high, so that the LED chips must be placed on a target backplane with high yield to reduce the number of repairs, which requires that the LED chips be subjected to sufficient photoelectric characteristic tests before being transferred in a large amount to ensure that the transferred chip yield is close to 100%.

On the other hand, the Micro LED chip has small size, the probe used by the traditional probe type electroluminescence (English) test method has larger size, effective electrical contact is difficult to form between the probe and the electrode of the LED chip, and the test efficiency and the accuracy are low; however, the direct-view technology has a huge demand on the LED chips, and the traditional probe-type LED electroluminescence test method is difficult to meet the demand on productivity. In addition, the traditional Photoluminescence (english: Photoluminescence) test method can achieve a higher test speed, and can also make a certain judgment on the yield of the LED chip according to the Photoluminescence test result, but the accuracy of the Photoluminescence test method still cannot meet the requirements of Micro LED display application.

Therefore, the efficient LED chip testing method is an important premise for realizing the Micro LED display technology.

Disclosure of Invention

The invention aims to provide a test fixture, a test method and a test system for an LED chip, so as to solve the problem that the accuracy of the traditional test method is difficult to meet the requirement.

The utility model provides a LED chip test fixture, which comprises a substrate, be equipped with the test electrode pair that the interval was arranged on the base plate, the test electrode pair includes positive test electrode and negative test electrode, and the setting of base plate one side coating of test electrode pair has with dielectric layer including the test electrode pair covers, one the test electrode pair corresponds a LED chip that awaits measuring, the positive test electrode of test electrode pair be used for with the positive capacitance coupling of the LED chip that awaits measuring, negative test electrode be used for with the negative pole capacitance coupling of the LED chip that awaits measuring, positive test electrode connects first power, the second power is connected to the negative test electrode, first power with there is the potential difference between the second power.

In one embodiment, the dielectric layer is a film with elasticity.

In one embodiment, the dielectric layer is made of polydimethylsiloxane.

In one embodiment, the positive test electrode is connected to the first power source through a first circuit and the negative test electrode is connected to the second power source through a second circuit.

In one embodiment, the substrate includes a first flexible substrate, the first circuit and the second circuit are conductive metal traces, and the first circuit and the second circuit are laid in the first flexible substrate.

In one embodiment, the substrate includes a first flexible substrate and a second flexible substrate arranged in a stack, the second flexible substrate having a stiffness less than a stiffness of the first flexible substrate, the test electrode pairs are arranged on a first surface of the second flexible substrate, and the first flexible substrate is arranged on a second surface of the second flexible substrate opposite to the first surface;

the first circuit and the second circuit are conductive metal wires, and the first circuit and the second circuit are laid in the second flexible substrate.

In one embodiment, the test electrode pairs arranged at intervals form a plurality of rows of positive test electrodes and a plurality of rows of negative test electrodes which are arranged in a staggered manner, the number of the positive test electrodes in one row is consistent with that of the negative test electrodes in one row, the minimum distance between the positive test electrodes in one adjacent row and the negative test electrodes in one adjacent row is greater than or equal to the minimum distance between the positive electrode and the negative electrode of the LED chip to be tested, and the maximum distance between the positive test electrodes in one adjacent row and the negative test electrodes in one adjacent row is less than or equal to the maximum distance between the positive electrode and the negative electrode of the LED chip to be tested.

In one embodiment, the row of positive test electrodes is connected in series to the first power supply via the first circuit, and the row of negative test electrodes is connected in series to the second power supply via the second circuit; or, the row of positive test electrodes is connected to the first circuit through the same metal line, and the row of negative test electrodes is connected to the second circuit through the same metal line.

In one embodiment, the test electrode pairs arranged at intervals form a plurality of rows of positive test electrodes and a plurality of rows of negative test electrodes which are arranged in a staggered manner, the number of the positive test electrodes in one row is consistent with that of the negative test electrodes in one row, the minimum distance between the positive test electrodes in one adjacent row and the negative test electrodes in one row is greater than or equal to the minimum distance between the positive electrode and the negative electrode of the LED chip to be tested, and the maximum distance between the positive test electrodes in one adjacent row and the negative test electrodes in one adjacent row is less than or equal to the maximum distance between the positive electrode and the negative electrode of the LED chip to be tested.

In one embodiment, the column of positive test electrodes is connected in series to the first power supply via the first circuit, and the column of negative test electrodes is connected in series to the second power supply via the second circuit; or, the column of positive test electrodes is connected to the first circuit through the same metal line, and the column of negative test electrodes is connected to the second circuit through the same metal line.

In one embodiment, the test electrode pairs arranged at intervals form a plurality of rows of positive test electrodes and a plurality of columns of negative test electrodes, the number of the positive test electrodes in a row is consistent with the number of the columns of the negative test electrodes in a column, each negative test electrode in a column of the negative test electrodes is respectively positioned between the positive test electrodes in adjacent rows, the minimum distance between the adjacent positive test electrodes and the adjacent negative test electrodes is greater than or equal to the minimum distance between the positive electrode and the negative electrode of the LED chip to be tested, and the maximum distance between the adjacent positive test electrodes and the negative test electrodes is less than or equal to the maximum distance between the positive electrode and the negative electrode of the LED chip to be tested.

In one embodiment, the row of positive test electrodes is connected in series to a first circuit, each first circuit is connected to a first power source, the column of negative test electrodes is connected in series to a second circuit, and each second circuit is connected to a second power source; alternatively, the first and second electrodes may be,

the row of positive test electrodes is connected to the first circuit through the same metal wire, each first circuit is connected to the first power supply, the row of negative test electrodes is connected to the second circuit through the same metal wire, and each second circuit is connected to the second power supply.

In one embodiment, the width of the conductive metal trace is less than or equal to 1/3 of the minimum width of the test electrode.

In one embodiment, the second flexible substrate is made of polyimide or polyethylene terephthalate.

In one embodiment, the half-plate second flexible substrate is a plastic substrate, a paper sheet, tempered glass, or a substrate made of polyethylene terephthalate.

The LED chip testing jig is characterized in that the substrate is paved with the testing electrodes, after the dielectric layer on one side of the substrate is attached to the chip film paved with the LED chips to be tested, the testing electrodes of the testing jig can be aligned with the two electrodes of the LED chips to be tested on the chip film to form capacitive coupling, and therefore the LED chips to be tested are coupled and powered to perform photoelectric characteristic testing.

This application second aspect provides a LED chip test system for to await measuring the LED chip to the chip membrane and carry out the photoelectric property test, its characterized in that, LED chip test system includes: the LED chip testing jig comprises a processor, shooting equipment and the LED chip testing jig;

the dielectric layer of the LED chip test fixture is attached to the chip film, so that the test electrode pair of the test fixture is aligned with two electrodes of an LED chip to be tested on the chip film, the shooting equipment is arranged below the chip film, the substrate of the chip film is transparent, when the LED chip to be tested on the chip film is powered on, the shooting equipment is used for shooting an image of the LED chip to be tested on the chip film when the LED chip to be tested is powered on, and the processor is used for identifying whether the LED chip to be tested emits light when the LED chip to be tested is powered on according to the shot light-emitting image.

The third aspect of the present application provides an LED chip testing method for testing an LED chip to be tested on a chip film, wherein the LED chip testing method includes:

attaching the dielectric layer in the LED chip test fixture to the chip film to enable the test electrode pair of the test fixture to be aligned with two electrodes of the LED chip to be tested on the chip film, wherein the substrate of the chip film is transparent;

turning on the first power supply and the second power supply;

and shooting the light-emitting image of the LED chip to be detected, and identifying whether the LED chip to be detected emits light when being electrified or not according to the shot light-emitting image.

In the LED chip testing system and method provided in the second and third aspects, the LED chip testing jig may provide a substrate on which a plurality of testing electrode pairs are laid, and after the dielectric layer on one side of the substrate is attached to the chip film on which the LED chips to be tested are laid, the testing electrode pairs of the testing jig may be aligned with two electrodes of the LED chips to be tested on the chip film to form effective capacitive coupling, so as to perform a photoelectric characteristic test on the power supplied to the LED chips to be tested, and thus, the LED chip testing jig may be used to perform a photoelectric characteristic test on a large number of LED chips, and has high testing efficiency and high accuracy; in addition, whether the LED chip emits light or not during power-on can be identified by collecting the light-emitting image of the LED chip to be tested, and the test process is simple and quick.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an LED chip testing fixture according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of an LED chip testing fixture according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of an LED chip testing fixture according to a third embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a first connection manner of test electrodes in the LED chip test fixture according to the embodiment of the invention;

FIG. 5 is a schematic diagram illustrating a second connection manner of test electrodes in the LED chip test fixture according to the embodiment of the invention;

FIG. 6 is a schematic diagram illustrating a third connection manner of test electrodes in the LED chip test fixture according to the embodiment of the invention;

fig. 7 is a schematic structural diagram of an LED chip testing system according to a first embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an LED chip testing system according to a second embodiment of the present invention;

fig. 9 is a schematic structural diagram of an LED chip testing system according to a third embodiment of the present invention;

FIG. 10 is a flowchart of a method for testing an LED chip according to a second embodiment of the present invention;

fig. 11 is a process diagram of manufacturing a second flexible substrate by using the manufacturing method of the LED chip test fixture according to the first embodiment of the invention;

fig. 12 is a process diagram of depositing metal according to the method for manufacturing an LED chip test fixture according to the first embodiment of the present invention;

FIG. 13 is a process diagram of depositing a dielectric layer according to the method for manufacturing an LED chip test fixture provided by the first embodiment of the present invention;

fig. 14 is a process diagram of attaching a first flexible substrate to the manufacturing method of the LED chip test fixture according to the first embodiment of the invention;

FIG. 15 is a schematic structural diagram of an LED chip testing system according to an embodiment of the present invention;

FIG. 16 is a first equivalent circuit diagram of capacitively coupled electroluminescence of an LED chip testing system according to an embodiment of the present invention;

fig. 17 is a second equivalent circuit diagram of capacitive coupling electroluminescence of the LED chip testing system according to the embodiment of the present invention;

FIG. 18 is a voltage timing diagram and a current timing diagram for a first LED electroluminescence mode driving in accordance with an embodiment of the present invention;

fig. 19 is a voltage timing diagram and a current timing diagram of a second LED electroluminescence driving mode adopted in the embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more, and "/" means "or" several "means one or more unless specifically limited otherwise.

Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of an LED chip testing fixture according to two embodiments of the present application.

In this embodiment, the LED chip testing fixture includes a substrate 10, the substrate 10 has a first surface and a second surface opposite to the first surface, the first surface of the substrate 10 is provided with testing electrode pairs 20 arranged at intervals, and one side (i.e. the first surface) of the substrate 10 where the testing electrode pairs 20 are arranged is coated with a dielectric layer 15 covering the testing electrode pairs 20, the testing electrode pairs 20 should match with the arrangement of the two

electrodes

101, 102 of the LED chip 100 to be tested on the chip film 200, so that during testing, the dielectric layer 15 is attached to the two

electrodes

101, 102 of the LED chip 100 to be tested, the testing electrode pairs 20 can form effective capacitive coupling (or electric field coupling, electrostatic coupling) with the two

electrodes

101, 102 of the LED chip 100 to be tested, it can be understood that the LED chip testing fixture is suitable for the two

electrodes

101, 102 of the LED chip 100 to be tested to be located on the exposed surfaces, such as on the top, or on both sides; the LED chip 100 may be a face-up or flip LED chip.

In one embodiment, the testing electrode pair 20 is connected to the power source through the testing circuit 11, wherein the testing electrode pair 20 includes a positive testing electrode (labeled "+") and a negative testing electrode (labeled "-"), one testing electrode pair 20 corresponds to one LED chip 100 to be tested, the positive testing electrode of the testing electrode pair 20 is used for capacitive coupling with the positive electrode 101 of the LED chip 100 to be tested, the negative testing electrode is used for capacitive coupling with the negative electrode 102 of the LED chip 100 to be tested, the positive testing electrode is connected to the first power source 31, the negative testing electrode is connected to the second power source 32, and there is an electric potential difference between the first power source 31 and the second power source 31.

Referring to fig. 1 to 6, in some embodiments, the positive test electrode and the negative test electrode are arranged at an interval in the first direction x to be adapted to the arrangement of the two

electrodes

101 and 102 of the LED chip 100 to be tested, so as to form an effective electrical contact.

When testing more than two LED chips 100 to be tested arranged in an array, the testing electrode pairs 20 on the first surface of the substrate 10 are multiple pairs, the positive testing electrodes and the negative testing electrodes are arranged at intervals in a first direction x, and the positive testing electrodes and the negative testing electrodes are respectively arranged at intervals and in parallel in a second direction y perpendicular to the first direction x. Thus, the dielectric layer 15 is relatively close to the first surface of the chip film 200 on which the LED chips 100 to be tested are laid, and the two

electrodes

101 and 102 of the LED chips 100 to be tested are aligned with a positive test electrode and a negative test electrode, respectively, so as to form effective capacitive coupling, as shown in fig. 4 to 6.

Optionally, the positive test electrode and the negative test electrode may have the same structure and a simple structure, i.e., the positive test electrode and the negative test electrode have no obvious difference in shape and structure, which is beneficial to the manufacture of the test fixture. In addition, the end surface length of the positive test electrode is equal to the end surface length of the positive electrode of the LED chip 100 to be tested, which is beneficial to the consistency of the capacitive coupling between the two

electrodes

101 and 102 of the LED chip 100 to be tested and the test electrode pair 20.

Optionally, the substrate 10 is elastic or flexible, i.e. a film with elasticity or a film with flexibility, and optionally, the substrate 10 is a film with elasticity or a film with flexibility. The substrate 10 has elasticity or flexibility, and even if the top ends of the testing electrode pairs 20 are not on the same plane, or the two

electrodes

101 and 102 of the LED chip 100 to be tested are not on the same plane, or the chip film 200 carrying the LED chip 100 to be tested is bent, the dielectric layer 15 can be ensured to be well attached to the surfaces of the two electrodes 102 of all the LED chips 100 to be tested through the deformation of the elastic/flexible substrate 10, so that the testing electrode pairs 20 and the two

electrodes

101 and 102 of the LED chip 100 to be tested are ensured to be uniformly attached to each other, the occurrence of uneven height difference is avoided, the formed capacitive coupling degrees are different from each other greatly, the electroluminescent effect is uneven, the testing effect is not ideal, and the testing is not accurate. It will be appreciated that the dielectric layer 15 should also be of uniform thickness so that the test electrode pair 20 is in uniform proximity with both

electrodes

101, 102 of the LED chip 100 to be tested.

Referring to FIG. 2, in one embodiment, the positive test electrode of the test electrode pair 20 is connected to the first power source 31 through a first circuit 111, and the negative test electrode is connected to the second power source 32 through a second circuit 112. The first circuit 111 and the second circuit 112 are laid on the conductive metal traces in the substrate 10, and are electrically connected to the positive and negative test electrodes fixed on the bottom end of the substrate 10.

In one embodiment, the substrate 10 includes a second flexible substrate 11 and a first flexible substrate 12 which are stacked, and the second flexible substrate 11 has a rigidity smaller than that of the first flexible substrate 12, the test electrode pair 20 is disposed on a first surface of the second flexible substrate 11, and the first flexible substrate 12 is disposed on a second surface of the second flexible substrate 11 opposite to the first surface; the first and

second circuits

111 and 112 are formed of a deposited metal laid in the second flexible substrate 11. The deposited metal is copper, and can also be aluminum oxide, gold, nickel and the like.

In this embodiment, the first flexible substrate 12 is a semi-flexible substrate, and the second flexible substrate 11 is a flexible substrate, and generally, the flexible substrate can be largely deformed in any form, and the semi-flexible substrate can be deformed in a small extent while maintaining original physical properties without being damaged. In the present application, since the two

electrodes

101 and 102 of the LED chip 100 to be tested may not be on the same plane, or the chip film 200 carrying the LED chip 100 to be tested has a warp, if a flexible or semi-flexible substrate is used to carry the LED chip 100 to be tested for transfer, the warp can be adapted more easily than a rigid substrate, and the dielectric layer 15 is ensured to be better attached to the surfaces of the two electrodes 102 of all the LED chips 100 to be tested.

Alternatively, the second flexible substrate 11 should be a high temperature resistant material, such as above 300 ℃, and the second flexible substrate 11 is made of Polyimide (PI) or Polyethylene terephthalate (PET). In the process of manufacturing the substrate 10, the first flexible substrate 12 is bonded to the second flexible substrate 11 in the last step, which is advantageous in that it does not need to undergo a high temperature process, so that the first flexible substrate 12 can be made of a material with low cost or other desirable characteristics, but does not need to withstand high temperature, such as plastic, leatheroid, tempered glass, and of course, can also be made of PET.

Referring to fig. 3, in another embodiment, the substrate 10 may be formed without using a second flexible substrate, and the substrate 10 includes the first flexible substrate 12, which is selected to be able to withstand a higher temperature, such as above 300 ℃, and may be made of tempered glass or PET. In this manner, the first and

second circuits

111 and 112 are to be laid in the first flexible substrate 12, and are formed of the deposited metal laid in the first flexible substrate 12.

Alternatively, the first circuit 111 and the second circuit 112 may be disposed on the substrate 10 in a cable manner.

The dielectric layer 15 is optionally a film having elasticity, and optionally the film may also be a tacky film. The dielectric layer 15 has the advantage of elasticity, which can partially absorb the height difference caused by one or more of the condition that the top ends of the test electrode pairs 20 are not on the same plane, the substrate 10 is warped, the chip film 200 carrying the LED chip 100 is warped, or the two

electrodes

101 and 102 of the LED chip 100 to be tested are not on the same plane, so that the two

electrodes

101 and 102 of the LED chip 100 to be tested are better attached to the dielectric layer 15, and the distance uniformity between the two

electrodes

101 and 102 of the LED chip 100 to be tested and the test electrode pairs 20 is better. The dielectric layer 15 is also resilient in that it is softer and more easily deformed in contact with the LED chip 100 to be tested, and is less likely to damage the chip. In one embodiment, the material of the dielectric layer 15 is Polydimethylsiloxane (PDMS).

Referring to fig. 4 to 6, three wiring diagrams of the testing electrode pair 20, the first circuit 111 and the second circuit 112 on the substrate 10 in the embodiment of the present application are respectively shown, wherein fig. 4 to 6 only take one LED chip 100 to be tested as an example to illustrate the electrical connection state between the fixture and the LED chip 100 to be tested during the measurement.

In the wiring scheme shown in fig. 4, all the positive test electrodes are connected to and to the first power supply 31 to be connected to the first voltage V1; all negative electrodes 102 are connected in communication and to the second power source 32 for receiving the second voltage V2. During measurement, a proper voltage difference is applied between the first voltage V1 and the second voltage V2, so that the LED chip 100 to be measured works, and the working state of the LED chip 100 to be measured can be observed through collecting influences.

In the wiring manner of fig. 5, the connection line between the test electrode pair 20 does not pass through the electrodes 102, so that the coupling between the electrodes 102 can be reduced, and the measurement accuracy can be improved.

Referring to fig. 4 and 5, in some embodiments, the testing electrode pairs 20 are arranged laterally, and in the testing electrode pairs 20 arranged at intervals, rows of positive testing electrodes 21 and rows of negative testing electrodes 22 are formed, and the number of the positive testing electrodes 21 is the same as that of the negative testing electrodes 22, the minimum distance between adjacent rows of positive testing electrodes 21 and negative testing electrodes 22 is greater than or equal to the minimum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested, and the maximum distance between adjacent rows of positive testing electrodes 21 and negative testing electrodes 22 is less than or equal to the maximum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested, so that the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested can be ensured to be successfully capacitively coupled.

The connection mode between each test electrode can be as follows: referring to FIG. 4, in one embodiment, a row of positive test electrodes 21 is connected in series and then connected to a first power source 31 through a first circuit 11, and a row of negative test electrodes 22 is connected in series and then connected to a second power source 32 through a second circuit 112. Referring to FIG. 5, in another embodiment, a row of positive test electrodes 21 is connected to the first circuit 111 by being connected to the same metal line 113 in parallel, and a row of negative test electrodes 22 is connected to the second circuit 112 by being connected to the same metal line 114, in the layout of FIG. 5, the metal line 113/114 between the test electrodes 20/21 of the same row does not pass through adjacent test electrodes, and the adjacent test electrodes are connected in parallel, so that the coupling between the test electrodes can be reduced, and the measurement accuracy can be improved.

In addition, in other embodiments, the test electrode pairs 20 may be arranged vertically, i.e., in a circuit layout that is rotated 90 ° clockwise or counterclockwise in fig. 4 and 5. In the test electrode pairs 20 arranged at intervals, a plurality of rows of positive test electrodes 21 and a plurality of rows of negative test electrodes 22 are formed, the number of the positive test electrodes 21 in one row is the same as that of the negative test electrodes 22 in one row, the minimum distance between the positive test electrodes 21 in one adjacent row and the negative test electrodes 22 in one row is greater than or equal to the minimum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested, and the maximum distance between the positive test electrodes 21 in one adjacent row and the negative test electrodes 22 in one row is less than or equal to the maximum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested. In this way, it can be ensured that the testing electrode pair 20 and the anode 101 and the cathode 102 of the LED chip 100 to be tested can be successfully capacitively coupled.

Accordingly, the connection between the test electrodes may be: referring to FIG. 4 (rotated 90 clockwise or counterclockwise in FIG. 4), a row of positive test electrodes 21 are connected in series and then connected to a first power source 31 through a first circuit 11, and a row of negative test electrodes 22 are connected in series and then connected to a second power source 32 through a second circuit 112. In another embodiment, referring to FIG. 5 (rotated 90 clockwise or counterclockwise in FIG. 5), a row of positive test electrodes 21 are connected to the first circuit 111 by being connected in parallel to the same metal line 113, and a row of negative test electrodes 22 are connected to the second circuit 112 by being connected to the same metal line 114. Likewise, in both routing schemes, all the LED chips 100 to be tested are simultaneously turned on and off. During measurement, a proper voltage difference is applied between the first voltage V1 and the second voltage V2, so that the LED chip 100 to be measured works, and the working state of the LED chip 100 to be measured can be observed through collecting influences.

In the related embodiments of fig. 4 and 5, the minimum distance between the adjacent row of positive test electrodes 21 and the row of negative test electrodes 22 refers to: the shortest distance between the opposite edges of the adjacent positive test electrode and the negative test electrode which are closest to each other in the two rows of test electrodes; the maximum distance between the adjacent row of positive test electrodes 21 and the row of negative test electrodes 22 refers to: the maximum distance of the edges of the two adjacent and nearest positive and negative test electrodes of the two rows of test electrodes that face away from each other. The minimum distance and the maximum distance between the anode 101 and the cathode 102 of the LED chip 100 to be tested are respectively: the shortest distance between the opposing edges of the positive electrode 101 and the negative electrode 102, and the greatest distance between the opposing edges of the positive electrode 101 and the negative electrode 102.

In other embodiments, the minimum distance between an adjacent row of positive test electrodes 21 and a row of negative test electrodes 22 may be smaller than the minimum distance between the positive electrodes 101 and the negative electrodes 102 of the LED chips 100 to be tested, while ensuring that one test electrode does not contact the electrodes 101/102 of two LED chips 100 to be tested simultaneously; alternatively, the maximum distance between the adjacent row of positive test electrodes 21 and the adjacent row of negative test electrodes 22 may be greater than the maximum distance between the positive electrodes 101 and the negative electrodes 102 of the LED chip 100 to be tested.

In the wiring scheme of fig. 4 and 5, all the positive test electrodes are connected to and to the first power supply 31 to be connected to the first voltage V1; all negative test electrodes are connected in series and connected to the second power supply 32 to receive the second voltage V2, and in both wiring modes, all the LED chips 100 to be tested are simultaneously turned on and off. During measurement, a proper potential difference is applied between the first voltage V1 and the second voltage V2 to enable the LED chip 100 to be measured to work, and the working state of the LED chip 100 to be measured can be observed by collecting images of the LED chip 100 to be measured.

Referring to fig. 6, in some embodiments, in the test electrode pairs 20 arranged at intervals, a plurality of rows of positive test electrodes 23 and a plurality of columns of negative test electrodes 24 are formed, and the number of the positive test electrodes 23 in a row is consistent with the number of the columns of the negative test electrodes 24, each negative test electrode in a column of the negative test electrodes 24 is respectively located between the positive test electrodes 23 in adjacent rows, a minimum distance between adjacent positive test electrodes and adjacent negative test electrodes is greater than or equal to a minimum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested, and a maximum distance between adjacent positive test electrodes and adjacent negative test electrodes is less than or equal to a maximum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested. In this way, it can be ensured that the testing electrode pair 20 and the anode 101 and the cathode 102 of the LED chip 100 to be tested can be successfully capacitively coupled.

The minimum distance between adjacent positive and negative test electrodes refers to: the shortest distance between two opposite edges of adjacent positive and negative test electrodes; the maximum distance between adjacent positive and negative test electrodes refers to: the maximum distance of the edges of the adjacent positive and negative test electrodes that face away from each other. The minimum distance and the maximum distance between the anode 101 and the cathode 102 of the LED chip 100 to be tested are respectively: the shortest distance between the opposing edges of the positive electrode 101 and the negative electrode 102, and the greatest distance between the opposing edges of the positive electrode 101 and the negative electrode 102.

In other embodiments, the minimum distance between adjacent positive and negative test electrodes may be less than the minimum distance between the positive 101 and negative 102 electrodes of the LED chip 100 to be tested, while ensuring that one test electrode does not contact the 101/102 electrodes of two LED chips 100 to be tested simultaneously; or, the maximum distance between the adjacent positive test electrode and the negative test electrode may be greater than the maximum distance between the positive electrode 101 and the negative electrode 102 of the LED chip 100 to be tested.

Accordingly, the connection between the test electrodes may be: referring to fig. 6, in some embodiments, a row of positive test electrodes 23 is connected to a first circuit 111 through a same metal line 115, the number of the first circuits 111 is the same as the number of rows of the positive test electrodes 23 and the number of the metal lines 115, each first circuit 11 is connected to a first power source 31, a row of negative test electrodes 24 is connected to a second circuit 112 through a same metal line 116, the number of the second circuits 112 is the same as the number of columns of the negative test electrodes 24 and the number of the metal lines 116, and each second circuit 112 is connected to a second power source 32. In another embodiment, a row of positive test electrodes 23 is connected in series and then connected to a first circuit 111, each first circuit 111 is connected to a first power source 31, a column of negative test electrodes 24 is connected in series and then connected to a second circuit 112, each second circuit 112 is connected to a second power source 32, and the connection manner between the positive test electrodes and the negative test electrodes in this embodiment can refer to fig. 4.

In the wiring scheme of fig. 6, each row of positive test electrodes 23 is connected together and all rows are connected to the first power supply 31 through separate first circuits 111, respectively, to access the first voltage V1. Each column of negative test electrodes 24 is connected together and all columns are connected to the second power supply 32 via a separate second circuit 112, respectively, for receiving a second voltage V2. Thus, row-column scanning can be realized, and the purpose of lighting a single LED chip 100 to be tested is achieved.

Referring to fig. 7 and 8, schematic structural diagrams of LED chip testing systems in two embodiments of the present application are shown. The LED chip testing system is used for testing the photoelectric characteristics of the LED chip 100 to be tested on the chip film 200, the LED chip 100 to be tested is laid on the first surface of the chip film 200, and the two

electrodes

101 and 102 of the LED chip 100 to be tested are positioned on the exposed surfaces. The substrate of the chip film 200 is transparent, which means that the light emitted from the LED chip 100 to be tested can penetrate through the substrate.

The LED chip testing system includes the LED chip testing fixture, the first photographing apparatus 300, and a processor (not shown) according to any of the embodiments.

The LED chip testing jig is used for supplying power to the LED chip 100 to be tested. During testing, the dielectric layer 15 of the LED chip testing jig is attached to the first surface of the chip film 200, so that the two

electrodes

101 and 102 of each LED chip 100 to be tested are aligned to one testing electrode pair 20 respectively; the first photographing apparatus 300 is disposed below the chip film 200, and when the LED chip 100 to be tested of the chip film 200 is powered on, the first photographing apparatus 300 is configured to photograph an image of the LED chip 100 to be tested on the chip film 200 to be tested when the LED chip 100 to be tested is lighted, and the processor is configured to identify whether the LED chip 100 to be tested is lighted when the LED chip to be tested is powered on according to the photographed image.

During measurement, a proper voltage difference is applied between the first voltage V1 provided by the first power supply 31 and the second voltage V2 of the second power supply 32, so that the LED chip 100 to be measured operates. Alternatively, the second voltage may be set to 0V, i.e., the first power supply 31 and the second power supply 32 may be positive and negative outputs of the same power supply, respectively. Referring to fig. 7, in one embodiment, the first photographing device 30 is disposed below the chip film 200 and is located between 5cm and 50cm away from the chip film 200, and preferably located right opposite to the center of the chip film 200, so as to be able to see all the LED chips 100 to be measured. Thus, the LED chip 100 to be tested emits light and can be captured by the first camera 300 through the chip film 200, and then the position of the dead pixel of the LED chip 100 to be tested can be determined according to the captured image. Preferably, the first photographing apparatus 300 is located at a middle position (e.g., right below) below the chip film 200, and further, the specific placement position of the photographing apparatus 300 may be determined according to configuration parameters of the first photographing apparatus 300, which may include parameters of a photographing angle of view, a field of view, a lens, and the like.

Referring to fig. 8, in another embodiment, the first photographing apparatus 300 may be located above the LED chip testing jig and between 5cm and 50cm from the substrate 10. In this embodiment, the substrate 10 is transparent, and the transparency in this embodiment means that the light emitted from the LED chip 100 to be tested can penetrate through the substrate.

Referring to fig. 9, in an embodiment, the LED chip testing system further includes a second photographing apparatus 400.

The second photographing apparatus 400 is located above the substrate 10 or below the chip film 200, so that the substrate 10 or the chip film 200 can penetrate through visible light, the second photographing apparatus 400 is configured to collect alignment images of the two

electrodes

101 and 102 of each LED chip 100 to be tested and the test electrode pair 20, respectively, and the alignment images are configured to identify whether the two

electrodes

101 and 102 of each LED chip 100 to be tested are aligned with the test electrode pair 20, respectively, so as to improve power supply efficiency and further improve test accuracy.

It is understood that the first photographing apparatus 300 and the second photographing apparatus 400 may be the same or separate apparatuses, and two different cameras are selected more specifically; respectively, may be disposed on the same side of the substrate 10 or the chip film 200, respectively, or on different sides.

Referring to fig. 7 to 10, an embodiment of the present application further provides an LED chip testing method, for performing a photoelectric characteristic test on an LED chip 100 to be tested on a chip film 200, where the LED chip is laid on a first surface of the chip film 200, and two

electrodes

101 and 102 of the LED chip 100 to be tested are located on exposed surfaces, and the LED chip testing method includes the following steps:

step S81, the dielectric layer 15 in the LED chip test fixture according to any one of the above embodiments is attached to the first surface of the chip film 200, so that the two

electrodes

101 and 102 of the LED chip 100 to be tested are aligned with a positive test electrode and a negative test electrode, respectively, and the substrate of the chip film 200 is transparent, where the transparency means that light emitted by the LED chip 100 to be tested can penetrate through the substrate.

Step S82, turning on the first power supply 31 and the second power supply 32 to supply the first voltage V1 and the second voltage V2 to the first circuit 111 and the second circuit 112, respectively;

in step S83, a light emission image of the LED chip 100 to be tested is photographed, and whether the LED chip 200 to be tested emits light when powered on is identified from the photographed light emission image.

In one embodiment, before step S82, the method further includes:

the alignment images of the two

electrodes

101 and 102 of the LED chip 100 to be tested and a positive test electrode and a negative test electrode are collected respectively, and whether the two

electrodes

101 and 102 of the LED chip 100 to be tested are aligned with the positive test electrode and the negative test electrode respectively is identified according to the alignment images, so that the power supply efficiency is improved, and the test accuracy is improved.

It can be understood that the luminescent image and the alignment image may be captured by the same image capturing device, or captured by different image capturing devices, and two different cameras may be selected more specifically.

Optionally, when the LED chip is tested, the chip film 200 should be placed on a carrier board, and when the shooting device is disposed on one side of the chip film 200, the carrier board should be of a transparent structure, where the transparency means that light emitted by the LED chip 100 to be tested can penetrate through the carrier board.

Therefore, the LED chip test fixture can provide the substrate 10 paved with the test electrode pairs 20, and after the dielectric layer 15 of the substrate 10 is attached to the chip film 200 paved with the LED chips arranged in an array, the test electrode pairs of the test fixture can be effectively and electrically coupled with the two

electrodes

101 and 102 of the LED chip 100 to be tested on the chip film, so that the LED chip 100 to be tested can be subjected to photoelectric characteristic test. In addition, by collecting the light-emitting image of the LED chip, whether the LED chip 100 to be tested emits light or not can be judged, and the test process is simple and quick.

Referring to fig. 11 to 14, an embodiment of the present application further provides a method for manufacturing an LED chip test fixture, including:

referring to fig. 11, a second flexible substrate 11 is prepared, and the surface of the second flexible substrate 11 is cleaned to ensure that the surface has no foreign particles.

Referring to fig. 12, a metal is deposited on the second flexible substrate 11 to form a testing electrode pair 20, a first circuit 111 and a second circuit 112, please refer to fig. 4-6.

It is noted that in the layout, it is considered that the transmission resistance of the deposited metal cannot be too small, and alternatively, the thickness of the deposited metal should not be lower than 2 um. In addition, the parasitic capacitance cannot be too large, which may cause errors in measurement, and optionally, the wire width (width of deposited metal) of the first circuit 111 and the second circuit 112 should not exceed 1/3 of the width (based on the minimum width) of the deposited metal of the test electrode; the thickness of the deposited metal should not exceed 3 um; the distance between the first and

second circuits

111, 112 and the test electrode pair 20 should be as large as possible.

In a third step, referring to fig. 13, a uniform dielectric layer 15 is further deposited on the deposited metal. The dielectric layer 15 should completely cover the deposited metal and have a flat upper surface. The thickness of the dielectric layer 15 minus the height of the test electrodes is the plate spacing of the equivalent capacitance between the electrodes of the LED chip 100 to be tested and the test electrodes.

In a fourth step, referring to fig. 14, the first flexible substrate 12 is bonded to the back surface of the second flexible substrate 11 by using glue or thermal fusion.

The following describes a specific method of electroluminescence of the LED chip and its principle.

Some dimensions are marked in fig. 15, wherein

electrodes

1, 2, 3, 4 represent a positive test electrode in the test fixture, a negative test electrode in the test fixture, a positive electrode of the (to be) LED chip, a negative electrode of the LED chip, respectively. Setting each electrode at a vertical positionThe length in the direction perpendicular to the paper surface is e. The following analysis simply considers length a1= length a3= a13, length a2= length a4= a24, height b1= height b2= b12, height b3= height b4= b 34. With C_mnThe method represents the equivalent capacitance between the electrode m and the electrode n, and specifically comprises the following steps:

，

，

，

；

wherein

In order to have a dielectric constant in a vacuum,

is the dielectric relative permittivity. Since the distance between the electrode 1 and the electrode 4, and between the electrode 2 and the electrode 3 are long, and the equivalent area is small, C is considered to be approximated to C₁₄=C₂₃=0。

In one embodiment, the LED chip has a size of 200um x 400 um. The four electrodes are all 100um x 100um, dx =100um, dy =2um, the thickness of the test electrode is b12=3um, the thickness of the chip electrode is b34=0.5um,

(silica).

In this example, C₁₃=C₂₄=1.7e-13F；C₁₂=1.0e-16F；C₃₄=1.7e-17F；

Therefore, the equivalent circuit is as shown in fig. 16. Generally (in most cases), (a 1, a2, a3, a4, e)>>(b 1, b2, b3, b 4), and dx>>dy, thusC₁₃，C₂₄）>>（C₁₂，C₃₄) Thus, the circuit diagram can be simplified to fig. 17, and the current and voltage of this circuit satisfy the relationship:

；

thus:

；

during the measurement, it is desirable that the LED voltage and current stabilize to the typical voltage and current values in display applications, namely:

，

；

and V2 can be fixed to the reference voltage, V2= 0. Thus:

；

integration yields:

；

this relationship is shown in the timing chart (a) of fig. 18 or the period t0 of the timing chart (a) of fig. 19, i.e., the initial voltage is equal to the LED operation voltage V₀Then V1 increases linearly with time, the rate of increase is determined by the capacitance and the LED operating current I_LEDAnd (4) jointly determining. For the duration of this process, t0, the LED is illuminated and the camera can collect light.

In one embodiment, V_LED=2.7V，I_LED=5 uA. In one embodiment (described above), the capacitance value is brought upThe relationship described above yields:

；

fig. 18 shows a timing diagram of voltage (a) and a corresponding timing diagram of LED current (b) used in this patent. Wherein V_RFor the reverse voltage of the LED chip 100 to be tested, the LED chip 100 to be tested can be at the reverse voltage V_RThe lower is not broken down.

During time t0, a forward voltage is applied. The forward voltage increases linearly with time until it reaches V_RUntil now. Entering the t1 time period thereafter, reducing V1 to 0 and increasing linearly negatively with time, ensuring that the LED reverse current is at a constant value I_R。I_RKeeping the reverse current at I for the maximum current capable of being borne in the reverse direction_RMaximum discharge efficiency can be achieved. The change in reverse voltage over time can be described as:

；

when the reverse voltage reaches V_RAt this time, the charge on the capacitor is fully discharged, and then the second cycle is entered.

In one embodiment, V_R=33V，I_R=2nA。

In one embodiment, the relationship of the inverted voltage of V1 is:

；

in this embodiment, the total time of the forward voltage is:

；

the total time of the reverse voltage is:

；

it is worth noting thatThe integration time cannot be too long, otherwise the potential gradient would exceed the critical electric field of the dielectric layer leading to breakdown. In this embodiment, the breakdown field of the dielectric layer is

The safe voltage does not exceed 1200V, and the integration time cannot exceed 20 us.

As shown in fig. 18, the process may be repeated multiple times in a loop to increase the cumulative intensity of the signals collected by the camera. In one embodiment, the preferred range of total measurement time is 1s-60 s.

Fig. 19 shows another voltage timing diagram (a) and a corresponding LED current timing diagram (b) adopted in the present patent. The difference from fig. 18 is that the reverse voltage is fixed to 0. This has the advantage that the supply circuit can be simplified without the need to provide a reverse voltage. This is done at the cost of a decreasing reverse current intensity over time, requiring a longer discharge time and further resulting in a longer total measurement time.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. The utility model provides a LED chip test fixture, its characterized in that, includes the base plate, be equipped with the test electrode pair of arranging at interval on the base plate, the test electrode pair includes positive test electrode and negative test electrode, and the setting of base plate one side coating of test electrode pair has with dielectric layer including the test electrode pair covers, one the test electrode pair corresponds a LED chip that awaits measuring, the positive test electrode of test electrode pair be used for with the positive capacitance coupling of the LED chip that awaits measuring, negative test electrode be used for with the negative pole capacitance coupling of the LED chip that awaits measuring, positive test electrode connects first power, negative test electrode connects the second power, first power with there is the potential difference between the second power.

2. The LED chip testing fixture of claim 1, wherein the dielectric layer is a film with elasticity.

3. The LED chip test fixture of claim 1 or 2, wherein the dielectric layer is made of polydimethylsiloxane.

4. The LED chip testing fixture of claim 1, wherein the positive testing electrode is connected to the first power source through a first circuit, and the negative testing electrode is connected to the second power source through a second circuit.

5. The LED chip testing fixture of claim 4, wherein the substrate comprises a first flexible substrate, the first and second circuits are conductive metal traces, and the first and second circuits are laid in the first flexible substrate.

6. The LED chip testing jig according to claim 4, wherein the substrate includes a first flexible substrate and a second flexible substrate which are stacked, the second flexible substrate has a rigidity smaller than that of the first flexible substrate, the test electrode pair is disposed on a first surface of the second flexible substrate, and the first flexible substrate is disposed on a second surface of the second flexible substrate opposite to the first surface;

7. The LED chip testing fixture of claim 4, 5 or 6, wherein the spaced test electrode pairs form rows of positive test electrodes and rows of negative test electrodes which are staggered, the number of the positive test electrodes in a row is the same as that of the negative test electrodes in a row, the minimum distance between the positive test electrodes in an adjacent row and the negative test electrodes in an adjacent row is greater than or equal to the minimum distance between the positive electrode and the negative electrode of the LED chip to be tested, and the maximum distance between the positive test electrodes in an adjacent row and the negative test electrodes in an adjacent row is less than or equal to the maximum distance between the positive electrode and the negative electrode of the LED chip to be tested.

8. The LED chip testing fixture of claim 7, wherein said row of positive test electrodes are connected in series and then connected to said first power supply through said first circuit, and said row of negative test electrodes are connected in series and then connected to said second power supply through said second circuit; or, the row of positive test electrodes is connected to the first circuit through the same metal line, and the row of negative test electrodes is connected to the second circuit through the same metal line.

9. The LED chip testing fixture of claim 4, 5 or 6, wherein the spaced test electrode pairs form rows of positive test electrodes and rows of negative test electrodes, the number of the positive test electrodes in a row is equal to the number of the negative test electrodes in a row, the minimum distance between the positive test electrodes in an adjacent row and the negative test electrodes in an adjacent row is greater than or equal to the minimum distance between the positive electrodes and the negative electrodes of the LED chips to be tested, and the maximum distance between the positive test electrodes in an adjacent row and the negative test electrodes in an adjacent row is less than or equal to the maximum distance between the positive electrodes and the negative electrodes of the LED chips to be tested.

10. The LED chip testing fixture of claim 9, wherein said row of positive test electrodes are connected in series and then connected to said first power supply via said first circuit, and said row of negative test electrodes are connected in series and then connected to said second power supply via said second circuit; or, the column of positive test electrodes is connected to the first circuit through the same metal line, and the column of negative test electrodes is connected to the second circuit through the same metal line.

11. The LED chip testing jig according to claim 4, 5 or 6, wherein the testing electrodes arranged at intervals are aligned to form a plurality of rows of positive testing electrodes and a plurality of columns of negative testing electrodes, the number of the positive testing electrodes in a row is the same as the number of the columns of the negative testing electrodes in a column, each negative testing electrode in a column of the negative testing electrodes is respectively located between the positive testing electrodes in adjacent rows, the minimum distance between the adjacent positive testing electrodes and the adjacent negative testing electrodes is greater than or equal to the minimum distance between the positive electrodes and the negative electrodes of the LED chips to be tested, and the maximum distance between the adjacent positive testing electrodes and the negative testing electrodes is less than or equal to the maximum distance between the positive electrodes and the negative electrodes of the LED chips to be tested.

12. The LED chip testing fixture of claim 11, wherein said row of positive test electrodes are connected in series and then connected to one of said first circuits, each of said first circuits is connected to one of said first power supplies, said column of negative test electrodes are connected in series and then connected to one of said second circuits, each of said second circuits is connected to one of said second power supplies; alternatively, the first and second electrodes may be,

13. The LED chip testing fixture of claim 5 or 6, wherein the width of the conductive metal trace is less than or equal to 1/3 of the minimum width of the test electrode.

14. The LED chip testing fixture of claim 6, wherein the second flexible substrate is made of polyimide or polyethylene terephthalate.

15. The LED chip testing jig according to claim 5 or 6, wherein the first flexible substrate is a plastic substrate, a paper sheet, tempered glass, or a substrate made of polyethylene terephthalate.

16. An LED chip test system for testing photoelectric characteristics of an LED chip to be tested on a chip film, the LED chip test system comprising: the processor, the shooting equipment and the LED chip test fixture of any one of claims 1 to 15;

the dielectric layer of the LED chip test fixture is attached to the chip film, so that a test electrode pair of the test fixture is aligned with two electrodes of an LED chip to be tested on the chip film, the shooting equipment is arranged below the chip film, a substrate of the chip film is transparent, when the LED chip to be tested on the chip film is electrified, the shooting equipment is used for shooting an image when the LED chip to be tested on the chip film emits light, and the processor is used for identifying whether the LED chip to be tested emits light when the LED chip to be tested is electrified according to the shot light-emitting image.

17. An LED chip testing method is used for testing an LED chip to be tested on a chip film, and is characterized by comprising the following steps:

attaching the dielectric layer of the LED chip testing jig according to any one of claims 1 to 15 to the chip film such that the testing electrode pair of the testing jig is aligned with two electrodes of the LED chip to be tested on the chip film, the substrate of the chip film being transparent;

turning on the first power supply and the second power supply;

and shooting a luminous image of the LED chip to be detected, and identifying whether the LED chip to be detected emits light when being electrified or not according to the shot luminous image.