JP2003323416A - Microcomputer, and bus control device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform the ROM access of an OSD circuit corresponding to the amount of display data. <P>SOLUTION: A wait signal generating circuit 400 generates a wait signal WS wherein a first period of H-level and a second period of L-level are alternately repeated, on the basis of display control data DCS from a RAM 104. The wait signal generating circuit 400 elongates the first period of the wait signal WS in accordance with the increase of the display data amount. A bus switching circuit 103 connects address bus AB1-data bus DB1-control bus CB1 and address bus AB3-data bus DB3-control bus CB3, when the wait signal WS is in the H-level. On the other hand, the address bus AB1-data bus DB1-control bus CB1 and the address bus AB2-data bus DB2-control bus CB2 are connected, when the wait signal SW is in the L-level. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, a bus control device and a bus control method. More specifically, the present invention relates to a microcomputer having an OSD (On Screen Display) circuit, a bus control device and a control method when a CPU and an OSD circuit share the same ROM.

[0002]

2. Description of the Related Art AV equipment such as a television and a video deck is equipped with a microcomputer having an OSD circuit. As a result, various information such as channels and volume is displayed on-screen on a display such as a cathode ray tube or a liquid crystal display device.

Some microcomputers incorporating an OSD circuit share the same ROM with the CPU and the OSD circuit. For example, Japanese Patent Laid-Open No. 11-102352.
It is disclosed in Japanese Patent Laid-Open No. 11-134291. In such a microcomputer, CP
The bus is controlled so that the U and the OSD circuit can alternately access the ROM at a one-to-one ratio, and the instruction data read by the CPU and the display data read by the OSD circuit are performed in time division.

[0004]

[Patent Document 1] Japanese Patent Laid-Open No. 11-102352

[Patent Document 2] JP-A-11-134291

[0005]

In the above microcomputer, when the OSD circuit needs to access the ROM, the OSD circuit and the CPU must alternately access the ROM at a ratio of 1: 1. . Therefore, when the number of characters to be displayed or the number of colors of characters increases and the amount of display data read from the ROM to the OSD circuit increases, the OSD circuit may not be able to access the ROM sufficiently.

[0006]

According to one aspect of the present invention, a microcomputer is a C
A PU, a ROM, an on-screen display circuit (hereinafter referred to as an OSD circuit), a wait signal generation circuit, and a bus switching circuit are provided. The ROM stores a program to be executed by the CPU and display data to be on-screen displayed on the display device. The OSD circuit reads the display data stored in the ROM and outputs it to the display device. The weight signal generation circuit generates a weight signal that alternately repeats the first level in the first period and the second level in the second period. The weight signal generation circuit is a ROM
The length of the first period is determined according to the amount of display data read by the OSD circuit. The bus switching circuit forms a bus between the OSD circuit and the ROM when the wait signal is at the first level, and forms a bus between the CPU and the ROM when the wait signal is at the second level.

In the above microcomputer, the CP and the first period in which the bus is formed between the OSD circuit and the ROM.
The second period in which the bus is formed between U and the ROM is alternately repeated. As a result, RO by the OSD circuit
The reading of the display data from M and the reading of the instruction data from the ROM by the CPU are performed in a time division manner. First
The length of the period is determined according to the amount of display data read from the ROM to the OSD circuit. For example, ROM
When the amount of display data read by the OSD circuit is relatively large, the first period is lengthened accordingly. As a result, even if the amount of display data to be read from the ROM to the OSD circuit increases, the OSD circuit can sufficiently access the ROM.

Preferably, the microcomputer further comprises a first bus, a second bust and a third bus. The first bus is provided between the ROM and the bus switching circuit. The second bus is provided between the CPU and the bus switching circuit. The third bus is provided between the OSD circuit and the bus switching circuit. The bus switching circuit connects the first bus and the third bus when the wait signal is at the first level. As a result, a bus is formed between the OSD circuit and the ROM. On the other hand, the bus switching circuit connects the first bus and the second bus when the wait signal is at the second level. As a result, a bus is formed between the CPU and the ROM.

Preferably, the weight signal generating circuit determines the length of the first period according to the number of characters to be displayed on-screen on the display device.

As the number of characters to be displayed on-screen on the display device increases, the amount of display data to be read from the ROM to the OSD circuit also increases. In the above microcomputer, the length of the first period is determined according to the number of characters to be displayed on-screen on the display device. For example, when the number of characters to be displayed on-screen on the display device is relatively large, the first period is lengthened accordingly.

Preferably, the weight signal generation circuit determines the length of the first period according to the number of colors of characters to be on-screen displayed on the display device.

As the number of colors of characters to be displayed on-screen on the display device increases, the amount of display data to be read from the ROM to the OSD circuit also increases. Here, the number of character colors indicates the number of colors that can be selected. In the above microcomputer, the first period is determined according to the number of colors of characters to be displayed on-screen on the display device. For example, when the number of colors of characters to be displayed on-screen on the display device is relatively large, the first period is lengthened accordingly.

According to another aspect of the present invention, a bus control device is a bus control device when a CPU and an OSD circuit share the same ROM, and includes a wait signal generation circuit and a bus switching circuit. Equipped with. ROM is
A program to be executed by the CPU and display data to be on-screen displayed on the display device are stored. The OSD circuit reads the display data stored in the ROM and outputs it to the display device. The weight signal generation circuit generates a weight signal that alternately repeats the first level in the first period and the second level in the second period. The weight signal generation circuit determines the length of the first period according to the amount of display data read from the ROM to the OSD circuit. The bus switching circuit forms a bus between the OSD circuit and the ROM when the wait signal is at the first level, and forms a bus between the CPU and the ROM when the wait signal is at the second level.

Preferably, the weight signal generating circuit determines the length of the first period according to the number of characters to be displayed on-screen on the display device.

Preferably, the weight signal generating circuit determines the length of the first period according to the number of colors of characters to be displayed on-screen on the display device.

According to yet another aspect of the present invention, in a bus control method, a CPU and an OSD circuit are the same R.
This is a bus control method in the case of sharing an OM. R
The OM stores a program to be executed by the CPU and display data to be on-screen displayed on the display device. OS
The D circuit reads the display data stored in the ROM and outputs it to the display device. In the above bus control method, the first process and the second process are alternately performed. In the first process, a bus is formed between the OSD circuit and the ROM for the first period. In the second processing, a bus is formed between the CPU and the ROM during the second period. The length of the first period is determined according to the amount of display data read from the ROM to the OSD circuit.

Preferably, the length of the first period is determined according to the number of characters to be on-screen displayed on the display device.

Preferably, the length of the first period is determined according to the number of colors of characters to be on-screen displayed on the display device.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

(First Embodiment) <Structure of Microcomputer> FIG. 1 shows the structure of a microcomputer according to the first embodiment. This microcomputer includes a CPU 101 and an OSD circuit 102.
, Bus switching circuit 103, RAM 104, ROM 1
05, address buses AB1 to AB3, and data bus D
B1 to DB3 and control buses CB1 to CB3 are provided. The microcomputer shown in FIG. 1 has an OSD circuit 102 built-in, and can be
Installed in V equipment. Further, in this microcomputer, the CPU 101 and the OSD circuit 102 are the same RO.
It shares M105.

The ROM 105 has a program (command data) to be executed by the CPU 101 and a display device (not shown).
Display data (for example, character font data) to be displayed on-screen is stored in.

Display control data is stored in the RAM 104. The display control data mentioned here is additional information such as the type of character to be displayed on-screen (for example, a character code), the color of the character, the background color, whether or not to blink.

Address bus AB1 data bus DB1
The control bus CB1 is arranged between the ROM 105 and the bus switching circuit 103. An address is given from the bus switching circuit 103 to the ROM 105 via the address bus AB1. Data is exchanged between the ROM 105 and the bus switching circuit 103 via the data bus DB1. Bus switching circuit 10 via control bus CB1
A control signal is supplied from 3 to the ROM 105.

Address bus AB2, data bus DB2,
The control bus CB2 includes a bus switching circuit 103 and a CP.
It is placed between U101. An address is given from the CPU 101 to the bus switching circuit 103 via the address bus AB2. Data is exchanged between the CPU 101 and the bus switching circuit 103 via the data bus DB2. A control signal is applied from the CPU 101 to the bus switching circuit 103 via the control bus CB2.

Address bus AB3, data bus DB3,
The control bus CB3 includes a bus switching circuit 103 and an OS.
It is arranged between the D circuit 102. Address bus AB3
An address is given from the OSD circuit 102 to the bus switching circuit 103 via the. OSD via data bus DB3
Data is exchanged between the circuit 102 and the bus switching circuit 103. OS via control bus CB3
A control signal is applied from the D circuit 102 to the bus switching circuit 103.

The OSD circuit 102 reads the display data from the ROM 105 based on the display control data DCS from the RAM 104. The OSD circuit 102 is the ROM 105
Generate an OSD display signal based on the display data read from the display control data DCS from the RAM 104,
Output to a display device (not shown). As a result, various information such as channels and volume is displayed on-screen on a display (display device) such as a cathode ray tube or a liquid crystal display device.

The OSD circuit 102 includes a wait signal generation circuit 400. The wait signal generation circuit 400 outputs the wait signal WS which alternately repeats the H level (logical high level) of the first period and the L level (logical low level) of the second period based on the display control data DCS from the RAM 104. To generate.

The bus switching circuit 103 has a wait signal WS.
Is at H level Address bus AB1 and data bus DB
1. Connect the control bus CB1 to the address bus AB3, the data bus DB3, and the control bus CB3. As a result, a bus is formed between the OSD circuit 102 and the ROM 105. On the other hand, the bus switching circuit 103
Address bus AB1 when wait signal WS is at L level
Data bus DB1, control bus CB1 and address bus AB2, data bus DB2, control bus C
Connect with B2. As a result, the CPU 101 and the ROM
A bus is formed with 105.

<Bus Control> Next, bus control in the microcomputer configured as described above will be described with reference to FIG.

First, before the OSD circuit 102 accesses the ROM 105, the display control data D is read from the RAM 104.
CS is read (ST201).

The wait signal generation circuit 400 in the OSD circuit 102 generates a wait signal WS based on the display control data DCS (ST202) and outputs it to the CPU 101 and the bus switching circuit 103.

When the wait signal WS is at H level, CP
The U 101 sets the read enable signal (control signal) to the H level (inactive) to invalidate the data reading from the ROM 105. In this way, the CPU 101 to the ROM 1
The access to 05 is stopped and the CPU 101 is put in the access waiting state. Further, the bus switching circuit 103 includes an address bus AB1, a data bus DB1, a control bus CB1.
The address bus AB3, the data bus DB3, and the control bus CB3 are connected to each other. As a result, the OSD circuit 1
02, an address and a read enable signal (control signal) are given to the ROM 105 (ST203, ST2).
04, ST205). The display data stored at the given address is read from the ROM 105 to the data bus DB1. The read data is output to the OSD circuit 102 via the bus switching circuit 103 and the data bus DB3 (ST206).

On the other hand, when the wait signal WS is at L level, the OSD circuit 102 sets the read enable signal (control signal) to H level (inactive) to invalidate the data reading from the ROM 105. In this way, the OSD circuit 1
The access from 02 to the ROM 105 is stopped and the OSD circuit 102 is placed in the access waiting state. Further, the bus switching circuit 103 connects the address bus AB1, the data bus DB1, the control bus CB1, the address bus AB2, the data bus DB2, and the control bus CB2. As a result, the CPU 101 gives the address and the read enable signal (control signal) to the ROM 105 (S
T203, ST207, ST208). The instruction data stored at the given address is read from the ROM 105 to the data bus DB1. The read data is sent to the CPU via the bus switching circuit 103 and the data bus DB2.
It is output to 101 (ST209).

FIG. 3 shows a timing chart in the above bus control. Referring to FIG. 3, when wait signal WS is at H level, access from CPU 101 to ROM 105 is stopped, CPU 101 enters an access waiting state, and the address from OSD circuit 102 is applied to ROM 105 as a selected address. The ROM data stored at this selected address is output to the OSD circuit 102 via the data buses DB1 and DB3.

On the other hand, when the wait signal WS is at L level, the ROM access of the OSD circuit 102 is stopped and the OSD is stopped.
The circuit 102 enters an access waiting state, and the address from the CPU 101 is given to the ROM 105 as a selection address. The ROM data stored at this selected address is output to the CPU 101 via the data buses DB1 and DB2.

<Structure of Wait Signal Generating Circuit 400> FIG. 4 shows the internal structure of the wait signal generating circuit 400. The wait signal generation circuit 400 includes a counter circuit 401,
And an output circuit 402. The counter circuit 401 counts the number of characters to be displayed on-screen (the number of displayed characters). The output circuit 402 outputs the wait signal WS based on the count value CNT output from the counter circuit 401.
To generate.

<Operation of Weight Signal Generating Circuit 400> Next, the weight signal generating circuit 40 configured as described above.
The operation of 0 will be described.

First, the display control data DCS stored in the RAM 104 is loaded into the counter circuit 401. R
The AM 104 stores one display control data DCS for each character to be displayed on-screen.

Next, the counter circuit 401 counts the number of times the display control data DCS is taken in for a predetermined period (for example, for one line), and outputs the count value CNT as the number of display characters to the output circuit 402.

Next, the output circuit 402 outputs the wait signal WS.
Is the count value CNT
Based on. The output circuit 402 displays the count value C
The larger the NT is, the longer the first period is determined. Here, the period of two cycles of the system clock is set as a reference unit T, and the length of the first period is set to (CNT × T). On the other hand, the length of the second period is set to two cycles of the system clock. The length of the second period is the count value CNT.
It is constant regardless of. The output circuit 402 outputs to the CPU 101 and the bus switching circuit 103 a wait signal WS that alternately repeats the H level during the first period and the L level during the second period.

FIG. 5 shows an example of the timing of generating the wait signal WS. In FIG. 5, first, “ABCD
The five characters "E" shall be displayed on-screen.
RAM 104 has one display control data DC for each character.
S is stored, and when "ABCDE" is displayed, the display control data DCS is output 5 times. The count value CNT of the counter circuit 401 which takes in the display control data DCS becomes 5. Therefore, the output circuit 402 is
The period length of the system clock is 10 cycles (= 5 ×
2), the length of the second period is set to two cycles of the system clock.

Next, one character "O" is displayed on the screen. When displaying "O", the display control data DCS is output once. Display control data DC
The count value CNT of the counter circuit 401 that takes in S
Is 1. Therefore, the output circuit 402 determines that the length of the first period is two cycles (= 1 × 2) of the system clock and the second period.
The period is defined as 2 cycles of the system clock.

Displaying five characters "ABCDE" requires a larger amount of display data than displaying one character "O". However, since the length of the first period of the wait signal WS is longer when displaying five characters of "ABCDE" than when displaying one character of "O", the display data is displayed to the OSD circuit 102 by that amount. Can be captured.

<Effect> As described above, according to the first embodiment, the ratio of the ROM access time of the CPU 101 and the OSD circuit 102 is changed by changing the length of the first period in which the wait signal WS is at the H level. Can be changed. As a result, the amount of display data to be read out to the OSD circuit 102 increases due to an increase in the number of characters to be displayed on-screen, and sufficient ROM access cannot be performed.
The first period is lengthened according to the counted number of display characters to stop the access from the CPU 101 to the ROM 105, and
The access from the SD circuit 102 to the ROM 105 can be made dense. As a result, the OSD circuit 102 can efficiently perform the ROM access with respect to the display data amount.

Although the period of two cycles of the system clock is used as the reference unit T here, the length of the reference unit T is not limited to this. For example, the period of one cycle of the system clock may be used as the reference unit T. Further, although the length of the second period is two cycles of the system clock, the length of the second period is not limited to this. For example, the period of one cycle of the system clock may be the length of the second period.

(Second Embodiment) A microcomputer according to the second embodiment includes a wait signal generation circuit 600 shown in FIG. 6 instead of the wait signal generation circuit 400 shown in FIG. Other configurations are the same as those in the first embodiment.

<Internal Configuration of Weight Signal Generating Circuit 600> As shown in FIG.
It includes a register 601 and an output circuit 602. In the register 601, the number of colors of characters to be displayed on-screen (the number of colors of displayed characters) is set. Here, the number of colors of displayed characters means the number of colors of characters that can be selected. Output circuit 6
Reference numeral 02 generates a weight signal WS based on the value NB of the number of colors of display characters set in the register 601.

<Operation of Weight Signal Generation Circuit 600> Next, the weight signal generation circuit 60 configured as described above.
The operation of 0 will be described.

First, the number of colors of displayed characters is set in the register 601.

Next, the output circuit 602 outputs the wait signal W.
The length of the first period in which S becomes H level is set to the register 60.
It is determined based on the color number NB of the display character set to 1. The output circuit 602 determines that the length of the first period becomes longer as the number of colors of displayed characters NB increases. Here, the period of two cycles of the system clock is set as a reference unit T, and the length of the first period is set to (NB × T). On the other hand, the length of the second period is set to two cycles of the system clock.
The length of the second period is constant regardless of the number of colors NB.
Then, the output circuit 602 outputs the H level in the first period and the second level.
Wait signal WS that alternately repeats the L level during the period
Is output to the CPU 101 and the bus switching circuit 103.

FIG. 7 shows an example of the timing for generating the wait signal. In FIG. 7, first, it is assumed that the character “A” having two types of colors is displayed. The amount of display data is double that in the case where the number of colors is one. The color value NB set in the register 601 is 2. Therefore, the output circuit 602 determines the length of the first period as 4 cycles (= 2 × 2) of the system clock and the length of the second period as 2 cycles of the system clock.

Next, it is assumed that the character "O" having four types of colors is displayed. The amount of display data is four times that in the case where the number of colors is one. The color numerical value NB set in the register 601 is 4. Therefore, the output circuit 602 is
The length of the period is 8 cycles of the system clock (= 4 ×
2), the length of the second period is set to two cycles of the system clock.

Displaying a character "O" having four types of colors requires a larger amount of display data than displaying a character "A" having two types of colors. However, since the first period of the wait signal WS is longer when displaying the character “O” having four kinds of colors than when displaying the character “A” having two kinds of colors, the OSD circuit is correspondingly longer. Display data can be captured in 102.

<Effect> As described above, according to the second embodiment, the display data amount to be read out to the OSD circuit 102 increases due to the number of colors of display characters, so that sufficient ROM access cannot be performed. The first period is lengthened by the number of character colors to stop the access from the CPU 101 to the ROM 105, and the OSD circuit 102 causes the ROM 105 to access.
Access to can be tight. As a result, the OS
The D circuit 102 is a ROM for the display data amount efficiently.
Can access.

Although the period of two cycles of the system clock is used as the reference unit T here, the length of the reference unit T is not limited to this. For example, the period of one cycle of the system clock may be used as the reference unit T. Further, although the length of the second period is two cycles of the system clock, the length of the second period is not limited to this. For example, the period of one cycle of the system clock may be the length of the second period.

Further, by combining the weight signal generation circuit 600 according to the second embodiment and the weight signal generation circuit 400 according to the first embodiment, the weight signal WS in consideration of both the number of display characters and the number of colors of display characters. It is also possible to generate

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining bus control in the microcomputer shown in FIG.

FIG. 3 is a timing chart for explaining bus control in the microcomputer shown in FIG.

FIG. 4 is a block diagram showing an internal configuration of a wait signal generation circuit shown in FIG.

FIG. 5 is a diagram showing an example of timing for generating a wait signal.

FIG. 6 is a block diagram showing an internal configuration of a wait signal generation circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an example of timing for generating a wait signal.

[Explanation of symbols]

101 CPU, 105 ROM, 102 OSD circuit, 400, 600 wait signal generation circuit, 103
Bus switching circuit, WS wait signal.

Claims (10)

[Claims] 1. A CPU, a ROM for storing a program to be executed by the CPU and display data to be on-screen displayed on a display device, and display data stored in the ROM for output to the display device. On-screen display (OS
D) a circuit, a weight signal generation circuit that generates a weight signal that alternately repeats the first level of the first period and the second level of the second period, and when the weight signal is at the first level A bus switching circuit which forms a bus between the OSD circuit and the ROM, and which forms a bus between the CPU and the ROM when the wait signal is at a second level. The generation circuit determines the length of the first period according to the amount of display data read from the ROM to the OSD circuit. 2. A first circuit provided between the ROM and the bus switching circuit according to claim 1.
Second bus provided between the CPU and the bus switching circuit
Further bus, and a third bus provided between the OSD circuit and the bus switching circuit, wherein the bus switching circuit includes the first bus when the wait signal is at a first level. Is connected to the third bus, and when the wait signal is at the second level, the first bus and the second bus are connected. 3. The microcomputer according to claim 1, wherein the weight signal generation circuit determines the length of the first period according to the number of characters to be on-screen displayed on the display device. 4. The microcomputer according to claim 1, wherein the weight signal generation circuit determines the length of the first period according to the number of colors of characters to be displayed on-screen on the display device. . 5. A bus control device in the case where a CPU and an on-screen display (OSD) circuit share the same ROM, wherein the ROM is a program to be executed by the CPU and an on-screen display on a display device. Display data to be stored, the OSD circuit reads the display data stored in the ROM and outputs the read display data to the display device, and the bus control device stores the first level and the second level in the first period. And a wait signal generating circuit that generates a wait signal that alternately repeats the second level during the period, and a bus is formed between the OSD circuit and the ROM when the wait signal is at the first level. And a bus switching circuit that forms a bus between the CPU and the ROM when the wait signal is at the second level. The bus control device, wherein the length of the first period is determined according to the amount of display data read from the ROM to the OSD circuit. 6. The bus control device according to claim 5, wherein the wait signal generation circuit determines the length of the first period according to the number of characters to be displayed on-screen on the display device. . 7. The bus control according to claim 5, wherein the wait signal generation circuit determines the length of the first period according to the number of colors of characters to be displayed on-screen on the display device. apparatus. 8. A method of controlling a bus in the case where a CPU and an on-screen display (OSD) circuit share the same ROM, wherein the ROM is a program to be executed by the CPU and an on-screen display on a display device. Display data to be stored, the OSD circuit reads the display data stored in the ROM, and outputs the display data to the display device. In the bus control method, first processing and second processing are performed. Alternately, in the first process, a bus is formed between the OSD circuit and the ROM for a first period, and in the second process, the CPU and the R for a second period.
A bus control method, wherein a bus is formed between the OM and the OM, and the length of the first period is determined according to the amount of display data read from the ROM to the OSD circuit. 9. The bus control method according to claim 8, wherein the length of the first period is determined according to the number of characters to be on-screen displayed on the display device. 10. The bus control method according to claim 8, wherein the length of the first period is determined according to the number of colors of characters to be on-screen displayed on the display device.