JP2003307543A - Apparatus and method for inspecting lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a conventional LSI tester that testing a real use operation of a non-synchronized, multiple-lock, high-speed system LSI is difficult, resulting in low testing quality. <P>SOLUTION: A real use operation is tested by providing a peripheral circuit including such as an external memory 104 or a peripheral LSI 105 having an operation similar to an operation of a real setting of the inspected subject LSI 101 to be actually used by a user on a load board 103 provided on an interface between a LSI tester 102 and an inspected subject LSI 101. A test result extracting circuit 109 determines the output result. The inspected subject LSI 101 can be operated only with test data and a simple control signal such as a synchronized signal or a reset signal as a test signal. The real use operation can be thus conducted by a conventional low-cost LSI tester, thereby suppressing inspection cost and improving inspection quality. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI inspection device and inspection method.

[0002]

2. Description of the Related Art Conventionally, when inspecting an LSI, an LSI tester is used to inspect the LSI alone or in combination with a simple component that assists the inspection. The simple parts here are relays,
Passive elements such as resistors, capacitors, and filters.

FIG. 9 shows the configuration of a conventional inspection method. The inspection target LSI 101 and the relay 8 are mounted on the load board 801.
02, capacitor 803, filter 804, resistor 805
Are arranged. The inspection target LSI 101 is connected to the LSI tester 102 via the load board 801. The relay 802 is for switching the connection between the LSI 101 to be inspected and the LSI tester 102, and has a capacitor 803 and a filter 80.
4. The resistor 805 is used for the purpose of converting the characteristics of the signal at the time of testing and stabilizing the power supply.

[0004] The load board 801 configured in this way
The LSI tester 102 supplies a test signal pattern of a predetermined format to the inspection target LSI 101 by using
By measuring the test result signal output by the SI 101 in response to the supply of the test signal pattern, the inspection target LSI 10
I was doing the actual operation test of 1.

Further, when testing an asynchronous output interface, the asynchronous output interface is individually operated for inspection.

As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.

[0007]

[Patent Document 1] JP-A-7-128405

[0008]

However, according to the above-mentioned prior art, a functional test in a generally used LSI tester cannot simply input a plurality of frequencies that are not in an integral multiple relationship at the same time. For LSI,
Although it is possible to perform actual operation function tests, for system LSIs that have the characteristics of high speed, asynchronous, and multiple clocks, it is difficult to perform actual operation function tests by the conventional method, and it becomes impossible to perform sufficient inspection, resulting in poor inspection quality. Guaranteed quality could not be realized. A high-speed, high-performance LSI tester is required to implement a functional test of system LSIs.
There was a problem that the inspection cost increased.

The SEMI Technology Symposium 200
The same problems as above were pointed out in P.5-81 to 5-88 of the 1st Proceedings. If a part of the content is extracted, the test based on SCAN is effective as a structural test for the purpose of eliminating manufacturing defects, but it cannot be tested by SCAN because the original functional circuit configuration of LSI itself becomes complicated. The critical path in actual operation increases. As is well known,
It often happens that there is a difference in defect detection between structural tests such as SCAN and actual functional tests. Therefore, it is essential to have a functional test for actual operation.
There was a problem that an I tester was required and the inspection cost increased.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an LSI inspection apparatus and an inspection method having a high inspection guarantee level capable of realizing an actual operation function test at a low inspection cost. To do.

[0011]

In the LSI inspection apparatus and inspection method of the present invention, a test signal pattern of a predetermined format is supplied to an inspection target LSI, and the inspection target LSI responds to the supply of the test signal pattern. In the LSI inspection using a general purpose LSI tester that tests the operation of the LSI to be inspected by measuring the output test result signal, the inspection object is placed on the load board that interfaces between the LSI tester and the LSI to be inspected. The actual operation functional test is performed by providing the LSI with a peripheral circuit known to be a non-defective product that enables the same or equivalent operation as the actual set actually used by the user. As a result, the LSI to be inspected can be actually operated only with test data as test signals and simple control signals such as a synchronizing signal and a reset signal, and an actual operation test can be performed with the general LSI tester described above. Therefore, it is possible to suppress an increase in inspection cost to a minimum and improve inspection quality.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows the configuration of an LSI inspection apparatus according to the present invention. The inspection target LSI 101 is connected to the external memory 104, the peripheral LSI 105, and the test result capturing circuit 109 that captures the test result on the load board 103 as in the actual use state of the user. The clock generator A 106, the clock generator B 107, and the clock generator C 108 are also connected in the same way as in the actual use state of the user. In this embodiment, all the outputs of the clock generator are supplied to the inspection target LSI 101, and the external memory 10
4. It is assumed that the clocks to the peripheral LSI 105 and the test result acquisition circuit 109 are supplied from the inspection target LSI 101. The clock A supplied from the clock generator A 106 is the inspection target LSI 101, the external memory 104, and the peripheral.
It is used as a reference clock for data processing used in the LSI 105. The clock B supplied from the clock generator B107 is used as a clock for the inspection target LSI 101 to fetch a signal. The clock supplied from the clock generator C108 is used as a clock for the LSI under test 101 to output a signal. In addition to the wiring for the actual operation described above, the LSI tester 102 is used at the time of inspection.
Signal lines for interfacing with are also wired on the load board 103. Further, the inspection target LSI 101, the external memory 104, the peripheral LSI 105, the clock generator 106 to
Power for 108 and the test result acquisition circuit 109 is supplied from the LSI tester 102. Road board 10
As long as the configuration of No. 3 is the same as the actual use by the user, even if it is different from this embodiment, it is naturally within the scope of the claims of the present invention. The parts on the load board 103 are non-defective products in advance except the LSI 101 to be inspected.

Next, the data flow at the time of inspection will be described with reference to FIG. The test signal 201 indicated by the solid line is input from the LSI tester 102 to the inspection target LSI 101, and the inspection target LSI 101 is subjected to the flow indicated by the broken line 202 in the same manner as the actual operation.
It is processed by the external memory 104 and the peripheral LSI 105. After that, it is taken into the LSI tester 102 as a test result signal 203, and a pass / fail judgment is made by comparing expected values. It should be noted that if the data flow is the same as in actual use, it is naturally within the scope of the claims of the present invention even if it is different from this embodiment.

When the output interface is tested, the test signal 204 is the test result acquisition circuit 109.
Is output to the LSI tester 102, and the LSI tester 102 makes a pass / fail judgment by comparing expected values. In the case of a configuration in which the compression circuit is included in 109, the output result is compressed by the internal compression circuit, and the LSI tester 102 determines whether the compression result is good or bad by comparing expected values. Further, when 109 has a function capable of making a comparison judgment, the comparison judgment is made at 109, and only the pass / fail result is output to the LSI tester 102.

Next, the inspection flow will be described with reference to the flowchart of FIG. First, the inspection target LSI 101, the external memory 104, the peripheral LSI 105, and the clock generators 106 to 1
08, the power of the test result acquisition circuit 109 is turned on. Then, the clocks A, B, and C are started to be supplied from the clock generators 106 to 108 to the inspection target LSI 101, respectively. Next, reset is performed asynchronously with those clocks, and the LSI under test 101 is ready for actual use. Although the test signal 201 is supplied from the LSI tester 102 in this state, it is necessary to synchronize with the clock B. Therefore, the LSI tester 102 takes in the clock B and synchronizes. At this time, synchronization is achieved by using the edge search function and the match function provided in a general LSI tester. The input of the test signal 201 to the LSI to be inspected 101 is started at the timing of the synchronization, and the actual use operation is performed on the load board 103. The actual operation is performed in synchronization with clock A. Test result signal 203 obtained by actual use operation
When the LSI is loaded by the LSI tester 102, it must be loaded in synchronization with the clock C. Similar to when inputting the test signal, the clock C is taken in and the process of synchronizing with the clock C is performed.
The test result signal 203 is captured. Finally, LSI tester 10
In step 2, the test result signal 203 is compared with the expected value, and the quality of the inspection target LSI 101 is judged. When the test result of the output interface is to be inspected separately, the test signal 204 is output, and as shown in FIG.
The result is output to 09, only the valid data of the fetched result is fetched by the enable control circuit 110, and the fetched valid data is compressed by the compression circuit 111.

The compressed data is compared with the data stored in the expected value memory 113 by the judgment circuit 112, and only the judgment result is output to the tester 102 for inspection.
The quality of the LSI 101 is determined.

The LSI 101 to be inspected and the external memory 10
4 and the peripheral LSI 105 can be interfaced at a very high speed, but an actual operation test can be performed in exactly the same manner as the above-described embodiments. This is because the interface is independent of the input / output of the LSI tester 102, and the LSI tester 102 does not need to be a high speed tester.

As described above, only the general LSI tester and the peripheral circuits such as the external memory 104 and the peripheral LSI 105 that enable the LSI to be inspected 101 to perform an operation equivalent to the actual use by the user are used for the asynchronous, multi-clock, high-speed system LSI. Real operation test can be realized. Therefore, the inspection quality can be significantly improved at a low inspection cost.

In this embodiment, the LSI tester 102
Although the process of synchronizing with the clock is performed at the time of input / output, it may be possible that no synchronization is required depending on the specifications of the LSI under test. In that case, the actual operation test can be performed only by removing the synchronization processing of the inspection flow.

(Embodiment 2) In the case of the example given in Embodiment 1, it is possible to carry out an actual operation test at a low cost. However, the configuration with one load board is more feasible and costly. The problem remains. The reason will be explained below.

The actual set board used by the user or the evaluation board used in the evaluation stage and the load board used for the LSI inspection have completely different specifications such as the number of layers of the board and the wiring length, and are usually prepared separately. Different boards require different technologies and know-how. Therefore, in order to combine the two into one board, it is necessary to combine the technology and know-how of both to create the board, and a high level technology is required. In many cases, the user and the LSI vendor are separate, it is difficult for the user to provide the technology for board creation, and it is very difficult to combine the technologies. Further, as the number of board layers of the board increases, it is technically difficult to make the board, and the cost increases dramatically. A normal load board is realized by a multi-layer board, but the load board used in the first embodiment is a multi-layer board with more layers, and the cost is very large.

The second embodiment further shows an inspection apparatus capable of improving the feasibility of the load board and reducing the cost of the load board, as compared with the first embodiment.

FIG. 4 shows another configuration of the LSI inspection apparatus of the present invention. In contrast to the load board 103 shown in FIG. 1, the load board 401 includes an inspection target LSI 101, an external memory 104,
A signal line which is required to separate the first board 402 composed of the peripheral LSI 105 and the clock generators 106 to 108 from the second board 403 which interfaces with the LSI tester 102 and connect the boards to the LSI tester 102. It has a configuration in which spaces are wired. 404 and 4 in FIG.
Reference numeral 05 is a wiring connecting the first board 402 and the second board 403, and reference numerals 405 to 408 are columns that support the first board 402.

For example, the first board 402 is exactly the same as the board used in the actual set, and the second board 4
03 is a widely sold tester maker, and a general-purpose load board with a pre-wired board between the tester channel and the board is used, and the board is wired between the signal lines that need to be connected to the LSI tester 102. When configured, it applies to this embodiment. The data flow at the time of inspection and the inspection flow are exactly the same as in the first embodiment.

With this configuration, the inspection target LSI 1
01 and the first board 402 including peripheral circuits can be independently created and debugged. Therefore, the first
Since it is not necessary to combine the techniques for creating the board and the second board, the feasibility of the load board becomes very high.
Normally, it is sufficient to repeat the first board that has been evaluated and make some modifications, purchase the general-purpose load board sold by the tester maker for the second board, and wire between the two boards. In contrast to the load board 401 made of a multilayer board, the first board 402 can usually be made with a small number of layers, so that it is possible to suppress an increase in board making cost. Furthermore, if the board used in the actual set has the exact same configuration and is shared, the board creation cost can be reduced. Also, LS
Even if you do not use the I tester 102, if you have an actual set evaluation system, you can use it to debug.
The board debug using the I tester can be almost eliminated.

(Third Embodiment) In the third embodiment, an inspection method for further reducing the test cost by facilitating synchronization between the LSI tester and the LSI to be inspected and interfacing at a low speed is further provided from the first embodiment. Show.

The load board configuration in this embodiment is shown in FIG.
The load board 103 shown in FIG. 4 or the load board 401 shown in FIG. Here, only the data flow at the time of inspection and the inspection flowchart are different.

The data flow at the time of inspection by the LSI inspection method of the present invention will be described with reference to FIG. First, the LSI tester 10
The test signal 501 indicated by the solid line from 2 is the LSI 101 to be inspected.
The data is written to the external memory 104 via the, is processed by the inspection target LSI 101, the external memory 104, and the peripheral LSI 105 in the same manner as the actual operation in the flow indicated by the broken line 502, and is again written to the external memory 104. Then test result signal 503
Is taken into the LSI tester 102 via the inspection target LSI 101, and a pass / fail judgment is made by comparing expected values.

Next, the inspection flow will be described with reference to the flowchart of FIG. First, the inspection target LSI 101, the external memory 104, the peripheral LSI 105, and the clock generators 106 to 1
Power on 08. Then, the clock generator 10
Clocks A, B, and C from 6 to 108 are the inspection target LSI 1 respectively
Supply to 01 is started. Next, reset is performed asynchronously with those clocks, and the LSI under test 101 is ready for actual use. Here, the test mode is set from the LSI tester 102 to the inspection target LSI 101. This test mode is an operation mode corresponding to the actual use operation in which the data at the time of the actual use operation test is input from the external memory 104 and the data after the actual use operation process is written again to the external memory 104. Such a test mode can be
It is necessary to design it as the specification of. After the test setting, the test signal 201 is written from the LSI tester 102 to the external memory 104 using the asynchronous access function of the inspection target LSI 101 to the external memory 104. in this case,
Since it can be accessed asynchronously with the clocks A, B, C, the LSI tester 102 does not need to be synchronized as in the first embodiment. Generally, it can be performed at a lower speed than the input / output in the actual operation. When the writing is completed and the asynchronous access state is released, the same operation as the actual use operation is performed on the load board 103, and the test result signal 503 is transmitted to the external memory 1
Written to 04. Test result signal 503 is to be inspected
It is loaded into the LSI tester 102 using the asynchronous access function of the LSI 101 to the external memory 104. Finally LSI
The tester 102 compares the test result signal 503 with the expected value to determine whether the inspection target LSI 101 is good or bad.

As a result, the LSI tester 102 and the inspection target L
The SI 101 can be easily synchronized and can be interfaced at a low speed. Therefore, the LSI tester used does not need the function of synchronizing and the low-speed tester is improved, so that the test cost can be reduced.

In this embodiment, the LSI tester 102
The external memory 104 is used for the interface with the above, but it is also conceivable to use the memory built in the inspection target LSI 101 or the peripheral LSI 105.

(Fourth Embodiment) In the fourth embodiment, the test signal and the test signal used in the third embodiment are constructed by constructing a system for generating the test signal and the test result signal using an actual set evaluation device. We show an inspection method that shortens the generation time of the result signal and makes debugging on the LSI tester almost unnecessary.

The test signal and test result signal for the LSI tester are usually generated by simulation. Generating a test signal and a test result signal in the inspection by the LSI inspection device and the inspection means of the present invention by a simulation results in an enormous amount of data to be handled, which requires a considerable amount of time and machine power.

FIG. 8 shows an LSI using an actual set evaluation device.
1 shows a test signal and test result signal generation system configuration for a tester. The actual set evaluation device board 703 is the same as the first board 407 described in the second embodiment except that the test signal generator 7 is used.
02, a monitor 704 for monitoring the test result, and an interface of a personal computer 705 are added. Power is supplied from the power source 706.

In the data flow for generating the test signal and the test result signal, the source of the test signal is changed to the test signal generator 702 and the destination of the test result signal is changed to the monitor 704 or the personal computer 705 from the third embodiment. Only the others are the same.

Next, the test signal and test result signal generation flow will be described. First, after turning on the power supply and resetting, a predetermined amount of test signal is supplied from the test signal generator 702, and the test result signal is subjected to a sensitivity test on the monitor 704 for correctness. If it is determined to be correct, then move to the step of extracting the test signal to the personal computer. Reset again,
The personal computer controls the LSI to be inspected 101 to write the same test signal to the external memory 104. Therefore, the test signal is fetched to the personal computer 705 by using the asynchronous access function of the inspection target LSI 101 to the external memory 104. Furthermore, it moves to the step of taking out the test result signal to the personal computer. After resetting again, the same test signal is supplied from the test signal generator 702, and the LSI under test 1
01 is controlled to write the test result signal to the external memory 104. Therefore, the test result signal is fetched into the personal computer 705 by using the asynchronous access function of the inspection target LSI 101 to the external memory 104.

Based on the test signal and the test result signal thus obtained, a reset pattern, a test setting pattern, and an asynchronous access pattern to the external memory 104 via the inspection target LSI 101 are added to the LSI tester 102.
Generate a test signal and a test result signal for.

As a result, the generation time of the LSI test signal and the test result signal becomes about several tens of minutes, which can be greatly shortened compared with the generation time in the simulation. Furthermore, since the test result signal is generated under the environment equivalent to that at the time of LSI inspection, debugging on the LSI tester can be almost eliminated.

Since this interface is simply added to the first board 407, the actual set evaluation device board 703 is replaced with the first board 407 to form a load board equivalent to the load board 401 of the second embodiment. can do. That is, the load board can be created by diverting the actual set evaluation device board, and the load board design cost can be reduced as described in the second embodiment.

This embodiment shows an example of generating the test signal and the test result signal used in the third embodiment, but the test signal and the test result signal contents are the same as the signal contents used in the first and second embodiments. Is. Therefore, the test signal and the test result signal used in the first and second embodiments can be generated by changing the additional pattern when converting the test signal for the LSI tester and the test result signal.

[0042]

According to the LSI inspection apparatus and method of the present invention, a general LSI tester and a peripheral circuit that enables the LSI to be inspected to perform an operation equivalent to the operation on the actual set actually used by the user. Only by doing so, the actual operation test of asynchronous, multi-clock, high-speed system LSI can be realized. Therefore, the inspection quality can be significantly improved at a low inspection cost.

Further, by making the board to be inspected and the board having the peripheral circuit independent and separate from the board which interfaces with the input / output channel of the LSI tester, the board can be easily manufactured and the increase in board cost can be suppressed. The board debug on the tester can be made almost unnecessary.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an LSI inspection apparatus of the present invention.

FIG. 2 is a data flow diagram at the time of inspection by the LSI inspection device of the present invention.

FIG. 3 is an inspection flowchart in the LSI inspection apparatus of the present invention.

FIG. 4 is a diagram showing another configuration of the LSI inspection apparatus of the present invention.

FIG. 5 is a data flow diagram at the time of inspection by the LSI inspection method of the present invention.

FIG. 6 is a diagram showing a test result acquisition circuit configuration in the LSI inspection method of the present invention.

FIG. 7 is an inspection flowchart in the LSI inspection method of the present invention.

FIG. 8 is a diagram showing the configuration of a test signal and test result signal generation system of the LSI inspection method of the present invention.

FIG. 9 is a diagram showing a configuration of a conventional LSI inspection method.

[Explanation of symbols]

101 LSI to be inspected 102 LSI tester 103 road board 104 external memory 105 peripheral LSI 106 Clock generator A 107 Clock generator B 108 Clock generator C 109 Test result acquisition circuit 802 relay 803 capacitor 804 Filter 805 resistance

Continued front page    (72) Inventor Takeshi Yamashita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Akihiko Watanabe             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 2G132 AA00 AB01 AC01 AC09 AE14                       AE18 AE23 AE30 AG02 AG08                       AH07 AL09 AL11

Claims (10)

[Claims] 1. A test signal pattern of a predetermined format is supplied to a test target LSI, and a test result signal output by the test target LSI in response to the supply of the test signal pattern is measured to obtain the test target pattern. LS using LSI tester to test LSI operation
In the I inspection, on the load board that interfaces between the LSI tester and the LSI to be inspected, the LSI to be inspected can perform the same or equivalent operation as the actual set actually used by the user. Characterized by having peripheral circuits known to be non-defective
LSI inspection equipment. 2. The load board includes one or a plurality of first boards having the LSI to be inspected and the peripheral circuit, and an interface with an input / output channel of the LSI tester, separately from the first board. 2. The LSI inspection apparatus according to claim 1, further comprising: a second board that connects the first board and the second board. 3. The LSI inspection method according to claim 1, wherein the test signal pattern supplied from the LSI tester is supplied to the inspection target LSI or the peripheral circuit. 4. The test result signal output from the LSI to be inspected is read to the LSI tester directly from the LSI to be inspected or via the peripheral component. LSI inspection method. 5. The memory to be inspected or the peripheral component has a memory that can be accessed asynchronously with respect to a reference clock during actual operation.
The described LSI inspection device. 6. The LSI inspection method according to claim 5, wherein the test signal pattern supplied from the LSI tester is supplied to the inspection target LSI via the memory. 7. The LSI inspection method according to claim 5, wherein the test result signal output from the inspection target LSI is read to the LSI tester via the memory. 8. The test target pattern is supplied to a test target LSI by measuring a test result signal output from the test target LSI in response to the supply of the test signal pattern. In an LSI inspection using an LSI tester that tests the operation of an LSI, a device that captures the test result signal and performs data compression or result determination is provided on a load board that interfaces between the LSI tester and the inspection target LSI. An LSI inspection device characterized in that 9. The test result on the load board,
The enable control circuit that fetches only the necessary test result data by performing the enable control is added to the inspection target LS.
An LSI inspection device characterized by being provided inside or outside the I. 10. The test signal pattern and the test result signal are not generated by simulation using a simulation model in which the operation of the inspection target LSI is described, but are the same as the inspection target LSI or the inspection target LSI. Using an actual LSI with a configuration, using an actual set evaluation device equipped with a peripheral circuit that enables the LSI to be inspected to perform the same or equivalent operation as on the actual set actually used by the user. The LSI inspection method according to claim 1, wherein the LSI inspection method is generated.