JP2007232620A - Semiconductor evaluation method, specimen mounting substrate, and semiconductor evaluation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evaluate reliability of a semiconductor device under a condition close to an actual mounting condition. <P>SOLUTION: The semiconductor evaluation device has: a specimen mounting substrate 2 provided with a mounting part with DUTs 1<SB>1</SB>-1<SB>n</SB>mounted thereon, and peripheral circuits connected to the DUTs mounted on the mounting part; a variable electric power source 6 for supplying electric power to the DUTs mounted on the mounting part; a clock generating circuit 7 for supplying a clock to the DUTs mounted on the mounting part; a test pattern generating/measuring circuit 8 for supplying a test pattern to the DUTs mounted on the mounting part, and for measuring outputs from the DUTs; and a control part 10 for controlling the variable electric power source 6 and the clock generating circuit 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for evaluating the reliability of a semiconductor device such as an IC or an LSI, particularly a semiconductor device capable of flip chip mounting that does not require lead wires to be drawn from a chip to a substrate.

An apparatus that can evaluate the reliability of a semiconductor device by changing parameters such as a power supply voltage and an operating frequency has been proposed (see Patent Document 1). The apparatus described in Patent Document 1 includes a tester CPU that can set test condition data for a start value, a change amount, and a stop value, a register unit that holds test condition data set by the tester CPU, and the register A data generation unit that generates data to be supplied to the subject based on the test condition data held by the unit, and pin electronics for supplying the data generated by the data generation unit to the subject. According to this apparatus, by connecting the semiconductor device that is the subject to the pin electronics, the operation frequency is constant and the power supply voltage is changed stepwise to check the operating state of the semiconductor device at each voltage, In addition, it is possible to check the operation state of the semiconductor device at each operation frequency by changing the operation frequency stepwise while keeping the power supply voltage constant.
JP 9-318705 A

  The number of cases in which a malfunction of a semiconductor device occurs during an actual operation on an apparatus on which the semiconductor device is mounted. For this reason, it has been demanded that the reliability evaluation of semiconductor devices be performed in a state closer to an actual mounting form. For example, in an electronic device such as a personal computer or a mobile phone, a peripheral circuit (for example, a memory or various interfaces) connected to the semiconductor device may be mounted on a printed board on which the semiconductor device is mounted. In many cases, it is required to evaluate a semiconductor device with the semiconductor device and peripheral circuits mounted together on a printed circuit board. In particular, in recent electronic equipment in which a semiconductor device is mounted on a substrate by flip chip mounting, it is necessary to perform evaluation with a peripheral circuit mounted together with the semiconductor device because of higher functionality and higher speed. It has become a higher one.

  However, in the apparatus described in Patent Document 1, since the terminal (for example, a power supply terminal) of a semiconductor device that is a subject is simply connected to pin electronics, the semiconductor device is evaluated in a state close to an actual mounting form. It is difficult.

  An object of the present invention is to provide a semiconductor device evaluation apparatus capable of solving the above problems and evaluating the reliability of a semiconductor device in a state close to an actual mounting state.

  To achieve the above object, the present invention provides a subject mounting provided with at least one mount portion on which a semiconductor device as a subject is mounted and a peripheral circuit connected to the semiconductor device mounted on the mount portion. A variable power supply for supplying power to a semiconductor device mounted on the mounting unit, a semiconductor device mounted on the mount unit, and a clock generation with a variable output clock frequency for supplying a clock to the semiconductor device mounted on the mount unit And a test pattern generation / measurement circuit for supplying a test pattern for operating the semiconductor device to the semiconductor device mounted on the mount unit and measuring an output of the semiconductor device, and an output of the variable power supply A control unit for controlling the voltage and the frequency of the output clock of the clock generation unit, respectively. That, characterized in that.

  According to the above configuration, since the test is performed by mounting the semiconductor device on the subject mounting board having the peripheral circuit, the semiconductor device can be evaluated in a state closer to the form mounted on the actual product. Is possible.

  According to the present invention, it is possible to perform a test in a state closer to a form mounted on an actual product, so that it is possible to obtain an evaluation result of a semiconductor device with higher reliability than in the past.

  Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor evaluation apparatus according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor evaluation apparatus according to the present embodiment includes a subject mounting board 2 on which devices under test (DUTs) 1 ₁ to 1 _n are mounted, a variable power supply 6, a variable clock generation circuit 7, It comprises a test pattern generation / measurement circuit 8, a switch 9, a control unit 10, and a thermostatic chamber 11.

The subject mounting board 2 is provided with peripheral circuits connected in advance to the DUTs _{1 1} to 1 _n to be mounted. The variable power supply 6 is for supplying a voltage to the DUTs _{1 1} to 1 _n and the peripheral circuits on the subject mounting board 2, and its output voltage changes according to a control signal from the control unit 10. The variable range of the output voltage of the variable power source 6 includes a range from the lowest operating voltage of the DUT to the highest operating voltage. The variable clock generation circuit 7 is for supplying a clock to the DUTs _{1 1} to 1 _n on the subject mounting board 2, and the frequency of the output clock changes according to a control signal from the control unit 10. The variable range of the frequency of the output clock of the variable clock generation circuit 7 includes a range from the lowest operation frequency of the DUT to the highest operation frequency.

The switch 9 is a switch for switching the connection between the test pattern generation / measurement circuit 8 and the DUTs _{1 1} to 1 _n . The test pattern generation / measurement circuit 8 generates a test pattern for operating the DUTs 1 ₁ to 1 _n and measures the output of the DUT that has supplied the test pattern. The test pattern generated by the test pattern generation / measurement circuit 8 is supplied to _{one of} the DUTs _{1 1} to 1 _n via the switch 9. Outputs of DUTs _{1 1} to 1 _n are supplied to a test pattern generation / measurement circuit 8 via a switch 9. The constant temperature bath 11 is configured to store a region where the DUTs _{1 1} to 1 _n of the subject mounting board 2 are mounted, and can maintain the temperature in the bath at a temperature specified by the control unit 10. It is.

  The control unit 10 controls operations of the variable power supply 6, the variable clock generation circuit 7, the test pattern generation / measurement circuit 8, the switch 9, and the thermostatic chamber 11.

FIG. 2 shows the configuration of the subject mounting board 2. As shown in FIG. 2, the subject mounting board 2 is a printed board, and has a region 2 a where the DUTs _{1 1} to 1 _n are mounted and a region 2 b where the peripheral circuit 20 is mounted. In the region 2a, mount portions 2 ₁ to 2 _{n on} which the DUTs _{1 1} to 1 _n are mounted are provided.

The peripheral circuit 20 is a peripheral circuit connected to the DUT mounted on the mount units 2 ₁ to 2 _n . Examples of the peripheral circuit 20 include a semiconductor memory (for example, DRAM) and various interfaces.

Each DUT1 ₁ to 1 _n is a semiconductor chip with metal bumps on the surface of the side to be mounted on the mount portion, each of the mount portion 2 ₁ to 2 _n correspond with the DUT bump implemented Metal bumps are provided at the positions. Figure 3 is a schematic view showing a mounting portion 2 ₁ of the configuration. As shown in FIG. 3, the DUT _{1 1} is mounted on the mount portion 2 ₁ so that the metal bumps are bonded to each other (flip chip mounting). The thermostat 11 is provided so as to accommodate the region 2a.

Although not shown in FIG. 2, the subject mounting board 2 is provided with wiring necessary for operating the DUT together with the peripheral circuit 20 for evaluation. As the wiring, for example, wiring for supplying power from the variable power source 6 to the DUT mounted on the mount units 2 ₁ to 2 _n and the clock from the variable clock generation circuit 7 are mounted on the mount units 2 ₁ to 2 _n . There are wiring for supplying to the mounted DUT, wiring for inputting / outputting data to / from the DUT mounted on the mount portions 2 ₁ to 2 _n , and the like. When the peripheral circuit 20 is a circuit that requires power, a power supply and wiring for supplying the power are separately provided.

  Next, the operation of the semiconductor evaluation apparatus of this embodiment will be described.

  FIG. 4 shows the relationship between the operating frequency and operating voltage of a semiconductor device. As shown in FIG. 4, the operating frequency of the semiconductor device increases as the operating voltage increases. Test conditions for evaluating the reliability of a semiconductor device having such characteristics include a first test condition in which the operating voltage is constant and the frequency is variable, and a first test condition in which the operating frequency is constant and the operating voltage is variable. Two test conditions are considered.

  In the semiconductor evaluation apparatus according to the present embodiment, the DUT can be evaluated in a state where the DUT and the peripheral circuit are operated together under the first or second test conditions.

  When the evaluation is performed under the first test condition, the control unit 10 controls the output voltage of the variable power supply 6 to be constant, and changes the frequency of the output clock of the variable clock generation circuit 7 stepwise. Further, the control unit 10 supplies the test pattern generated by the test pattern generation / measurement circuit 8 to the designated DUT on the subject mounting board 2 and outputs the DUT as the test pattern generation / measurement circuit 8. The switch 9 is controlled so as to be supplied to. If the test pattern generation / measurement circuit 8 generates a test pattern, for example, a pattern in which data is written to and read from DRAM in which the DUT is a peripheral circuit, the DUT and the peripheral circuit operate together. Can be made. The frequency of the output clock is first set to a recommended frequency and then increased by, for example, 10 MHz.

  When the evaluation is performed under the second test condition, the control unit 10 controls the frequency of the output clock of the variable clock generation circuit 7 to be constant, and changes the output voltage of the variable power supply 6 stepwise. Further, the control unit 10 supplies the test pattern generated by the test pattern generation / measurement circuit 8 to the designated DUT on the subject mounting board 2 and outputs the DUT as the test pattern generation / measurement circuit 8. The switch 9 is controlled so as to be supplied to. The output voltage is first set to the recommended voltage, and then lowered by, for example, 0.1V.

  Hereinafter, the operation of the semiconductor evaluation apparatus according to the present embodiment will be specifically described with an example in which the evaluation is performed under the first test condition.

  FIG. 5 shows a flow of processing by the control unit 10 in the evaluation of the first test condition. First, the output voltage of the variable power source 6 is set to a predetermined voltage (recommended voltage) (step 101). Next, the frequency of the output clock of the variable clock generation circuit 7 is set to a predetermined operating frequency (recommended frequency) (step 102). Next, the test pattern generation / measurement circuit 8 generates a test pattern and measures the output of the DUT supplied with the test pattern (step 103). Next, based on the measurement result by the test pattern generation / measurement circuit 8, it is determined whether there is any problem in the device operation (step 104). If there is no problem in device operation, the frequency of the output clock of the variable clock generation circuit 7 is increased (step 105), and the process proceeds to step 103. If there is a problem with device operation, the voltage and frequency at that time are stored in a storage unit (not shown) (step 106), and the process is terminated. In the information recording in step 106, other information such as the temperature chamber conditions (temperature, humidity, cycle number) may be stored together in the storage unit.

  By separately referring to the measurement data stored in the storage unit, it is possible to grasp the degree of deterioration of the semiconductor device before and after the reliability test is performed. Note that by generating a test pattern that operates only with the DUT, it is possible to perform a test with the DUT alone.

  According to the semiconductor evaluation apparatus of the present embodiment described above, the DUT is mounted on the subject mounting board 2 provided with the peripheral circuit and the test is performed. Therefore, the test in a state closer to the form mounted on the actual product. Is possible. In particular, in recent electronic equipment in which a semiconductor device is mounted on a substrate by flip-chip mounting, when the semiconductor device is evaluated, it is necessary to evaluate the semiconductor device and the peripheral circuit operating together. Therefore, the semiconductor evaluation apparatus of the present embodiment has a flip chip mounted semiconductor device and a peripheral circuit on the same substrate, and thus has a particularly great effect in the evaluation of the semiconductor device in such an electronic apparatus.

  In addition, since the power source and the clock can be varied, it is possible to confirm the operation of the dynamic device when the power source and the clock are varied.

  Furthermore, since the subject mounting board can be equipped with a plurality of DUTs, and the DUT selected by the switch can be operated together with the peripheral circuit for evaluation, it is necessary to replace the DUT once for each evaluation. Absent. Therefore, work efficiency is also improved.

  Furthermore, since the measurement system, the power source, and the clock source are placed outside the thermostat and can be tested only with the DUT, a reliability test can be performed with the DUT alone.

  Furthermore, the configuration in which only the DUT is accommodated in the thermostatic chamber allows the DUT to be separated from the system in which the measurement and control are performed, and the DUT can be evaluated without being affected by the parts not related to the actual evaluation. . Thereby, the reliability of the evaluation result is further improved.

  Moreover, since the test can be performed in the state of the chip, there is no need to assemble.

  In addition, since it is possible to evaluate the DUT alone and in a state including the DUT and the peripheral circuit, it is possible to simultaneously examine the normal reliability test and the deterioration of the chip speed.

  In the above-described embodiment, the semiconductor device that is mounted on a flip chip is evaluated. However, the present invention is not limited to this. The present invention can also be applied to evaluation of semiconductor devices that perform other mounting methods, for example, bare chip mounting in which a chip is directly mounted on a substrate.

It is a block diagram which shows schematic structure of the semiconductor evaluation apparatus which is one Embodiment of this invention. It is a top view which shows the structure of the test subject mounting board | substrate shown in FIG. It is a schematic diagram which shows an example of the mount part shown in FIG. It is a figure which shows the relationship between the operating frequency of a semiconductor device, and an operating voltage. It is a flowchart which shows the flow of a process by the control part in the case of evaluating a semiconductor device on the test conditions which have a constant operating voltage and variable frequency.

Explanation of symbols

1 ₁ to 1 _n Device under test (DUT)
2 Substrate mounting board 6 Variable power supply 7 Variable clock generation circuit 8 Test pattern generation / measurement circuit 9 Switch 10 Control unit 11 Temperature chamber

Claims (8)

A test subject mounting substrate provided with at least one mount portion on which a semiconductor device as a test subject is mounted and a peripheral circuit connected to the semiconductor device mounted on the mount portion;
A variable power supply for supplying power to the semiconductor device mounted on the mount;
A clock generating unit capable of supplying a clock to a semiconductor device mounted on the mount unit, wherein the output clock frequency is variable;
A test pattern generation / measurement circuit for supplying a test pattern for operating the semiconductor device to the semiconductor device mounted on the mount unit and measuring an output of the semiconductor device;
And a control unit that controls the output voltage of the variable power supply and the frequency of the output clock of the clock generation unit. A plurality of the mount parts are provided on the subject mounting substrate,
A switch that selectively switches the connection between the test pattern generation / measurement circuit and each of the semiconductor devices mounted on the plurality of mount parts,
2. The semiconductor evaluation apparatus according to claim 1, wherein the control unit controls the switch to select one of a plurality of semiconductor devices mounted on the mount unit.   The semiconductor evaluation apparatus according to claim 1, further comprising a thermostatic chamber that accommodates a region of the subject mounting substrate in which the mount portion is formed. The semiconductor device is a chip in which a first metal bump is provided on a surface mounted on the mount portion,
4. The semiconductor evaluation apparatus according to claim 1, wherein the mount portion includes a second metal bump bonded to a first metal bump provided on the chip. 5. A test subject mounting substrate used in an apparatus for evaluating a semiconductor device,
At least one mount portion on which a semiconductor device as a subject is mounted;
A test subject mounting board comprising: a peripheral circuit connected to a semiconductor device mounted on the mount portion.   The test subject mounting substrate according to claim 5, further comprising a thermostatic chamber that accommodates the region in which the mount portion is formed. The semiconductor device is a chip in which a first metal bump is provided on a surface mounted on the mount portion,
The test subject mounting substrate according to claim 5, wherein the mount portion includes a second metal bump bonded to a first metal bump provided on the chip. A semiconductor evaluation method using a test subject mounting substrate provided with at least one mount part on which a semiconductor device as a test object is mounted and a peripheral circuit connected to the semiconductor device mounted on the mount part,
Supplying a voltage and a clock to the semiconductor device mounted on the mount unit, and changing one of the voltage and the clock stepwise;
Supplying a test pattern for operating the semiconductor device to the semiconductor device mounted on the mount unit, and measuring the output of the semiconductor device for each stepwise changed voltage or frequency; A semiconductor evaluation method.

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