JP2004260090A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can carry out a self-test of an operation margin effectively at a low cost. <P>SOLUTION: The semiconductor integrated circuit device has a functional block with a semiconductor circuit including a central processing unit, a memory storing a self-test program for carrying a self-test of a semiconductor circuit inside the functional block, a first transformation circuit which converts a power supply voltage input from an outside to a prescribed voltage and outputs it, and a second transformation circuit which converts output from the first transformation circuit at a prescribed ratio and outputs it as an operation voltage for a self-test to the functional block. The central processing unit is constituted to control a voltage output from the first transformation circuit and the second transformation circuit according to a self-test program, and to carry out a self-test of a semiconductor circuit autonomously. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a built-in self-test function for autonomously testing a capability of a semiconductor integrated circuit to cope with power supply voltage fluctuations and frequency clock fluctuations.
[0002]
[Prior art]
Conventionally, in a semiconductor integrated circuit device, an operation margin test such as a voltage margin test and a frequency margin test for confirming a capability of responding to a power supply voltage variation and a clock frequency variation is exclusively connected to the outside of the semiconductor integrated circuit device. This is performed using a tester capable of controlling the voltage and the frequency of a clock signal (for example, see Patent Document 1).
[0003]
For a voltage margin test using a conventional tester, a functional block using a predetermined internal voltage such as a central processing unit (CPU), a read only memory (ROM) or a timer circuit as an operation power supply, such as a central processing unit (CPU), and a read only memory (ROM). , A power transformer circuit, a memory storing a test program for an operation margin test, and an I / O port (Input / Output Port) of a large-scale integrated circuit device (LSI: Large-Scale Integration). The case will be described as an example.
[0004]
In such an LSI, in the case of normal driving, the external power supply voltage becomes the power supply of the I / O port, and a predetermined constant voltage obtained by stepping down the external power supply voltage by the transformer circuit becomes the power supply of the functional block. Further, a clock signal input from the outside is converted into a predetermined frequency at an I / O port and supplied to a functional block.
[0005]
When performing a voltage margin test or a frequency margin test of a functional block, it is necessary to perform a test at a plurality of test points where the power supply voltage and the frequency of the clock signal are changed so as to cover the product specifications. In this case, an external power supply voltage and a frequency clock from the tester are used, but it is necessary to control the power supply voltage and the frequency clock input to the functional block under a plurality of conditions according to the product specifications.
[0006]
For example, when the product specification values are: internal power supply voltage: 3 V ± 10%, maximum frequency: 20 MHz, the voltage margin test and the frequency margin test are performed at a test point of internal power supply voltage: 3.3 V or more, frequency: 20 MHz or more, internal power supply It is necessary to perform the test under conditions that include the product standard value, such as a test point of voltage: 2.7 V or less and frequency: 20 MHz or more.
[0007]
[Patent Document 1]
JP-A-62-38374 (pages 2 to 4, FIG. 1)
[0008]
[Problems to be solved by the invention]
However, when the power supply voltage from the tester is constant, only a predetermined constant voltage can be input to the function block via the power supply transformation circuit. Therefore, when performing a test of a functional block, a voltage and a clock signal are directly input from the tester to the functional block, bypassing the power transformer circuit. That is, the voltage and the clock signal input from the tester become the voltage and the clock signal when the test is performed.
[0009]
Therefore, in order to perform the self-test under a plurality of conditions as described above, the power supply voltage input to the LSI and the frequency of the clock signal must be controlled in the tester. Then, as the LSI to be tested becomes sophisticated and the product specifications become more complicated, the number of test points to be executed increases, and accordingly, the control of the voltage or the frequency of the clock signal in the tester becomes complicated.
[0010]
Therefore, a plurality of testers must be prepared in accordance with the type of the specification of the LSI to be tested, and the tester must be replaced for each LSI, which causes a problem that the operation becomes complicated and the test time becomes long.
[0011]
In addition, in order to perform complicated control of the power supply voltage or the frequency of the clock signal, a high-performance tester capable of controlling these under a wide range of conditions is required. Problem.
[0012]
The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor integrated circuit device capable of inexpensively and efficiently performing a self-test of an operation margin.
[0013]
[Means for Solving the Problems]
A semiconductor integrated circuit device according to the present invention that solves the above-described problems is a semiconductor integrated circuit device having a self-test function for autonomously testing an operation margin with respect to an internal voltage change of a built-in semiconductor circuit, A functional block including a semiconductor circuit including a central processing unit, a memory storing a self-test program for performing a self-test of the semiconductor circuit in the functional block, and a circuit for converting a power supply voltage input from the outside into a predetermined voltage And a second transformer circuit for converting the output from the first transformer circuit at a predetermined ratio and outputting it as an operating voltage for self-test to a functional block. A first transformer circuit and a second transformer circuit in accordance with a self-test program in a test mode in which the arithmetic processing unit performs a self-test; And performing a self-test of autonomously semiconductor circuit controls the voltage et output.
[0014]
In the semiconductor integrated circuit device according to the present invention configured as described above, the first transformer capable of stepping down the input voltage to a predetermined voltage and the second transformer capable of stepping up and down the input voltage at a predetermined ratio In a test mode, a central processing unit provided as a part of a functional block controls these transformer circuits in accordance with a self-test program to automatically generate an operating voltage for a voltage margin test.
[0015]
Thus, in the semiconductor integrated circuit device, when performing the voltage margin test, the operating voltage for the voltage margin test can be easily and accurately controlled within a wide range in the semiconductor integrated circuit device.
[0016]
Therefore, when performing the voltage margin test of the semiconductor integrated circuit device, the tester does not need to control the input voltage to the semiconductor integrated circuit device in detail for each condition of the voltage margin test. It is only necessary to control to input.
[0017]
Therefore, it is not necessary to use a high-performance tester capable of handling complicated voltage control, that is, an expensive tester, so that a voltage margin test can be performed using a low-cost, simple-function tester. .
[0018]
Therefore, in this semiconductor integrated circuit device, the operating voltage for the voltage margin test is controlled in the semiconductor integrated circuit device irrespective of the performance of the tester, and the voltage margin test is performed autonomously and inexpensively and easily. can do.
[0019]
In addition, the operating voltage pattern for effective voltage margin testing can be automatically generated under the control of the central processing unit according to the test program, eliminating the need to replace testers depending on the test object or product specifications. It is.
[0020]
Therefore, in this semiconductor integrated circuit device, the operating voltage for the voltage margin test is controlled within the semiconductor integrated circuit device regardless of the performance of the tester, and the voltage margin test is efficiently and autonomously performed in a short time. can do.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a semiconductor integrated circuit device according to the present invention will be described below in detail with reference to the accompanying drawings.
[0022]
Embodiment 1 FIG.
FIG. 1 is a block diagram illustrating a configuration of a one-chip microcomputer 100 which is a semiconductor integrated circuit device according to a first embodiment and has a function of performing a voltage margin test autonomously. In FIG. 1, a one-chip microcomputer includes a first transformer 14 for performing a step-up conversion or a step-down conversion to a predetermined voltage using a power supply voltage input from the outside as a reference voltage, and a power supply voltage converted in the first transformer. A second transformer circuit 8 which performs step-up conversion or step-down conversion at a predetermined ratio as a reference voltage and outputs the same; a function block 7 which uses a predetermined internal voltage as an operation power supply; and a self-test program (hereinafter simply referred to as a test) in a test mode. An external input signal is input from a ROM 12 storing an external input terminal (not shown), and the external input signal is output to the functional block 7 in synchronization with a predetermined operation clock signal. The output control circuit 4 is provided on the same semiconductor chip (semiconductor substrate). Here, a DA converter is used as the first transformer circuit 14.
[0023]
The functional block 7 includes a CPU 13 that controls operations in a normal mode and a test mode for performing a voltage margin test of the functional block, a ROM 5 that is used as a memory in the normal mode and stores a program and the like in the normal mode, and a timer circuit. 6 is provided.
[0024]
The first transformer 14, the second transformer 8, the ROM 12, the CPU 13, and the ROM 5 are connected to each other via the internal path 11. The data input / output control circuit 4 is connected to the first and second transformer circuits 14 and 8, and the timer circuit 6 is connected to the ROM 5. The ROM 5, the timer circuit 6, the CPU 13, and the ROM 12 receive the operating voltage 9 for the voltage margin test output from the second transformer circuit 8, and the first transformer circuit 14, the second transformer circuit 8, The internal power supply voltage 10 is input to the data input / output control circuit 4.
[0025]
In the above configuration, in the normal mode, the CPU 13 reads a predetermined program from the ROM 5 according to a control signal input from the outside via the data input / output control circuit 4, and executes a predetermined calculation process and the like.
[0026]
When a reset signal is input, the CPU 13 switches to the test mode according to a predetermined program stored in the ROM 5 in advance, reads a predetermined test program from the ROM 12, and executes a voltage margin test. When the voltage margin test is completed, the test mode is ended according to the normal mode switching signal written in the test program, and the mode shifts to the normal mode.
[0027]
Next, an operation example of the one-chip microcomputer 100 shown in FIG. 1 in the test mode will be described with reference to the flowchart of FIG.
[0028]
In FIG. 2, the CPU 13 is reset when a predetermined voltage and clock frequency are input from the tester 1 in step S1. Then, in step S 2, the mode is switched to a test mode for performing a voltage margin test of the functional block 7 in accordance with a predetermined program stored in the ROM 5 in advance, and a predetermined test program is read from the ROM 12.
[0029]
Next, in step 3, the external power supply voltage 3 controlled to a constant voltage is input from the tester 1. Then, the external power supply voltage 3 is input as the internal power supply voltage 10 to the first transformation circuit 14, the second transformation circuit 8, and the data input / output control circuit 4 to drive them.
[0030]
Further, the external power supply voltage 3 controlled from the tester 1 and controlled to a constant voltage is converted into a predetermined voltage in the first and second transformer circuits 14 and 8 as described later, and the voltage margin test is performed. Operating voltage 9 is input to each circuit of the functional block 7 and serves as a power supply for driving these.
[0031]
Here, in step 4, the CPU 13 controls the first transformer circuit 14 by inputting a predetermined control signal to the DA converter which is the first transformer circuit 14 in accordance with the test program read from the ROM 12, and controls the internal power supply. The voltage 10 is converted to a predetermined voltage as a reference voltage. Then, the first transformer 14 outputs the converted predetermined voltage to the second transformer 8 as an analog output 15.
[0032]
Next, in step 5, the second transformer circuit 8 converts the analog output from the first transformer circuit 14 as a reference voltage 16 and further converts the analog output at a predetermined ratio so as to conform to the operating voltage for the voltage margin test. Generates the operating voltage 9 for the voltage margin test. At this time, the conversion ratio in the second transformer circuit 8 is controlled by the CPU 13 in accordance with the test program read from the ROM 12.
[0033]
Then, the operating voltage 9 for the voltage margin test generated in the second transformer circuit 8 is input to each semiconductor circuit of the function block 7 which is the test target module in step 6.
[0034]
Next, in step S7, the CPU 13 jumps to the start address of the test program stored in the ROM 12, executes the program, and executes the test program from step S8.
[0035]
In step S8, an index provided for each test target module is counted, and an index counter i used to determine whether or not the test has been completed in all test target modules is set to 1.
[0036]
Next, in step S9, the CPU 13 autonomously checks the operation of the test target module i corresponding to the counter value of the index counter i, that is, the test target module 1, that is, the voltage margin test. Is self-determined. If there is no abnormality in the operation check (YES), the module to be tested is determined to be non-defective, and the index counter i is incremented in step S10.
[0037]
If an abnormality is found in step S9 (NO), that is, if an error occurs in the operation check, the module to be tested is determined to be defective, and the process proceeds to step S11. After executing the error processing routine to be performed and performing predetermined processing, the process proceeds to step S10. Since the contents of the error processing routine are not directly related to the present invention, the description thereof is omitted here.
[0038]
Further, in step S12, the CPU 13 checks whether or not the counter value of the index counter i is a predetermined value A indicating that the tests of all the test target modules have been completed. Here, if the counter value of the index counter i has reached the predetermined value A (YES), the test mode ends in step S13, and this flow ends.
[0039]
If the counter value of the index counter i is not the predetermined value A in step S12 (NO), that is, if it is less than the predetermined value A, the process returns to step S9.
[0040]
As described above, the voltage margin test of the one-chip microcomputer 100 can be performed autonomously.
[0041]
Here, in Steps 4 to 12, the operating voltage is changed under the control of the CPU 13 according to the specifications of the module to be tested, ie, each semiconductor circuit of the functional block, so as to conform to a test point that includes the specifications. It is carried out repeatedly while being performed. At this time, the first power supply circuit 14 and the second power supply circuit 8 convert the external power supply voltage input from the tester 1 so as to conform to each condition of the voltage margin test as described above, so that the voltage margin is changed. Generate test operating voltage. The conversion of the voltage is controlled by the CPU 13 in accordance with the test program read from the ROM 12.
[0042]
That is, in the one-chip microcomputer 100, when the operation margin test is autonomously performed in the one-chip microcomputer 100 as described above, the control of the conversion of the voltage from the external power supply voltage to the operation voltage for the voltage margin test is controlled. Is performed by the CPU 13 provided as a part of the functional block 7.
[0043]
Therefore, the tester 1 does not need to basically control the external power supply voltage 3 in detail for each voltage margin test condition, but only needs to control the external power supply voltage 3 to input an external voltage within a predetermined range. The configuration has been greatly reduced.
[0044]
As described above, the first voltage transformer 14 capable of stepping down the input voltage to a predetermined voltage and the second voltage transformer 8 capable of stepping up / down the input voltage at a predetermined ratio are combined, and the external power supply voltage from the tester 1 is combined. By appropriately controlling 3, the operating voltage for the voltage margin test can be easily and accurately controlled in a wide range in the one-chip microcomputer 400 irrespective of the tester 1.
[0045]
When the module to be tested, that is, each semiconductor circuit of the functional block 7 has a high function and the product specifications are complicated, the number of test points increases, and the control of the operating voltage for the voltage margin test becomes complicated. . Therefore, when performing a voltage margin test of a conventional one-chip microcomputer, a high-performance tester capable of coping with complicated voltage control, that is, an expensive tester is required, and the test cost increases.
[0046]
However, when performing the voltage margin test of the one-chip microcomputer 100 as described above, the tester 1 only needs to control to input the external power supply voltage 3 in a predetermined range. As a result, it is not necessary to use a high-performance tester that can handle complicated voltage control, that is, an expensive tester, so that a voltage margin test can be performed using a low-cost, simple-function tester. It is.
[0047]
Therefore, in the one-chip microcomputer 100, the operating voltage for the voltage margin test is controlled in the one-chip microcomputer 100 regardless of the tester 1, and the autonomous voltage margin test can be performed inexpensively and simply. It is possible to effectively reduce the test cost.
[0048]
In addition, when performing a voltage margin test of a conventional one-chip microcomputer, a plurality of testers must be prepared according to the type of the specification of the semiconductor circuit to be tested, and the tester must be replaced depending on the test target. The test work becomes complicated and the test time becomes longer.
[0049]
However, when the operation margin test of the one-chip microcomputer 100 is performed, the CPU 13 automatically generates an operation voltage pattern for an effective voltage margin test under the control of the test program read from the ROM 12. No need to replace tester depending on test object or product specifications. Therefore, in the one-chip microcomputer 100, the operating voltage for the voltage margin test is controlled in the one-chip microcomputer 100 regardless of the tester 1, and the voltage margin test is efficiently and autonomously performed in a short time. Is possible.
[0050]
Further, since a voltage margin test is performed using the CPU 13 provided in the functional block 7 to perform arithmetic processing and the like in the normal mode, it is not necessary to provide a CPU dedicated to the voltage margin test, and the size of the one-chip microcomputer 100 is reduced. It is possible to incorporate the function of the tester into the one-chip microcomputer 100 while suppressing the increase in
[0051]
Hereinafter, a specific example of generating an operating voltage for a voltage margin test in the one-chip microcomputer 100 will be described. For example, an external power supply voltage of 5 V is input from the tester 1 as a power supply. Here, the DA converter as the first transformer 14 is controlled by the CPU 13 so that the DA converter has an 8-bit configuration and has a reference potential of 5 V, and the second transformer 8 outputs a constant voltage twice the reference voltage. And In this case, when the CPU 13 inputs 3Ch as a digital input value to the DA converter which is the first transformer circuit 14 according to the test program stored in the ROM 12, the output from the first transformer circuit 14 becomes 1.25V. . Then, since 1.25 V which is the output from the first transformer circuit 14 is input to the second transformer circuit 8 as a reference voltage, the output from the second transformer circuit 8 becomes 2.5 V, This is applied to the function block 7 as an operating voltage for a voltage margin test.
[0052]
The product standard of the module to be tested is, for example, as shown in FIG. 3, an internal source voltage: 3 V ± 10%, a maximum frequency of 20 MHz, a test point 20 of 3.6 V as a high voltage side test voltage, and a low voltage. When performing a voltage margin test at a test point 21 of 2.5 V as a side test voltage, the CPU 13 uses a test program stored in the ROM 12 as a digital input value to a DA converter that is the first transformer circuit 14. What is necessary is just to program so that 5Ch and 3Ch may be input.
[0053]
Embodiment 2 FIG.
Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram illustrating a schematic configuration of a one-chip microcomputer 200 which is a semiconductor integrated circuit device according to a second embodiment and has a function of performing a frequency margin test autonomously. Note that components not directly related to the frequency margin test are omitted for easy understanding.
[0054]
In FIG. 4, a one-chip microcomputer 200 includes a multiplying circuit 18 for multiplying an externally input frequency clock by a predetermined factor, a functional block 7 using a predetermined frequency clock as an operating frequency, and a test program in a test mode. The stored ROM 12 is provided on the same semiconductor chip (semiconductor substrate). Here, a phase locked loop (PLL) circuit is used as the multiplying circuit 18.
[0055]
The functional block 7 includes a CPU 13 that controls operation in a normal mode and a test mode in which a frequency margin test of the functional block functional block is performed; a ROM 5 that is used as a memory in the normal mode and stores a program and the like in the normal mode; And a timer circuit 6.
[0056]
The multiplying circuit 18, the ROM 12, the CPU 13, and the ROM 5 are connected to each other via the internal path 11.
[0057]
In the above configuration, in the normal mode, the CPU 13 reads a predetermined program from the ROM 5 according to a control signal input from the outside via a data input / output control circuit (not shown) and executes a predetermined calculation process and the like. .
[0058]
When a reset signal is input, the CPU 13 switches to the test mode according to a predetermined program stored in the ROM 5 in advance, reads a predetermined test program from the ROM 12, and autonomously executes a frequency margin test. When the frequency margin test is completed, the test mode is terminated according to the normal mode switching signal written in the test program, and the mode shifts to the normal mode.
[0059]
Next, an operation example in the test mode in the one-chip microcomputer 200 shown in FIG. 4 will be described with reference to the flowchart in FIG.
[0060]
In FIG. 5, the CPU 13 is reset when a predetermined voltage and frequency clock signal is input from the tester 1 in step S21. In step S22, the mode is switched to the test mode for performing the frequency margin test of the functional block 7 according to the predetermined program stored in the ROM 5 in advance, and the predetermined test program is read from the ROM 12.
[0061]
Next, in step 23, the external clock signal 22 controlled to a constant frequency is input from the tester 1 into the one-chip microcomputer 200. The input external clock signal 22 is input to the multiplying circuit 18 as an internal clock signal 23.
[0062]
Here, in step 24, the CPU 13 controls the number of multiplications in the multiplying circuit 18 by inputting a predetermined control signal to the PLL circuit which is the multiplying circuit 18 in accordance with the test program read from the ROM 12. The converted external clock signal 22 is converted by a predetermined multiple to generate an operation clock signal 17 for a frequency margin test having a predetermined frequency. Here, for example, an operation clock signal having a frequency that satisfies the product specifications can be obtained by programming the test program so that the CPU 13 can select a desired multiplication number such as 2 ×, 4 ×, 8 ×, or 16 ×. Can be generated.
[0063]
Then, in step 25, the multiplying circuit 18 inputs the generated operation clock signal 17 for the frequency margin test to each semiconductor circuit of the functional block 7 which is a test target module.
[0064]
Next, in step S26, the CPU 13 jumps to the start address of the test program stored in the ROM 12, executes the program, and executes the test program in and after step S27.
[0065]
In step S27, an index provided for each test target module is counted, and an index counter i used to determine whether or not the test has been completed in all test target modules is set to 1.
[0066]
Next, in step S28, the CPU 13 autonomously checks the operation of the test target module i corresponding to the counter value of the index counter i, that is, the test target module 1, that is, the frequency margin test. Is self-determined. If there is no abnormality in the operation check (YES), the module to be tested is determined to be non-defective, and the index counter i is incremented in step S29.
[0067]
If an abnormality is found in step S28 (NO), that is, if an error occurs in the operation check, the module to be tested is determined to be defective, and the process proceeds to step S30. In step S30, processing for the error is performed. After performing an error processing routine to perform predetermined processing, the process proceeds to step S29. Since the contents of the error processing routine are not directly related to the present invention, the description thereof is omitted here.
[0068]
Further, in step S31, the CPU 13 checks whether or not the counter value of the index counter i is a predetermined value A indicating that the tests of all the test target modules have been completed. Here, if the counter value of the index counter i has reached the predetermined value A (YES), the test mode ends in step S32, and this flow ends.
[0069]
In step S31, if the counter value of the index counter i is not the predetermined value A (NO), that is, if it is less than the predetermined value A, the process returns to step S28.
[0070]
As described above, the frequency margin test of the one-chip microcomputer 200 can be performed autonomously.
[0071]
Here, in steps 24 to 31, the operation clock signal is adjusted under the control of the CPU 13 so as to conform to a test point that includes the specification according to the specification of the module to be tested, that is, each semiconductor circuit of the functional block. It is repeated while changing. At this time, the operation clock signal 17 for the frequency margin test is generated by converting the external clock signal input from the tester 1 in the multiplication circuit 18 so as to meet each condition of the frequency margin test as described above. . The conversion of the clock signal is controlled by the CPU 13 according to the test program read from the ROM 12.
[0072]
That is, in the one-chip microcomputer 200, when the frequency margin test is autonomously performed in the one-chip microcomputer 200 as described above, the control of the conversion of the frequency from the external clock signal to the operation clock signal for the frequency margin test is performed. Is performed by the CPU 13 provided as a part of the functional block 7.
[0073]
Therefore, the tester 1 basically does not need to control the frequency of the external clock signal 22 in detail for each frequency margin test condition, but only needs to control the input of the external clock signal within a predetermined range. The load is greatly reduced.
[0074]
As described above, by using the multiplying circuit 18 capable of multiplying the input clock signal to a clock signal of a predetermined frequency and appropriately controlling the external clock signal 22 from the tester 1, the operation for the frequency margin test can be performed. The clock signal 17 can be easily and accurately controlled in a wide frequency range.
[0075]
When the module to be tested, that is, each semiconductor circuit of the functional block 7 becomes highly functional and the product specification becomes complicated, the number of test points increases, and the control of the operation clock signal for the frequency margin test becomes complicated. Become. For this reason, when performing a frequency margin test of a conventional one-chip microcomputer, a high-performance tester that can cope with complicated frequency clock control, that is, an expensive tester is required, and the test cost increases.
[0076]
However, when performing the frequency margin test of the one-chip microcomputer 200 as described above, the tester 1 only needs to control the input of the external clock signal 22 in a predetermined range. As a result, it is not necessary to use a high-performance tester that can handle complicated control of the frequency of the clock signal, that is, an expensive tester, so the frequency margin test is performed using a low-cost, simple-function tester. It is possible to do.
[0077]
Therefore, the one-chip microcomputer 200 controls the frequency of the operation clock signal for the frequency margin test in the one-chip microcomputer 200 irrespective of the tester 1 to autonomously perform the frequency margin test inexpensively and easily. It can be implemented, and the test cost can be effectively reduced.
[0078]
In addition, when performing a frequency margin test of a conventional one-chip microcomputer, a plurality of testers must be prepared according to the type of the specification of the semiconductor circuit to be tested, and the tester must be replaced depending on the test target. The test work becomes complicated and the test time becomes longer.
[0079]
However, when the operation margin test of the one-chip microcomputer 200 is performed, the operation clock signal pattern for the effective frequency margin test is automatically generated under the control of the CPU 13 according to the test program read from the ROM 12. There is no need to replace the tester depending on the test object or the product specifications.
[0080]
Therefore, in the one-chip microcomputer 200, the frequency of the operation clock signal for the frequency margin test is controlled within the one-chip microcomputer 200 regardless of the tester 1, so that the frequency margin test can be efficiently and autonomously performed in a short time. It is possible to implement.
[0081]
Further, since a frequency margin test is performed using the CPU 13 provided in the functional block 7 to perform arithmetic processing and the like in the normal mode, there is no need to provide a CPU dedicated to the frequency margin test, and the size of the one-chip microcomputer 200 is reduced. It is possible to incorporate the function of the tester into the one-chip microcomputer 200 while suppressing the increase in
[0082]
Hereinafter, a specific example of generating an operation clock signal for a frequency margin test in the one-chip microcomputer 200 will be described. For example, consider a case where a frequency margin test is performed at a high-speed test frequency of 22 MHz and a low-speed test frequency of 2.75 MHz as an operation clock signal for a frequency margin test that satisfies the specification of a maximum frequency of 20 MHz.
[0083]
A clock signal having a constant frequency of, for example, 1.375 MHz is input from the tester 1 as an external clock signal. Here, it is assumed that a test program stored in the ROM 12 is designed so that the multiplication number can be switched among the multiplication numbers of 2, 4, 8, and 16 in the multiplication circuit 18 under the control of the CPU 13.
[0084]
In this case, the CPU 13 controls the multiplication circuit 18 to select the multiplication number of 16 or 2 so that a clock signal of 22 MHz or 2.75 MHz is output from the multiplication circuit 18, and this is output to the frequency margin test. Is input to the functional block 7 as an operation clock signal.
[0085]
Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing a schematic configuration of a one-chip microcomputer 300 which is a semiconductor integrated circuit device according to the third embodiment and has a function of performing a voltage margin test and a frequency margin test autonomously.
[0086]
The one-chip microcomputer 300 according to the present embodiment illustrated in FIG. 6 has a configuration in which the one-chip microcomputer 100 according to the above-described first embodiment and the one-chip microcomputer 200 according to the second embodiment are combined. It is. That is, the one-chip microcomputer 300 according to the present embodiment has the effects described in the first and second embodiments.
[0087]
Therefore, this one-chip microcomputer 300 controls the operating voltage for the voltage margin test and the frequency of the operation clock signal for the frequency margin test in the one-chip microcomputer 300 irrespective of the tester 1 so as to be inexpensive and simple. In addition, the voltage margin test and the frequency margin test can be performed autonomously. Further, in the one-chip microcomputer 300, the operating voltage for the voltage margin test and the frequency of the operation clock signal for the frequency margin test are controlled within the one-chip microcomputer 300 regardless of the tester 1, so that the short-time operation can be efficiently performed. Thus, the voltage margin test and the frequency margin test can be performed autonomously.
[0088]
Embodiment 4 FIG.
Next, a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram illustrating a schematic configuration of a one-chip microcomputer 400 which is a semiconductor integrated circuit device according to a fourth embodiment and has a function of performing a voltage margin test autonomously.
[0089]
The one-chip microcomputer 400 according to the present embodiment illustrated in FIG. 7 is configured such that the one-chip microcomputer 100 according to the above-described first embodiment includes the output terminal 19 of the operating voltage for a voltage margin test.
[0090]
That is, the one-chip microcomputer 400 has the effects described in the first embodiment. Since the one-chip microcomputer 400 includes the output terminal 19 of the operating voltage for the voltage margin test, the operating voltage 9 for the voltage margin test can be confirmed outside the one-chip microcomputer 400. As a result, it is possible to confirm whether or not the voltage margin test is performed reliably, and a highly reliable voltage margin test function is realized.
[0091]
【The invention's effect】
As described above, according to the present invention, the operating voltage for the voltage margin test can be easily and accurately controlled in a wide range in the semiconductor integrated circuit device, and therefore the internal voltage of the built-in semiconductor circuit can be easily controlled. The self-test of the operation margin can be performed inexpensively and efficiently, and the test cost can be effectively reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a one-chip microcomputer 100 according to a first embodiment.
FIG. 2 is a flowchart illustrating an operation example in a test mode in the one-chip microcomputer 100;
FIG. 3 is a diagram illustrating test points in a voltage margin test.
FIG. 4 is a block diagram showing a schematic configuration of a one-chip microcomputer 200 according to a second embodiment.
FIG. 5 is a flowchart illustrating an operation example in a test mode in the one-chip microcomputer 200;
FIG. 6 is a block diagram showing a schematic configuration of a one-chip microcomputer 300 according to a third embodiment.
FIG. 7 is a block diagram showing a schematic configuration of a one-chip microcomputer 400 according to a fourth embodiment.
[Explanation of symbols]
Reference Signs List 1 tester, 3 external power supply voltage, 4 data input / output control circuit, 5 ROM, 6 timer circuit, 7 functional blocks, 8 second transformer circuit, 9 operating voltage for voltage margin test, 10 internal power supply voltage, 11 internal path , 12 ROM, 13 CPU, 14 first transformer circuit, 17 operation clock signal for frequency margin test, 18 multiplier circuit, 19 output terminal, 20, 21 test points, 22 external clock signal, 23 internal clock signal.

Claims (4)

A semiconductor integrated circuit device having a self-test function for autonomously testing an operation margin with respect to an internal voltage fluctuation of a built-in semiconductor circuit,
A functional block including a semiconductor circuit including a central processing unit;
A memory storing a self-test program for performing a self-test of the semiconductor circuit in the functional block,
A first transformer circuit that converts a power supply voltage input from the outside into a predetermined voltage and outputs the converted voltage;
A second transformer circuit that converts an output from the first transformer circuit at a predetermined ratio and outputs it as an operating voltage for self-test to the functional block;
With
The central processing unit controls the voltages output from the first and second transformer circuits according to the self-test program in a test mode in which the self-test is performed, and autonomously controls the self-test of the semiconductor circuit. A semiconductor integrated circuit device for performing a test. 2. The semiconductor integrated circuit device according to claim 1, further comprising output means for outputting the operating voltage. A semiconductor integrated circuit device having a built-in self-test function for autonomously testing an operation margin with respect to a clock frequency fluctuation of a built-in semiconductor circuit,
A functional block including a semiconductor circuit including a central processing unit;
A memory storing a self-test program for performing a self-test of the semiconductor circuit in the functional block,
A multiplying circuit for multiplying a clock input from the outside to a predetermined frequency and outputting the same as an operation clock for self-test to the functional block;
With
A semiconductor, wherein the central processing unit controls a multiplication factor in the multiplying circuit according to the self-test program and autonomously performs a self-test of the semiconductor circuit in a test mode in which a self-test is performed. Integrated circuit device. 4. The semiconductor integrated circuit device according to claim 3, wherein said multiplying circuit is a phase locked loop circuit.

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