JP2009010913A - Delay circuit, and delay time adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay circuit and a delay time adjustment method which can easily adjust and change a delay time in signal transmission in interconnections of a wiring board such as a mounting board or a semiconductor package, and can be adapted to miniaturization and high density mounting of the wiring board. <P>SOLUTION: A delay circuit 1 includes an interface 11 for giving a command of setting a delay time and a delay device 12 programmable to be set to any desired delay time. The delay time of the delay device 12 is set according to the command from the interface 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a delay circuit and a delay time adjusting method for adjusting a signal propagation delay time of each wiring of a wiring board such as a mounting board or a semiconductor package.

  Despite the simultaneous transmission of signals on the transmission side of each wiring board used for mounting boards and semiconductor packages, signals are received on the reception side due to the type of load between patterns and the difference in pattern length. There is a “skew” that arrives with variations. Various means for adjusting the delay time of signal propagation have been developed to eliminate such skew. For example, there is a method of adjusting the wiring length of another wiring pattern by inserting a meander pattern in order to match the wiring length of the longest wiring pattern.

  Further, for example, in a semiconductor integrated circuit package containing a semiconductor integrated circuit, a delay element having an electrical delay time is provided between the input / output pin of the semiconductor integrated circuit and the pin of the semiconductor integrated circuit package connected to the input / output pin. There is a method in which a delay element accommodating portion for detachably accommodating is provided, a delay element having a necessary delay time is mounted on the delay element accommodating portion, and thereby the delay time is adjusted (for example, see Patent Document 1).

  In addition, for example, a semiconductor integrated circuit package having a structure in which an insulating material is filled in an input / output buffer of a semiconductor integrated circuit chip and a heat radiation lead wire is disposed thereon (see, for example, Patent Document 2). According to this, the delay time is adjusted by adjusting the heat radiation amount from the heat radiation lead wire.

  Further, for example, a method has been proposed in which an appropriate capacitive load is applied to a wiring pattern to obtain a required delay time (see, for example, Patent Documents 3 and 4).

  Further, for example, a method of adjusting the delay time by changing the dielectric constant of the insulator around the wiring pattern has been proposed (see, for example, Patent Document 5).

  For example, a delay time adjustment method using a fixed resistor has been proposed (see, for example, Patent Document 6).

JP-A-5-175415 Japanese Patent Laid-Open No. 8-12573 Japanese Patent Laid-Open No. 5-63315 Japanese Patent No. 3415830 JP 2004-356251 A Japanese Patent Laid-Open No. 11-135920

  The method of adjusting the delay time by inserting a meander pattern is disadvantageous for a semiconductor integrated circuit of high density mounting because the meander pattern requires a large space on the substrate.

  Further, according to the technique described in Patent Document 1 (that is, Japanese Patent Application Laid-Open No. 5-175415), it is necessary to prepare a delay element for each delay time. If the delay element is mounted in the delay element housing portion and incorporated in the semiconductor integrated circuit package, the delay time cannot be changed thereafter. In addition, it is difficult to reduce the size of the semiconductor integrated circuit package because of the structure in which the delay element is mounted in the delay element housing portion. Furthermore, there are two electrical contacts for mounting the delay element in the delay element accommodating portion, and this electrical contact may cause a contact failure.

  In addition, according to the technique described in Patent Document 2 (that is, Japanese Patent Application Laid-Open No. 8-12573), in order to keep the set delay time constant, it is necessary to keep the heat radiation amount from the heat radiation lead wire constant. However, for this reason, a mechanism for keeping the temperature around the semiconductor integrated circuit package constant is required. Therefore, it is difficult to apply this technique to a small device. Also, it is difficult to apply to applications in which the amount of heat generated by the chip varies greatly depending on the operating conditions of the semiconductor integrated circuit chip.

  Further, according to the technique described in Patent Document 3 (that is, JP-A-5-63315), it is easy to delete the delay pad, but it is difficult to add the delay pad. Therefore, the delay time once set can be reduced. But it is difficult to increase. In addition, the capacitive load must be designed to be contained within the substrate, and the process management for that purpose is costly. Further, it is not suitable for a semiconductor integrated circuit mounted with high density.

  Further, according to Patent Document 4 (that is, Japanese Patent No. 3415830), since the capacitive load is separated by laser cutting in order to adjust the delay time, the delay time once set can be reduced. It is impossible to increase. There is also a need for equipment for measuring the delay time and a laser device for disconnecting the capacitive load from the outside.

  In addition, according to the technique described in Patent Document 5 (that is, Japanese Patent Application Laid-Open No. 2004-356251), an insulating material must be selected in order to obtain a desired delay time, and a desired delay time can be reduced. Cost is required for process management to obtain. In addition, the delay time cannot be changed or adjusted after manufacturing.

  Further, according to the technique described in Patent Document 6 (that is, JP-A-11-135920), since the waveform observation terminal and the clock input circuit have a stub structure, signal reflection occurs due to the stub structure. Signal quality deteriorates. Further, since it is impossible to match the output impedance of the clock output circuit and the characteristic impedance of the clock path, it is not suitable for high-frequency signal transmission.

  Therefore, in view of the above problems, an object of the present invention is to easily adjust and change the signal propagation delay time of each wiring of a wiring board such as a mounting board or a semiconductor package, and to reduce the size and density of the wiring board. It is an object of the present invention to provide a delay circuit and a delay time adjustment method that can also be implemented.

  In order to achieve the above object, according to the delay time adjusting method of the present invention, based on the signal propagation time measured in advance for each wiring of the wiring board for which the delay time is to be set, the input terminal of each wiring of the wiring board is used. The delay time of the signal propagation of each wiring of the wiring board is adjusted by programming the delay time of a delay element that can be programmed to an arbitrary delay time provided as a delay circuit at each of the output terminals.

  More specifically, in the delay time adjusting method according to the first aspect of the present invention, in the measurement mode, the delay time is set from the terminal to which the delay circuit is to be connected of each wiring of the wiring board to which the delay time is to be set. A transmission step of transmitting a propagation time measurement signal toward the wiring of the wiring substrate to be received, and a reception step of receiving a propagation time measurement signal reflected on the wiring of the wiring substrate to which the delay time is set in the measurement mode In the measurement mode, the time difference between the time when the reception means receives the propagation time measurement signal and the time when the signal generator transmits the propagation time measurement signal is calculated, and half the time difference is calculated as A measurement step that measures the signal propagation time for the wiring on the wiring board where the delay time should be set, and the largest signal among the signal propagation times measured for each wiring on the wiring board A calculation step for determining the time difference between the sowing time and the signal propagation time measured for the wiring of the wiring board for which the delay time is to be set as the delay time of the wiring of the wiring board for which the delay time is to be set; A setting step for programming the delay time determined by the calculation step to a delay element that is provided as a delay circuit connected to the wiring and can be programmed to an arbitrary delay time.

  The delay time adjustment method according to the second aspect of the present invention is directed to the measurement reference wiring connected to the measurement terminal from the measurement terminal provided on the wiring board to set the delay time in the measurement mode. A transmission step for transmitting a propagation time measurement signal, a reception step for receiving a propagation time measurement signal reflected from the reference wiring for measurement in the measurement mode, and a propagation time measurement in the reception step in the measurement mode. A measurement step of measuring a time difference between the time at which the signal is received and the time at which the transmission time measurement signal is transmitted in the transmission step, and measuring half the time difference as the signal propagation time for the measurement reference wiring; Estimate using the signal propagation time for the measurement reference wiring from the ratio of the wiring design length of the wiring board to which the delay time should be set and the length of the measurement reference wiring The delay time is set by the time difference between the maximum signal propagation time of the signal propagation times for each wiring of the printed wiring board and the signal propagation time estimated for the wiring of the wiring board for which the delay time should be set. A calculation step for determining the delay time of the wiring of the power wiring board, and a setting step for programming the delay time to a delay element that is provided as a delay circuit connected to the wiring of the wiring board and can be programmed to an arbitrary delay time; .

  According to the present invention, the delay circuit for adjusting the signal propagation delay time of each wiring of the wiring board includes an interface for instructing the setting of the delay time, a delay element programmable to an arbitrary delay time, The delay time of the delay element is set by an instruction from the interface. This interface is, for example, a JTAG (Joint Test Action Group) interface. The JTAG interface will be described later.

  More specifically, the delay circuit according to the first aspect of the present invention includes a delay element programmable to an arbitrary delay time connected to each of the input end and the output end of each wiring of the wiring board. Each delay element should set a delay time in the measurement mode and a signal generator that transmits a propagation time measurement signal toward the wiring of the wiring board where the delay time should be set in the measurement mode. The receiving means for receiving the propagation time measurement signal reflected on the wiring of the wiring board, the time when the receiving means received the propagation time measurement signal in the measurement mode, and the signal generator transmitting the propagation time measurement signal. Measuring means for measuring the time difference between the time and the signal propagation time measured for each wiring on the wiring board, with the time half of the time difference being the signal propagation time for the wiring of the wiring board on which the delay time should be set The time difference between the maximum signal propagation time and the signal propagation time measured for the wiring of the wiring board for which the delay time is to be set is the wiring difference of the wiring board for which the delay time is to be set. It has a calculating means for programming the delay element as length of time, the.

  The delay circuit according to the first aspect of the present invention is provided on a wiring board on which wiring for setting a delay time is mounted. Then, the wiring board provided with the delay circuit according to the first aspect of the present invention and the wiring board provided with the delay circuit according to the first aspect of the present invention are connected to each other via each delay circuit. By connecting, the signal propagation time for the wiring of one wiring board is measured, and an appropriate delay time is set using the measured signal propagation time.

  The delay circuit according to the second aspect of the present invention includes a delay element that can be programmed to an arbitrary delay time and is connected to each of an input end and an output end of each wiring of the wiring board, and a wiring to set the delay time. A measuring element for measuring a signal propagation time of a reference wiring for measurement provided on the substrate. Then, the measurement element is reflected in the measurement reference wiring in the measurement mode and the signal generator that transmits the propagation time measurement signal toward the measurement reference wiring connected to the measurement element in the measurement mode. Measures the time difference between the receiving means that receives the propagation time measurement signal and the time when the receiving means receives the propagation time measurement signal and the time when the signal generator sends the propagation time measurement signal in the measurement mode. Then, measure the half of the time difference from the ratio of the measurement means that uses the signal propagation time for the measurement reference wiring and the wiring design length of the wiring board to set the delay time to the length of the measurement reference wiring. The maximum signal propagation time among the signal propagation times for each wiring of the wiring board estimated using the signal propagation time for the reference wiring for the wiring, and the wiring of the wiring board for which the delay time should be set Signal propagation time estimated with the time difference, has a calculating means for programming the delay elements as the delay time of the wiring board to be set the delay time line, the.

  The delay circuit according to the second aspect of the present invention is provided on a wiring board on which a wiring whose delay time is to be set is mounted. In addition, a measurement reference wiring is further provided on the wiring board provided with the delay circuit according to the second aspect of the present invention. Then, the signal propagation time for the measurement reference wiring is measured, and an appropriate delay time is set using the measured signal propagation time.

  In the first and second aspects of the present invention described above, when the wiring board is, for example, a mounting board on which a plurality of semiconductor packages are mounted, each wiring of the wiring board connects between the semiconductor packages. Each wiring of the mounting substrate corresponds. In this case, since a semiconductor chip is mounted on each semiconductor package, each wiring on the wiring board eventually corresponds to each wiring on the mounting board that connects the semiconductor chips.

  As another example, when the wiring board is a semiconductor package on which a plurality of semiconductor chips are mounted, each wiring of the wiring board corresponds to each wiring of the semiconductor package that connects the semiconductor chips.

  According to the present invention, since the signal propagation delay time of each wiring of the wiring board can be set by an electrical method, the delay time can be easily adjusted and changed many times. Further, according to the present invention, the skew of the wiring board can be easily measured, and a highly accurate delay circuit can be easily configured based on the measurement result. Furthermore, it is possible to realize a delay circuit that can cope with downsizing and high-density mounting of the wiring board.

  Further, according to the present invention, if a circuit for instructing execution of processing for adjusting and changing the delay time of the delay circuit is provided on the wiring board and connected to the JTAG interface in the delay circuit, the JTAG interface is used. The delay time of the delay circuit can be easily set or changed.

  According to the present invention, there is no need to prepare a delay element for each delay time as in the technique described in Patent Document 1 (that is, Japanese Patent Laid-Open No. 5-175415). Since there is no electrical contact for mounting in the housing, there is no fear of causing contact failure.

  Further, according to the present invention, the delay time is not adjusted by adjusting the heat radiation amount of the heat radiating lead as in the technique described in the above-mentioned Patent Document 2 (that is, Japanese Patent Laid-Open No. 8-125073). Therefore, a mechanism for keeping the temperature around the wiring board constant is unnecessary, and it is difficult to be affected by changes in ambient temperature.

  Further, according to the present invention, a capacitive load or meander pattern like the technique described in the above-mentioned Patent Document 3 (that is, JP-A-5-63315) and the above-mentioned Patent Document 4 (that is, Patent No. 3415830). Therefore, it is not necessary to mount a passive element such as a wiring board on the wiring board, so that the wiring space can be effectively used and the wiring board can be applied to a high-density mounting wiring board.

  Further, according to the first aspect of the present invention, by connecting the wiring board provided with the delay circuit and the wiring board provided with the delay circuit similarly to each other through each delay circuit, The signal propagation time for the wiring on one wiring board is measured, and an appropriate delay time is set using the measured signal propagation time. Therefore, a special jig or measuring device for adjusting or changing the delay time is used. Not required externally.

  Further, according to the second aspect of the present invention, the delay circuit and the measurement reference wiring are provided on the wiring board on which the wiring for which the delay time is to be set is mounted, so that the delay is performed as in the first aspect of the present invention. It is not necessary to connect the wiring boards provided with the circuits to each other via each delay circuit, and the delay time of the wiring boards can be adjusted more easily. In addition, the signal propagation time of the wiring on the wiring board varies depending on the ambient heat. According to the second aspect of the present invention, the measurement reference wiring is mounted on the wiring board on which the wiring whose delay time is to be set is mounted. Therefore, it can be said that the fluctuation rate due to heat is almost the same between the signal propagation time of the reference wiring for measurement and the signal propagation time of the wiring for which the delay time is to be set. It is possible to set a delay time that is not easily affected.

  As described above, in the present invention, when the wiring board is, for example, a mounting board on which a plurality of semiconductor packages are mounted, each wiring for which a delay time provided on the wiring board should be set is between the semiconductor packages. This corresponds to each wiring of the mounting board that connects to each other. In this case, since a semiconductor chip is mounted on each semiconductor package, each wiring on the wiring board eventually corresponds to each wiring on the mounting board that connects the semiconductor chips. In addition, when the wiring board is, for example, a semiconductor package on which a plurality of semiconductor chips are mounted, each wiring to set a delay time provided on the wiring board is connected to each semiconductor chip. Wiring corresponds. In other words, each wiring of the wiring board for which the delay time is to be set means each wiring for connecting between the semiconductor chips regardless of whether the wiring board is a mounting board or a semiconductor package.

  Hereinafter, components having the same reference numerals in different drawings mean components having the same functions.

  FIG. 1 is a diagram showing an example of mounting a delay circuit according to the first embodiment of the present invention on a wiring board. In the following, with reference to FIGS. 1 to 3, each wiring for setting a delay time provided on the wiring board will be collectively described as each wiring for connecting between semiconductor chips on the wiring board.

  The delay circuit 1 according to the first embodiment of the present invention includes an interface 11 for instructing setting of a delay time, and a delay element 12 that can be programmed to an arbitrary delay time. 11 is set by an instruction. The interface 11 is a JTAG (Joint Test Action Group) interface. JTAG is a standard method of a boundary scan test (boundary scan test), which is one of IC chip inspection methods. In the boundary scan test in JTAG, TAP (Test Access Port) terminals of ICs to be inspected can be daisy chain connected, and a plurality of ICs can be read out and inspected in order.

  The delay elements 12 are connected in series with a JTAG chain. If a circuit for instructing execution of processing for adjusting and changing the delay time of the delay circuit is provided on the wiring board and connected to the JTAG interface 11 in the delay circuit 1, the circuit in the delay circuit 1 is connected via the JTAG interface 11. The delay time of the delay element 12 can be easily set or changed. The delay element 12 is connected to each of an input end and an output end of each wiring connecting the semiconductor chips 2 on the wiring substrate 100. In the illustrated example, the semiconductor chip 2 is mounted on the wiring board 100, and the input terminal thereof is represented by reference numeral 122 and the output terminal is represented by reference numeral 124. The delay element 12 is provided between the input buffer 121 and the input terminal 122 of the semiconductor chip 2 and between the output driver 123 and the output terminal 124 of the semiconductor chip 2.

  FIG. 2 is a basic block diagram showing a delay circuit according to the first embodiment of the present invention. In FIG. 2, connection lines to the semiconductor chip as shown in FIG. 1 are not shown.

  As shown in FIG. 2, the delay circuit 1 includes a JTAG interface 11 that instructs setting of a delay time, a delay element 12 that can be programmed at an arbitrary time, a storage element 13 that stores a parameter that defines the delay time, A control circuit 14 that performs overall control of the operation of the delay circuit 1, an interface 15, and a switch 16 are provided.

  As described with reference to FIG. 1, the delay elements 12 are connected in series with a JTAG chain, and each delay element 12 is provided for each wiring of the semiconductor chip. It should be noted that the number of delay elements shown in the figure does not limit the present invention and may be other numbers.

  The storage element 13 stores a parameter that defines a delay time for each delay element 12. The parameter acquisition process that defines the delay time will be described later. When power is supplied to the wiring board, power is also supplied to the delay circuit 1, and the control circuit 14 reads out a parameter defining the delay time for each delay element 12 from the storage element 13 via the JTAG interface, The delay time of the element 12 is set.

  Here, a process for acquiring a parameter that defines the delay time in the measurement mode for measuring the signal propagation time of each wiring between the semiconductor chips will be described. When a plurality of semiconductor chips are mounted on a wiring board, a skew occurs due to a difference in wiring length of wirings connecting between related semiconductor chips. Usually, the skew can be obtained by calculation in the design work of the wiring board, and the delay time is set based on the calculation result. On the other hand, in the present invention, the skew is actually measured using the measuring means provided in the delay element, and the delay time is set based on the measurement result. FIG. 3 is a basic block diagram showing a delay element in the delay circuit according to the first embodiment of the present invention shown in FIG. In FIG. 3, connection lines to the semiconductor chip as shown in FIG. 1 are not shown.

  Even in the measurement mode in which the signal propagation time of each wiring connecting between semiconductor chips is measured, the delay element 12 in the delay circuit according to the first embodiment of the present invention is connected to each semiconductor chip on the wiring board. The wiring is connected to each of the input end and the output end.

  First, the output switch 24 in the delay element 12 connected to the “one” terminal (hereinafter referred to as “first terminal” for convenience) side of the wiring between the semiconductor chips for which the delay time is to be set is delayed. Switching from the delay tap switch 25 side to the signal generator 22 side is performed under the control of the control circuit 21 in the element 12. As a result, the propagation time measurement signal generated by the signal generator 22 is output from the output terminal of the delay element 12 connected to the first terminal of the wiring between the semiconductor chips for which the delay time is to be set. Become.

  On the other hand, the delay element 12 connected to the “other” terminal (hereinafter referred to as “second terminal” for convenience) of the wiring between the semiconductor chips for which the delay time is to be set is included in the delay element 12. The input switch 23 is switched to the side connected to the ground via the resistor R under the control of the control circuit 21 in the delay element 12. Here, the resistance value of the resistor R is set to a sufficiently high value with respect to the specific impedance of the wiring pattern on the wiring board. As a result, the function of the signal reflection means for reflecting the signal input to the delay element 12 connected to the second terminal of the wiring between the semiconductor chips to set the delay time is configured. .

  The output switch 24 in the delay element 12 connected to the first terminal side of the wiring between the semiconductor chips whose delay time is to be set, and the second terminal side of the wiring between the semiconductor chips whose delay time is to be set In the delay element 12 connected to the first terminal side of the wiring between the semiconductor chips to set the delay time in the state where the input switch 23 in the delay element 12 connected to is switched as described above. The control circuit 21 controls the signal generator 22 to generate a propagation time measurement signal. The propagation time measurement signal is, for example, a pulse signal. At the same time, the control circuit 21 notifies the delay time measuring device 27 that the propagation time measuring signal has been generated. Upon receiving this notification, the delay time measuring device 27 starts time counting.

  The propagation time measurement signal generated by the signal generator 22 in the delay element 12 connected to the first terminal side passes over the wiring between the semiconductor chips to which the delay time is to be set via the first terminal. After propagating and passing through the second terminal, it reaches the delay element 12 connected to the second terminal side. Then, the propagation time measurement signal input to the delay element 12 connected to the second terminal side is reflected by the signal reflecting means, propagates again on the wiring between the semiconductor chips for which the delay time is to be set, After passing through one terminal, it reaches the delay element 12 connected to the first terminal side.

  The delay element 12 connected to the first terminal side measures the propagation time reflected and returned by the signal reflecting means in the delay element 12 connected to the second terminal side via the wiring between the semiconductor chips. The delay time measuring device 27 receives the signal for use. The delay time measuring device 27 stops the time count at the received timing. Thus, the time difference between the time when the delay time measuring device 27 receives the propagation time measuring signal and the time when the signal generator 22 transmits the propagation time measuring signal is measured. This measurement data is sent to the control circuit 21. The control circuit 21 writes the received measurement data into the measurement data register 32.

  The above processing is executed for each related wiring connecting the semiconductor chips. Measurement data for each wiring is acquired by a component related to acquisition of measurement data in the corresponding delay element, and written into the measurement data register 32 in the delay element. Each measurement data written in the measurement data register 32 in each delay element 12 passes through the “DATA output” line in FIG. 3 while using the control register 31 by the JTAG interface 11 described with reference to FIG. Read out.

  The read measurement data indicates a time difference between the time when the delay time measuring device 27 receives the propagation time measuring signal and the time when the signal generator 22 transmits the propagation time measuring signal as described above. However, half the time difference is the signal propagation time for the wiring between the semiconductor chips for which the delay time is to be set. The control circuit 14 in FIG. 1 grasps the maximum signal propagation time among the signal propagation times measured for each wiring between the semiconductor chips obtained through the interface 15. Then, the control circuit 14 in FIG. 2 calculates the time difference between the maximum signal propagation time and the signal propagation time measured for the wiring between the semiconductor chips for which the delay time is to be set, from the wiring for which the delay time is to be set. Confirm as the delay time.

  Each parameter defining the delay time determined for each wiring connecting the semiconductor chips is stored in the storage element 13 in the delay circuit 1, and the measurement mode is thus completed.

  After measurement mode is completed, return to normal mode. In the normal mode, when power is supplied to the wiring board, power is also supplied to the delay circuit 1, and the control circuit 14 reads out parameters defining the delay time for each delay element 12 from the storage element 13, The delay time of the delay element 12 is set. The normal mode process will be described below.

  In the normal mode, in each delay element 12, the input switch 23 is connected to the delay element 26 and the delay tap switch 25 from the side connected to the ground via the resistor R under the control of the control circuit 21. Switch the connection to the other side. Similarly, the output switch 24 switches the connection from the signal generator 22 side to the delay tap switch 25 side under the control of the control circuit 21.

  In addition, in response to an instruction from the JTAG interface 11 in FIG. 1, a parameter related to the delay time of each delay element 12 stored in the storage element 13 is read out via the switch 16 and the interface 15 via the DATA line. To the corresponding delay element 12. In each delay element 12, the control circuit 21 controls the delay tap switch 25 based on the received parameter related to the delay time, but the number of delay elements 26 that can obtain the required delay time is selected. The tap of the delay tap switch 25 is switched. Each delay element 26 electrically generates a predetermined delay amount, and examples thereof include an LC passive element. The number of delay elements shown in the figure does not limit the present invention and may be other numbers. If the delay amount generated by the delay element 26 is reduced and the number of the delay elements 26 is increased, the delay time can be set with higher accuracy.

  Based on the signal propagation time measured for each wiring between the semiconductor chips, which is the wiring for which the delay time on the wiring board is to be set, a series of the above processing, the input end and the output end of each wiring between the semiconductor chips. The optimum delay time is programmed (set) for each delay element provided as a delay circuit.

  Note that the signal propagation time for each wiring between the semiconductor chips and the delay time for each wiring between the set semiconductor chips are measured via the JTAG interface 11 by appropriately using the input pins of the JTAG interface 11. It is also possible to read out externally.

  Next, the mounting of the delay circuit according to the first embodiment of the present invention on the wiring board will be described. Here, as an example, it is assumed that the delay circuit chip is provided in the form of a semiconductor chip in which a delay circuit including a delay element made of an LC passive element is formed on a semiconductor substrate (silicon). The delay circuit according to the first embodiment of the present invention may be provided in the semiconductor chip.

  FIG. 4 is a cross-sectional view illustrating a first example of mounting the delay circuit on the wiring board according to the first embodiment of the invention. In the illustrated example, the delay circuit chip 1 according to the first embodiment of the present invention is mounted on one surface of the semiconductor package 300, and the semiconductor chip 2 is mounted on the other surface. The input / output terminals of the delay circuit chip 1 and the semiconductor chip 2 are constituted by one of the bumps 42 of each chip. Further, the input / output terminals of the semiconductor package 300 are constituted by solder balls 41 on the lands 40. The electrical wiring 50 from the semiconductor chip 2 in the semiconductor package 300 on which the semiconductor chip 2 is mounted is connected to the solder ball 41 via the delay circuit chip 1 and is indicated by a broken line in the drawing. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad.

  FIG. 5 is a cross-sectional view illustrating a second example of mounting the delay circuit on the wiring board according to the first embodiment of the invention. In the illustrated example, the delay circuit chip 1 according to the first embodiment of the present invention is mounted inside a semiconductor package 300 on which the semiconductor chip 2 is mounted, that is, embedded in a wiring board that is a semiconductor package. Yes. Other configurations are the same as those of the first example of mounting the delay circuit on the wiring board described with reference to FIG. That is, the input / output terminals of the delay circuit chip 1 and the semiconductor chip 2 are constituted by one of the electrode 45 of the delay circuit chip 1 and the bump 42 of the semiconductor chip. Further, the input / output terminals of the semiconductor package 300 are constituted by solder balls 41 on the lands 40. The electrical wiring 50 from the semiconductor chip 2 in the semiconductor package 300 on which the semiconductor chip 2 is mounted is connected to the solder ball 41 via the delay circuit chip 1 and is indicated by a broken line in the drawing. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad.

  FIG. 6 is a cross-sectional view illustrating a third example of mounting the delay circuit on the wiring board according to the first embodiment of the invention. In the illustrated example, the delay circuit chip according to the first embodiment of the present invention is mounted in a package on package. That is, the delay circuit chip 1 according to the first embodiment of the present invention is mounted on the semiconductor package 300D, and the semiconductor chip 2 is mounted on the semiconductor package 300C. The semiconductor package 300C and the semiconductor package 300D are connected via solder balls 41 on lands 40 configured as input / output terminals thereof. Other configurations are the same as those of the first example of mounting the delay circuit on the wiring board described with reference to FIG. That is, the electrical wiring 50 from the semiconductor chip 2 in the semiconductor package 300C on which the semiconductor chip 2 is mounted is indicated by broken lines in the figure, and the solder balls 41 that connect between the semiconductor packages 300C and 300D and the electrical wiring of the semiconductor package 300D. It is connected to the solder ball 41 on the land 40 through the wiring 50 and the delay circuit chip 1. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad.

  FIG. 7 is a cross-sectional view illustrating a fourth example of mounting the delay circuit according to the first embodiment of the invention on a wiring board. In the illustrated example, a plurality of semiconductor chips are mounted on a semiconductor package 300. Semiconductor chips 2A and 2B are mounted on the semiconductor package 300. The delay circuit chips 1A and 1B according to the first embodiment of the present invention are provided at the input / output ends of the semiconductor chips 2A and 2B, respectively. In the illustrated example, the semiconductor chips 2A and 2B of the semiconductor package 300 are mounted. The delay circuit chips 1A and 1B according to the first embodiment of the present invention are mounted on the side opposite to the side. The input / output terminals of the delay circuit chips 1A and 1B and the semiconductor chips 2A and 2B are constituted by one of the bumps 42 of each chip. Further, the input / output terminals of the semiconductor package 300 are constituted by solder balls 41 on the lands 40. The electrical wiring 50 from the semiconductor chip 2 in the semiconductor package 300 on which the semiconductor chip 2 is mounted is indicated by a broken line in the figure via the delay circuit chip 1. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad. The wiring 50a is a wiring of the semiconductor package 300 that connects the semiconductor chips 2A and 2B, and connects the input / output terminals of the semiconductor chips 2A and 2B via the delay circuit chips 1A and 1B. The delay time of signal propagation of the wiring 50a is adjusted by the delay circuit chips 1A and 1B. The wiring 50b is a wiring of the semiconductor package 300 for connecting the semiconductor package 300 and another semiconductor package, and is connected to another semiconductor package via a wiring on the mounting substrate. The wiring 50b corresponds to the wiring 50 in FIG. Also, the input / output terminals of the semiconductor chips 2A and 2B and the solder balls 41, which are the input / output terminals of the semiconductor package, are connected via the delay circuit chips 1A and 1B.

  Next, a case where the wiring board is a mounting board on which a plurality of semiconductor packages are mounted will be described with reference to FIGS. Here, as an example, the delay circuit according to the first embodiment of the present invention is a delay circuit chip. FIG. 8 is a schematic view illustrating a case where the delay circuit according to the first embodiment of the invention is mounted on a mounting board on which a plurality of semiconductor packages are mounted, and the delay time of each wiring connecting the semiconductor packages is adjusted. FIG.

  Here, as an example, consider a case where the semiconductor package 300A and the semiconductor package 300B are mounted on the mounting substrate 200, the semiconductor chip 2A is mounted on the semiconductor package 300A, and the semiconductor chip 2B is mounted on the semiconductor package 300B. Note that the number of semiconductor packages and the number of semiconductor chips mounted on the illustrated mounting substrate 200 are not limited to the present invention, and may be other numbers.

  The semiconductor chip 2A on the semiconductor package 300A and the semiconductor chip 2B on the semiconductor package 300B are electrically connected by wirings 51 and 52 provided on the mounting substrate 200. A skew occurs between the wirings 51 and 52 due to a difference in wiring length. Therefore, in order to adjust the delay time, the delay circuit chip 1A according to the first embodiment of the present invention is provided at the input end and output end of the semiconductor chip 2A on the semiconductor package 300A, and the semiconductor on the semiconductor package 300B. The delay circuit chip 1B according to the first embodiment of the present invention is provided at the input end and output end of the chip 2B.

  In the first embodiment of the present invention, in the measurement mode, the measurement means (not shown) provided in the respective delay elements (not shown) in the delay circuit chips 1A and 1B have already been described. The skew is actually measured, and the delay time is set based on the measurement result. In the example of FIG. 8, the propagation time measurement signal output from the output terminal of the delay circuit chip 1A on the semiconductor package 300A passes through the wiring 51 provided on the mounting substrate 200, and the delay circuit chip 1B on the semiconductor package 300B. To the input terminal. Then, this propagation time measurement signal is reflected at the input terminal of the delay circuit chip 1B, and reaches the output terminal of the delay circuit chip 1A through the wiring 51 provided on the mounting substrate 200. Thereby, the signal propagation time of the wiring 51 for which the delay time is to be set is measured. On the other hand, the propagation time measurement signal output from the output terminal of the delay circuit chip 1B on the semiconductor package 300B passes through the wiring 52 provided on the mounting substrate 200 and is input to the input terminal of the delay circuit chip 1A on the semiconductor package 300A. To reach. Then, this propagation time measurement signal is reflected at the input terminal of the delay circuit chip 1A, and reaches the output terminal of the delay circuit chip 1B through the wiring 52 provided on the mounting substrate 200. Thereby, the signal propagation time of the wiring 52 to set the delay time is measured. Based on the measured signal propagation times of the wirings 51 and 52 for which the delay times are to be set, the delay times of the wirings 51 and 52 of the mounting board 200 are set in accordance with the method described above. Note that the measured signal propagation times of the wirings 51 and 52 include the propagation times of the wirings from the input / output terminals of the semiconductor packages 300A and 300B to the delay circuit chips 1A and 1B, respectively. However, this propagation time is ignored because the wiring length to the delay circuit chips 1A and 1B in the semiconductor packages 300A and 300B is extremely shorter than the wiring lengths of the wirings 51 and 52 provided on the mounting substrate 200, respectively. Can do.

  FIG. 9 is a cross-sectional view illustrating an example of implementation of the delay circuit schematically illustrated in FIG. A semiconductor package 300A and a semiconductor package 300B are mounted on the mounting substrate 200. In the illustrated example, the delay circuit chips 1A and 1B according to the first embodiment of the present invention are mounted by the method described with reference to FIG. That is, the delay circuit chip 1A according to the first embodiment of the present invention is mounted on one surface of the semiconductor package 300A, and the semiconductor chip 2A is mounted on the other surface. Also, the delay circuit chip 1B according to the first embodiment of the present invention is mounted on one surface of the semiconductor package 300B, and the semiconductor chip 2B is mounted on the other surface. The input terminals of the delay circuit chips 1A and 1B are each composed of a bump 46in, and the output terminals of the delay circuit chips 1A and 1B are each composed of a bump 46out. Further, the input terminals of the semiconductor chips 2A and 2B are each configured by a bump 42in, and the output terminals of the semiconductor chips 2A and 2B are each configured by a bump 42out. The wirings 51 and 52 shown in FIG. 8 are indicated by broken lines in FIG. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad. In the example shown in FIG. 9, the delay circuit chips 1A and 1B according to the first embodiment of the present invention are mounted by the method described with reference to FIG. 4. As an alternative example, FIG. The delay circuit chips 1A and 1B may be mounted by the method referred to.

  Next, a case where the wiring board is a semiconductor package on which a plurality of semiconductor chips are mounted will be described with reference to FIG. As an example, the delay circuit according to the first embodiment of the present invention is a delay circuit chip. FIG. 10 shows a case where the delay circuit according to the first embodiment of the present invention is mounted on a semiconductor package on which a plurality of semiconductor chips are mounted, and the delay time of each wiring of the semiconductor package connecting the semiconductor chips is adjusted. It is a schematic diagram illustrated.

  Here, as an example, a case where the semiconductor chip 2A and the semiconductor chip 2B are mounted on the semiconductor package 300 is considered. It should be noted that the number of semiconductor packages and the number of semiconductor chips mounted on the illustrated semiconductor package 300 are not limited to the present invention, and may be other numbers.

  The semiconductor chip 2A and the semiconductor chip 2B are electrically connected by wirings 51 and 52 provided in the semiconductor package 300. For this implementation, for example, the method described with reference to FIG. 7 may be applied. In this case, the wiring 50a in FIG. 7 corresponds to the wirings 51 and 52 in FIG. A skew occurs between the wirings 51 and 52 due to a difference in wiring length. Therefore, in order to adjust the delay time, the delay circuit chip 1A according to the first embodiment of the present invention is provided at the input end and output end of the semiconductor chip 2A on the semiconductor package 300, and the input end of the semiconductor chip 2B. The output terminal is provided with the delay circuit chip 1B according to the first embodiment of the present invention.

  In the first embodiment of the present invention, in the measurement mode, the measurement means (not shown) provided in the respective delay elements (not shown) in the delay circuit chips 1A and 1B have already been described. The skew is actually measured, and the delay time is set based on the measurement result. In the example of FIG. 10, the propagation time measurement signal output from the output terminal of the delay circuit chip 1A on the semiconductor package 300 passes through the wiring 51 provided in the semiconductor package 300 and reaches the input terminal of the delay circuit chip 1B. To do. Then, this propagation time measurement signal is reflected at the input terminal of the delay circuit chip 1B, and reaches the output terminal of the delay circuit chip 1A through the wiring 51 provided in the semiconductor package 300. Thereby, the signal propagation time of the wiring 51 for which the delay time is to be set is measured. On the other hand, the propagation time measurement signal output from the output terminal of the delay circuit chip 1B passes through the wiring 52 provided in the semiconductor package 300 and reaches the input terminal of the delay circuit chip 1A. Then, this propagation time measurement signal is reflected at the input terminal of the delay circuit chip 1A, and reaches the output terminal of the delay circuit chip 1B through the wiring 52 provided in the semiconductor package 300. Thereby, the signal propagation time of the wiring 52 to set the delay time is measured. Based on the measured signal propagation times of the wirings 51 and 52 for which the delay times are to be set, the delay times of the wirings 51 and 52 of the semiconductor package 300 are set according to the method described above.

  Next, a case where the wiring board is a mounting board, a plurality of semiconductor packages are mounted on the mounting board, and a plurality of semiconductor chips are mounted on one of the semiconductor packages will be described with reference to FIG. . As an example, the delay circuit according to the first embodiment of the present invention is a delay circuit chip. In FIG. 11, the delay circuit according to the first embodiment of the present invention is mounted on a mounting substrate on which a plurality of semiconductor packages are mounted, and a plurality of semiconductor chips are mounted on one of the semiconductor packages. It is a schematic diagram which illustrates the case where the delay time of each wiring which connects is adjusted.

  Here, as an example, a semiconductor package 300A in which the semiconductor chip 2A is mounted, a semiconductor package 300B in which the semiconductor chip 2B is mounted, and a semiconductor package 300C in which the semiconductor chips 2C and 2D are mounted are mounted on the mounting substrate 200. Consider the case. Note that the number of semiconductor packages and the number of semiconductor chips mounted on the illustrated mounting substrate 200 are not limited to the present invention, and may be other numbers.

  The semiconductor chip 2C and the semiconductor chip 2D on the semiconductor package 300C are electrically connected by wirings 51 and 52 provided in the semiconductor package 300C. For this implementation, for example, the method described with reference to FIG. 7 may be applied. In this case, the wiring 50 a in FIG. 7 corresponds to the wiring 51 or 52. 7 corresponds to the wiring of the semiconductor package 300C connected to the wirings 53, 54, 55, and 56 of the mounting substrate 200. In addition, the semiconductor chip 2A on the semiconductor package 300A is electrically connected to the semiconductor chip 2C on the semiconductor package 300C by wirings 53 and 54 provided on the mounting substrate 200. Further, the semiconductor chip 2B on the semiconductor package 300B is electrically connected to the semiconductor chip 2D on the semiconductor package 300C by wirings 55 and 56 provided on the mounting substrate 200.

  A skew occurs between the wiring 51 and the wiring 52, between the wiring 53 and the wiring 54, and between the wiring 55 and the wiring 56 due to a difference in wiring length. Therefore, in order to adjust the delay time, the input terminals and output terminals of the semiconductor chips 2A, 2B, 2C and 2D are respectively connected to the delay circuit chips 1A, 1B, 1C and 1D are provided. In the present invention, in the measurement mode, the skew is actually measured using measurement means (not shown) provided in each delay element (not shown) in the delay circuit chips 1A, 1B, 1C and 1D. The delay time is set based on the measurement result, and the method is as described above.

  In the second embodiment of the present invention, the signal propagation time of the reference wiring for measurement provided on the wiring board is actually measured, and the delay time is set based on the measurement result. FIG. 12 is a diagram showing a mounting example on the wiring board of the delay circuit according to the second embodiment of the present invention. In the following, with reference to FIGS. 12 to 14, each wiring to be set with a delay time provided on the wiring board will be described collectively as each wiring for connecting between semiconductor chips on the wiring board.

  The delay circuit 1 according to the second embodiment of the present invention includes an interface 11 for instructing setting of a delay time, an input delay element 12-1 and an output delay element 12-2 that can be programmed to an arbitrary delay time, and a delay time. And a measuring element 17 for measuring the signal propagation time of the reference wiring for measurement provided on the wiring board to be set.

  As in the first embodiment of the invention described above, the delay times of the input delay element 12-1 and the output delay element 12-2 are set by an instruction from the interface 11. The interface 11 is a JTAG (Joint Test Action Group) interface. Further, the data (in this case, the signal propagation time of the reference wiring for measurement) measured by the measuring element 17 described later can be read out via the JTAG interface 11. The input delay element 12-1, the output delay element 12-2, and the measurement element 17 are connected in series by a JTAG chain.

  The input delay element 12-1 and the output delay element 12-2 are connected to the input end and the output end of each wiring connecting the semiconductor chips 2 on the wiring substrate 100, respectively. In the illustrated example, the semiconductor chip 2 is mounted on the wiring board 100, and the input terminal thereof is represented by reference numeral 122 and the output terminal is represented by reference numeral 124. The input delay element 12-1 is provided between the input buffer 121 and the input terminal 122 of the semiconductor chip 2, and the output delay element 12-2 is provided between the output driver 123 and the output terminal 124 of the semiconductor chip 2.

  A microstrip line and a strip line are provided in advance as the measurement reference line 126 on the wiring board on which the wiring for which the delay time is to be set is mounted. Therefore, the designer or the like can grasp in advance the length of the measurement reference wiring at the time of designing. Similarly, a designer or the like designs the wiring of the wiring board using the CAD system, so that the design length of the wiring of the wiring board for which the delay time should be set can be grasped in advance.

  The measurement element 17 is connected to the measurement reference wiring 126 via the measurement terminal 125. In the illustrated example, measuring elements 17 are provided independently for the wirings of the input buffer and the output driver. At least two measuring elements 17 are provided for the microstrip line and the strip line, but the number may be increased or decreased as necessary.

  One end of the measurement reference wiring 126 is connected to the measurement terminal 125 and the other end is grounded via the resistor R. The resistance value of the resistor R is sufficiently high with respect to the specific impedance of the wiring pattern on the wiring board. As a result, the signal output toward the measurement reference wiring 126 via the measurement terminal 125 is reflected and then returns to the measurement element 17 via the measurement terminal 125 again. As an alternative example, the measurement reference wiring 126 may be configured such that one end thereof is connected to the measurement terminal 125 and the other end is opened.

  FIG. 13 is a basic block diagram showing a delay circuit according to the second embodiment of the present invention. As shown in FIG. 13, the delay circuit 1 defines a delay time, a JTAG interface 11 for instructing the setting of a delay time, an input delay element 12-1 and an output delay element 12-2 that can be programmed at an arbitrary time. A storage element 13 that stores the parameters to be controlled, a control circuit 14 that performs overall control of the operation of the delay circuit 1, an interface 15, a switch 16, and a measurement element 17.

  The input delay element 12-1, the output delay element 12-2, and the measurement element 17 are connected in series by a JTAG chain. Further, the input delay element 12-1 is provided for each wiring to the input buffer of the semiconductor chip and is connected to each input buffer. The output delay element 12-2 is provided for each wiring to the output driver of the semiconductor chip and is connected to each output driver. It should be noted that the number of delay elements shown in the figure does not limit the present invention and may be other numbers.

  In the second embodiment of the present invention, as in the first embodiment of the present invention described above, the storage element 13 stores parameters that define the delay time for each delay element 12. When power is turned on to the wiring board, power is also supplied to the delay circuit 1, and the control circuit 14 transmits each of the input delay element 12-1 and the output delay element 12-2 from the storage element 13 via the JTAG interface. A parameter that defines the delay time is read, and the delay time of each input delay element 12-1 and output delay element 12-2 is set.

  In the second embodiment of the present invention, the parameter acquisition process for defining the delay time in the measurement mode for measuring the signal propagation time of each wiring between the semiconductor chips is as follows.

  FIG. 14 is a basic block diagram showing measurement elements in the delay circuit according to the second embodiment of the present invention shown in FIG. Note that FIG. 14 does not show connection lines to the semiconductor chip as shown in FIG.

  In the measurement mode for measuring the signal propagation time of each wiring on the wiring board, the control circuit 21 in the measuring element 17 provided on the wiring board on which the delay time is to be set causes the signal generator 22 to measure the propagation time. Control to generate a signal. As a result, a propagation time measurement signal is transmitted toward the measurement reference wiring connected to the measurement terminal of the measurement element 17. The propagation time measurement signal is, for example, a pulse signal. At the same time, the control circuit 21 notifies the delay time measuring device 27 that the propagation time measuring signal has been generated. Upon receiving this notification, the delay time measuring device 27 starts time counting.

  As described above, the reference wiring for measurement has a resistor R having a sufficiently high resistance value with respect to the specific impedance of the wiring pattern on the wiring board at the other end opposite to the one end connected to the measurement terminal. Therefore, the propagation time measurement signal generated by the signal generator 22 propagates on the measurement reference wiring, is reflected, propagates again on the measurement reference wiring, and passes through the measurement terminal. It reaches the measuring element 17 connected to the terminal for use.

  The measurement element 17 receives the propagation time measurement signal reflected by the measurement reference wiring and returned by the delay time measuring device 27. The delay time measuring device 27 stops the time count at the received timing. Thus, the time difference between the time when the delay time measuring device 27 receives the propagation time measuring signal and the time when the signal generator 22 transmits the propagation time measuring signal is measured. This measurement data is sent to the control circuit 21. The control circuit 21 writes the received measurement data into the measurement data register 32.

  As described above, in the second embodiment of the present invention, the measuring element is provided for each of the input buffer and the output drive, but the above processing is provided for each of the input buffer and the output drive. It is executed for the measurement reference wiring. Measurement data for each measurement reference wiring is acquired by the corresponding measurement element 17 and written to the measurement data register 32 in the measurement element 17. Each measurement data written in the measurement data register 32 in each measurement element 17 is displayed on the “DATA output” line in FIG. 14 while using the control register 31 by the JTAG interface 11 described with reference to FIG. Read via.

  The read measurement data indicates a time difference between the time when the delay time measuring device 27 receives the propagation time measuring signal and the time when the signal generator 22 transmits the propagation time measuring signal as described above. However, the half of the time difference is the signal propagation time for the measurement reference wiring.

  As described above, the measurement reference wiring is previously formed by a designer or the like on a wiring board on which wiring for which a delay time is to be set is mounted. Therefore, the designer or the like can grasp the length of the reference wiring for measurement at the time of designing. On the other hand, the designer or the like designs the wiring of the wiring board using the CAD system, so that the design length of the wiring of the wiring board for which the delay time should be set can also be grasped.

  Therefore, since the signal propagation time per unit length of the measurement reference wiring can be calculated from the signal propagation time and length of the measurement reference wiring, the signal propagation time per unit length of the measurement reference wiring And the wiring delay time of the wiring board on which the delay time is to be set can be estimated by calculation from the wiring design length of the wiring board on which the delay time is to be set. In the second embodiment of the present invention, the length of the reference wiring for measurement and the design length of the wiring of the wiring board on which the delay time is to be set are input in advance to the computer to which the JTAG interface 11 is connected. Thus, the delay time of the wiring of the wiring board on which the delay time is to be set is estimated by executing the calculation as described above.

  About each wiring of the wiring board estimated using the signal propagation time for the measurement reference wiring from the ratio of the wiring design length of the wiring board to which the delay time should be set as described above and the length of the measurement reference wiring The maximum signal propagation time is grasped via the interface 15 by the control circuit 14 of FIG. Then, the control circuit 14 in FIG. 13 determines the time difference between the maximum signal propagation time and the signal propagation time estimated for the wiring for which the delay time is to be set as the delay time of the wiring for which the delay time is to be set. To do.

  Each parameter that defines the delay time determined for each wiring is stored in the storage element 13 in the delay circuit 1, and the measurement mode is thus completed. Also in the second embodiment of the present invention, as in the first embodiment, after completion of the measurement mode, the mode returns to the normal mode.

  FIG. 15 is a basic block diagram showing an input delay element in the delay circuit according to the second embodiment of the present invention shown in FIG. FIG. 16 is a basic block diagram showing an output delay element in the delay circuit according to the second embodiment of the present invention shown in FIG. 15 and 16 do not show connection lines to the semiconductor chip as shown in FIG.

  In the normal mode, when power is turned on to the wiring board, power is also supplied to the delay circuit 1, and the control circuit 14 controls each of the input delay element 12-1 and the output delay element 12-2 from the storage element 13. A parameter that defines the delay time is read, and the delay time of each input delay element 12-1 and output delay element 12-2 is set.

  In response to an instruction from the JTAG interface 11 in FIG. 13, a parameter related to the delay time of the input delay element 12-1 stored in the storage element 13 is read out, and the input delay element via the DATA line via the interface 15. Sent to 12-1.

  In the input delay element 12-1 in FIG. 15, the control circuit 21 controls the delay tap switch 25 based on the received parameter related to the delay time, but the number of delays that can obtain the required delay time. The tap of the delay tap switch 25 is switched so that the element 26 is selected.

  In response to an instruction from the JTAG interface 11 in FIG. 13, a parameter related to the delay time of the output delay element 12-2 stored in the storage element 13 is read out, and is output via the DATA line via the interface 15. Sent to 12-2.

  In the output delay element 12-2 of FIG. 16, the control circuit 21 controls the delay tap switch 25 based on the received parameter relating to the delay time, but the number of delays that can obtain the required delay time. The tap of the delay tap switch 25 is switched so that the element 26 is selected.

  Each delay element 26 electrically generates a predetermined delay amount as in the case of the first embodiment, and examples thereof include an LC passive element. The number of delay elements shown in the figure does not limit the present invention and may be other numbers. If the delay amount generated by the delay element 26 is reduced and the number of the delay elements 26 is increased, the delay time can be set with higher accuracy.

  Through the series of processes described above, in the second embodiment of the present invention, the input end and output of each wiring between the semiconductor chips based on the signal propagation time measured for the reference wiring for measurement provided on the wiring board. The optimum delay time is programmed (set) for each of the input delay element and the output delay element provided as a delay circuit at each of the ends.

  Note that the signal propagation time for the measurement reference wiring and the delay time for each wiring between the set semiconductor chips are read out via the JTAG interface 11 by appropriately using the input pins of the JTAG interface 11. Is also possible.

  Next, the mounting of the delay circuit according to the second embodiment of the present invention on the wiring board will be described. Here, a case where the wiring board is a mounting board on which a plurality of semiconductor packages are mounted will be described with reference to FIGS. Here, as an example, the delay circuit according to the second embodiment of the present invention is a delay circuit chip.

  FIG. 17 is a schematic view illustrating a case where the delay circuit according to the second embodiment of the invention is mounted on a mounting board on which a plurality of semiconductor packages are mounted, and the delay time of each wiring connecting the semiconductor packages is adjusted. FIG.

  Here, as an example, consider a case where the semiconductor package 300A and the semiconductor package 300B are mounted on the mounting substrate 200, the semiconductor chip 2A is mounted on the semiconductor package 300A, and the semiconductor chip 2B is mounted on the semiconductor package 300B. Note that the number of semiconductor packages and the number of semiconductor chips mounted on the illustrated mounting substrate 200 are not limited to the present invention, and may be other numbers.

  The semiconductor chip 2A on the semiconductor package 300A and the semiconductor chip 2B on the semiconductor package 300B are electrically connected by wirings 51 and 52 provided on the mounting substrate 200. A skew occurs between the wirings 51 and 52 due to a difference in wiring length. Therefore, in order to adjust the delay time, the delay circuit chip 1A according to the second embodiment of the present invention is provided at the input end and output end of the semiconductor chip 2A on the semiconductor package 300A. On the other hand, in the second embodiment of the present invention, unlike the first embodiment, there is no need to provide a delay circuit chip on the semiconductor package 300B.

  In the second embodiment of the present invention, a measurement reference wiring 126 is provided on the mounting substrate 200 and connected to a measurement terminal (not shown) of the delay circuit chip 1A. In the measurement mode, the signal propagation time of the measurement reference wiring 126 is actually measured as described above using the measurement element (not shown) in the delay circuit chip 1A, and the delay is based on the measurement result. Set the time.

  Specifically, in the example of FIG. 17, the propagation time measurement signal output from the output terminal of the delay circuit chip 1A on the semiconductor package 300A propagates through the measurement reference wiring 126. Then, this propagation time measurement signal is reflected and then reaches a measurement element (not shown) of the delay circuit chip 1A. Then, the signal propagation time of the wirings 51 and 52 for which the delay time is to be set is estimated. Based on these estimated signal propagation times, the delay times of the wirings 51 and 52 of the mounting substrate 200 are set in accordance with the method described above.

  18 is a cross-sectional view illustrating an example of mounting the delay circuit schematically illustrated in FIG. A semiconductor package 300A and a semiconductor package 300B are mounted on the mounting substrate 200. In the illustrated example, the delay circuit chip 1A according to the first embodiment of the present invention is mounted on one surface of the semiconductor package 300A, and the semiconductor chip 2A is mounted on the other surface. The semiconductor chip 2B is mounted on one surface of the semiconductor package 300B. In addition, a measurement reference wiring 126 is provided on the mounting substrate 200. A measurement terminal connected to the measurement reference wiring 126 and a measurement element (not shown) in the delay circuit chip 1 </ b> A is constituted by a bump 47. The input terminal of the delay circuit chip 1A is composed of bumps 46in, and the output terminal of the delay circuit chip 1A is composed of bumps 46out. Further, the input terminals of the semiconductor chips 2A and 2B are each configured by a bump 42in, and the output terminals of the semiconductor chips 2A and 2B are each configured by a bump 42out. The wirings 51 and 52 shown in FIG. 17 are indicated by broken lines in FIG. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad.

  Next, a case where the wiring board is a semiconductor package on which a plurality of semiconductor chips are mounted will be described with reference to FIG. As an example, the delay circuit according to the second embodiment of the present invention is a delay circuit chip. FIG. 19 shows a delay time of each wiring of a semiconductor package in which the delay circuit according to the second embodiment of the present invention is mounted on one of the semiconductor packages on which a plurality of semiconductor chips are mounted, and connects the semiconductor chips. It is a schematic diagram which illustrates the case where it adjusts.

  Here, as an example, a case where the semiconductor chip 2A and the semiconductor chip 2B are mounted on the semiconductor package 300 is considered. The number of semiconductor chips mounted on the illustrated semiconductor package 300 is not limited to the present invention, and may be other numbers.

  The semiconductor chip 2A and the semiconductor chip 2B are electrically connected by wirings 51 and 52 provided in the semiconductor package 300. A skew occurs between the wirings 51 and 52 due to a difference in wiring length. Therefore, in order to adjust the delay time, the delay circuit chip 1A according to the second embodiment of the present invention is provided at the input end and output end of the semiconductor chip 2A on the semiconductor package 300. A measurement reference wiring 126 is provided on the semiconductor package 300 and is connected to a measurement terminal (not shown) of the delay circuit chip 1A. In the measurement mode, the signal propagation time of the measurement reference wiring 126 is actually measured as described above using the measurement element (not shown) in the delay circuit chip 1A, and the delay is based on the measurement result. Set the time.

  In the example of FIG. 19, the propagation time measurement signal output from the output terminal of the delay circuit chip 1 </ b> A on the semiconductor package 300 propagates through the measurement reference wiring 126. Then, this propagation time measurement signal is reflected and then reaches a measurement element (not shown) of the delay circuit chip 1A. Then, the signal propagation time of the wirings 51 and 52 for which the delay time is to be set is estimated. Based on these estimated signal propagation times, the delay times of the wirings 51 and 52 of the semiconductor package 300 are set in accordance with the method described above.

  FIG. 20 is a cross-sectional view illustrating an example of mounting the delay circuit schematically illustrated in FIG. In the illustrated example, the semiconductor chip 2A, the delay circuit chip 1A according to the second embodiment of the present invention, and the semiconductor chip 2B are mounted on one surface of the semiconductor package 300. A measurement reference wiring 126 is provided on the semiconductor package 300. A measurement terminal connected to the measurement reference wiring 126 and a measurement element (not shown) in the delay circuit chip 1 </ b> A is constituted by a bump 47. The input terminal of the delay circuit chip 1A is composed of bumps 46in, and the output terminal of the delay circuit chip 1A is composed of bumps 46out. Further, the input terminals of the semiconductor chips 2A and 2B are each configured by a bump 42in, and the output terminals of the semiconductor chips 2A and 2B are each configured by a bump 42out. The wirings 51 and 52 shown in FIG. 19 are indicated by broken lines in FIG. In this figure, reference numeral 43 indicates a sealing resin, and reference numeral 44 indicates a pad.

  Next, a case where the wiring board is a mounting board, a plurality of semiconductor packages are mounted on the mounting board, and a plurality of semiconductor chips are mounted on one of the semiconductor packages will be described with reference to FIG. . As an example, the delay circuit according to the second embodiment of the present invention is a delay circuit chip. In FIG. 21, a plurality of semiconductor packages are mounted, and the delay circuit according to the second embodiment of the present invention is mounted on a mounting substrate in which a plurality of semiconductor chips are mounted in one of the semiconductor packages. It is a schematic diagram which illustrates the case where the delay time of each wiring to connect is adjusted.

  Here, as an example, consider a case where a semiconductor package 300A on which the semiconductor chip 2A is mounted and a semiconductor package 300C on which the semiconductor chips 2C and 2D are mounted are mounted on the mounting substrate 200. Note that the number of semiconductor packages and the number of semiconductor chips mounted on the illustrated mounting substrate 200 are not limited to the present invention, and may be other numbers.

  The semiconductor chip 2C and the semiconductor chip 2D on the semiconductor package 300C are electrically connected by wirings 51 and 52 provided in the semiconductor package 300C. In addition, the semiconductor chip 2A on the semiconductor package 300A is electrically connected to the semiconductor chip 2C on the semiconductor package 300C by wirings 53 and 54 provided on the mounting substrate 200.

  A skew occurs between the wiring 51 and the wiring 52 and between the wiring 53 and the wiring 54 due to a difference in wiring length. Therefore, in order to adjust the delay time, the delay circuit chip 1C according to the second embodiment of the present invention is provided at the input end and the output end of the semiconductor chip 2C as shown in the figure. Further, on the semiconductor package 300C, a measurement reference wiring 126C for setting the delay time of the wirings 51 and 52 is provided adjacent to the wirings 51 and 52, and a measurement terminal (not shown) of the delay circuit chip 1C is provided. Connected). Similarly, a measurement reference wiring 126C for setting the delay time of the wirings 53 and 54 is provided adjacent to the wirings 53 and 54 on a part of the semiconductor package 300C and the mounting substrate 200, and the delay circuit chip 1A. Connected to a measurement terminal (not shown). In the measurement mode, the signal propagation time of the measurement reference wiring 126C is actually measured as described above using the measurement element (not shown) in the delay circuit chip 1A. Delay times of the wirings 51, 52, 53 and 54 are set.

  FIG. 22 is a flowchart showing an operation flow for adjusting the delay time in the delay circuit according to the second embodiment of the present invention.

  In step S101, in the measurement mode, the control circuit 21 in the measurement element 17 provided on the wiring board on which the delay time is to be set controls the signal generator 22 to generate a propagation time measurement signal. . As a result, a signal for propagation time measurement is transmitted from the signal generator 22 toward the measurement reference wiring 126 connected to the measurement terminal 125 of the measurement element 17. At the same time, the control circuit 21 notifies the delay time measuring device 27 that the propagation time measuring signal has been generated. Upon receiving this notification, the delay time measuring device 27 starts time counting.

  The propagation time measurement signal generated by the signal generator 22 is reflected on the measurement reference wiring 126 and then reflected, propagates again on the measurement reference wiring 126, passes through the measurement terminal 125, and then is measured. 17 is reached.

  Next, in step S <b> 102, the measurement element 17 receives the propagation time measurement signal reflected by the measurement reference wiring 126 and returned by the delay time measuring device 27. The delay time measuring device 27 stops the time count at the received timing. Thus, the time difference between the time when the delay time measuring device 27 receives the propagation time measuring signal and the time when the signal generator 22 transmits the propagation time measuring signal is measured. This measurement data is sent to the control circuit 21. The control circuit 21 writes the received measurement data into the measurement data register 32. Measurement data for each measurement reference wiring is acquired by the corresponding measurement element 17 and written to the measurement data register 32 in the measurement element 17. Each measurement data written in the measurement data register 32 in each measurement element 17 is read out via the DATA output line by using the control register 31 by the JTAG interface 11.

  Next, in step S103, the computer, based on the measurement data read out via the JTAG interface 11, the time when the delay time measuring device 27 receives the signal for measuring the propagation time, and the signal generator 22 for measuring the propagation time. A time half the time difference from the time when the signal is transmitted is calculated as a signal propagation time for the measurement reference wiring 126.

  Next, in step S104, the computer can calculate the signal propagation time per unit length of the measurement reference wiring 126 from the signal propagation time and length of the measurement reference wiring 126. From the signal propagation time per unit length of 126 and the wiring design length of the wiring board on which the delay time is to be set, the wiring delay time of the wiring board on which the delay time is to be set is estimated by calculation.

  The computer searches for the maximum signal propagation time from the signal propagation times for each wiring of the wiring board estimated as described above. This maximum signal propagation time is grasped via the interface 15 by the control circuit 14 of FIG. In step S105, the control circuit 14 in FIG. 13 determines the time difference between the maximum signal propagation time and the signal propagation time estimated for the wiring for which the delay time is to be set as the delay time of the wiring for which the delay time is to be set. Confirm as

  In step S106, the optimum delay time is programmed (set) for each input delay element and each output delay element in the normal mode.

  The present invention can be applied to a circuit for adjusting a signal propagation delay time of each wiring of a wiring board. According to the first and second embodiments of the present invention, the delay time of signal propagation of each wiring of the wiring board can be set by an electrical method, so that the delay time can be easily adjusted. And can be changed many times. Further, according to the first and second embodiments of the present invention, the skew of the wiring board can be easily measured, and the delay time is set based on the measurement result. It is more accurate than the setting of the delay time based on the calculation at the time. Furthermore, it is possible to realize a delay circuit that can cope with downsizing and high-density mounting of the wiring board. Further, according to the first embodiment of the present invention, no special jig or measuring device for adjusting or changing the delay time is required outside. Further, according to the second embodiment of the present invention, it is possible to set a delay time that is not easily affected by changes in ambient heat.

It is a figure which shows the example of mounting on the wiring board of the delay circuit by the 1st Example of this invention. 1 is a basic block diagram showing a delay circuit according to a first embodiment of the present invention. FIG. 3 is a basic block diagram showing delay elements in the delay circuit according to the first embodiment of the present invention shown in FIG. 2. 5 is a cross-sectional view illustrating a first example of mounting the delay circuit according to the first embodiment of the invention on a wiring board; FIG. 6 is a cross-sectional view illustrating a second example of mounting the delay circuit according to the first embodiment of the invention on a wiring board; FIG. FIG. 6 is a cross-sectional view illustrating a third example of mounting the delay circuit according to the first embodiment of the invention on a wiring board; 6 is a cross-sectional view illustrating a fourth example of mounting the delay circuit according to the first embodiment of the invention on a wiring board; FIG. FIG. 5 is a schematic view illustrating a case where the delay circuit according to the first embodiment of the present invention is mounted on a mounting board on which a plurality of semiconductor packages are mounted, and the delay time of each wiring connecting the semiconductor packages is adjusted. FIG. 9 is a cross-sectional view illustrating an example of implementation of the delay circuit schematically illustrated in FIG. 8. Schematic diagram illustrating a case where the delay circuit according to the first embodiment of the present invention is mounted on a semiconductor package on which a plurality of semiconductor chips are mounted, and the delay time of each wiring of the semiconductor package connecting the semiconductor chips is adjusted. It is. The delay circuit according to the first embodiment of the present invention is mounted on a mounting substrate on which a plurality of semiconductor packages are mounted, and a plurality of semiconductor chips are mounted on one of the semiconductor packages, and each of the semiconductor chips is connected to each other. It is a schematic diagram which illustrates the case where the delay time of wiring is adjusted. It is a figure which shows the example of mounting on the wiring board of the delay circuit by the 2nd Example of this invention. It is a basic block diagram showing a delay circuit according to a second embodiment of the present invention. FIG. 14 is a basic block diagram showing measurement elements in the delay circuit according to the second embodiment of the present invention shown in FIG. 13. FIG. 14 is a basic block diagram showing an input delay element in the delay circuit according to the second embodiment of the present invention shown in FIG. 13. FIG. 14 is a basic block diagram showing an output delay element in the delay circuit according to the second embodiment of the present invention shown in FIG. 13. It is a schematic diagram which illustrates the case where the delay circuit by the 2nd Example of this invention is mounted in the mounting board | substrate with which several semiconductor packages are mounted, and adjusts the delay time of each wiring which connects between semiconductor packages. FIG. 18 is a cross-sectional view illustrating an example of mounting the delay circuit schematically illustrated in FIG. 17. When the delay circuit according to the second embodiment of the present invention is mounted in one of the semiconductor packages on which a plurality of semiconductor chips are mounted, and the delay time of each wiring of the semiconductor package connecting the semiconductor chips is adjusted It is a schematic diagram which illustrates this. FIG. 20 is a cross-sectional view illustrating an example of implementation of the delay circuit schematically illustrated in FIG. 19. A plurality of semiconductor packages are mounted, and the delay circuit according to the second embodiment of the present invention is mounted on a mounting substrate in which a plurality of semiconductor chips are mounted in one of the semiconductor packages, and each wiring connecting the semiconductor chips It is a schematic diagram which illustrates the case where the delay time of is adjusted. It is a flowchart which shows the operation | movement flow about adjustment of the delay time in the delay circuit by the 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1A, 1B Delay circuit 2, 2A, 2B Semiconductor chip 11 JTAG interface 12 Delay element 13 Memory element 14 Control circuit 15 Interface 16 Switch 17 Measuring element 21 Control circuit 22 Signal generator 23 Input switch 24 Output switch 25 Delay tap switching device 26 Delay element 27 Delay time measuring device 31 Control register 32 Measurement data register 40 Land 41 Solder ball 42, 42 in, 42 out, 46 in, 46 out Bump 43 Sealing resin 44 Pad 50, 51, 52, 53, 54, 55, 56 Wiring 100 Wiring board 121 Input buffer 122 Input terminal 123 Output driver 124 Output terminal 125 Measuring terminal 126 Measuring reference wiring 200 Mounting board 300, 300A, 300B, 300C, 300D Semiconductor pad Over di

Claims (23)

A delay circuit for adjusting a delay time of signal propagation of each wiring of a wiring board,
An interface for instructing the setting of the delay time;
A delay element programmable to an arbitrary delay time;
With
A delay circuit, wherein a delay time of the delay element is set by an instruction from the interface. A storage element for storing a parameter defining the delay time;
The delay circuit according to claim 1, wherein a delay time of the delay element is set based on the parameter according to an instruction from the interface.   The delay circuit according to claim 2, wherein the delay element is connected to each of an input end and an output end of each wiring of the wiring board. Each of the delay elements is
In the measurement mode, a signal generator that transmits a propagation time measurement signal toward the wiring of the wiring board for which the delay time is to be set;
In the measurement mode, receiving means for receiving the propagation time measurement signal reflected on the wiring of the wiring board to set the delay time;
In the measurement mode, the time difference between the time when the receiving means receives the signal for measuring propagation time and the time when the signal generator transmits the signal for measuring propagation time is measured, and the time is half the time difference. Measuring means as a signal propagation time for the wiring of the wiring board to set the delay time,
The time difference between the maximum signal propagation time among the signal propagation times measured for each wiring of the wiring board and the signal propagation time measured for the wiring of the wiring board for which the delay time is to be set is defined as the delay time. The delay circuit according to claim 3, further comprising: determining means for determining the delay time of the wiring of the wiring board to be set. Each of the delay elements has signal reflecting means for reflecting the propagation time measurement signal received in the measurement mode,
In the measurement mode, the propagation time measurement signal transmitted from the signal generator in the delay element connected to one terminal of the wiring of the wiring board on which the delay time is to be set is set to the delay time. 5. The delay circuit according to claim 4, wherein the signal is reflected by the signal reflecting means in the delay element connected to the other terminal of the wiring of the wiring board to be set. The delay circuit according to claim 3, further comprising a measuring element that measures a signal propagation time of a wiring of a wiring board to set a delay time.
The measuring element is
In the measurement mode, a signal generator that transmits a propagation time measurement signal toward the measurement reference wiring connected to the measurement element;
In the measurement mode, receiving means for receiving the propagation time measurement signal reflected on the measurement reference wiring;
In the measurement mode, the time difference between the time when the receiving means receives the signal for measuring propagation time and the time when the signal generator transmits the signal for measuring propagation time is measured, and the time is half the time difference. Measuring means as a signal propagation time for the reference wiring for measurement,
A delay circuit.   The delay circuit includes the wiring board estimated from the ratio of the wiring design length of the wiring board to which the delay time is to be set and the length of the measurement reference wiring using the signal propagation time for the measurement reference wiring. The time difference between the maximum signal propagation time among the signal propagation times for each of the wirings and the signal propagation time estimated for the wiring of the wiring board for which the delay time is to be set is the wiring for which the delay time is to be set. The delay circuit according to claim 6, further comprising a determining unit that determines the delay time of the wiring on the substrate.   The delay circuit according to claim 4, wherein the parameter that defines the delay time determined by the determination unit is stored in the storage element.   The delay circuit according to claim 4, wherein the signal propagation time for each wiring of the wiring board measured by the measuring means can be read out to the outside through the interface.   The delay circuit according to claim 6, wherein the signal propagation time for the measurement reference wiring measured by the measurement unit can be read out to the outside via the interface.   The delay circuit according to claim 1, wherein the interface is a JTAG interface. A delay circuit for adjusting a delay time of signal propagation of each wiring of a wiring board,
The delay circuit includes a delay element programmable to an arbitrary delay time connected to each of an input end and an output end of each wiring of the wiring board,
Each of the delay elements is
In the measurement mode, a signal generator that transmits a propagation time measurement signal toward the wiring of the wiring board for which the delay time is to be set;
In the measurement mode, receiving means for receiving the propagation time measurement signal reflected on the wiring of the wiring board to set the delay time;
In the measurement mode, the time difference between the time when the receiving means receives the signal for measuring propagation time and the time when the signal generator transmits the signal for measuring propagation time is measured, and the time is half the time difference. Measuring means as a signal propagation time for the wiring of the wiring board to set the delay time,
The time difference between the maximum signal propagation time among the signal propagation times measured for each wiring of the wiring board and the signal propagation time measured for the wiring of the wiring board for which the delay time is to be set is defined as the delay time. And a calculation means for programming the delay element as a delay time of the wiring of the wiring board to be set. A delay circuit for adjusting a delay time of signal propagation of each wiring of a wiring board,
The delay circuit is
A delay element programmable to an arbitrary delay time connected to each of the input end and the output end of each wiring of the wiring board,
A measuring element for measuring the signal propagation time of the reference wiring for measurement provided on the wiring board on which the delay time is to be set;
With
The measuring element is
In the measurement mode, a signal generator that transmits a propagation time measurement signal toward the measurement reference wiring connected to the measurement element;
In the measurement mode, receiving means for receiving the propagation time measurement signal reflected on the measurement reference wiring;
In the measurement mode, the time difference between the time when the receiving means receives the signal for measuring propagation time and the time when the signal generator transmits the signal for measuring propagation time is measured, and the time is half the time difference. Measuring means as a signal propagation time for the reference wiring for measurement,
For each wiring of the wiring board estimated using the signal propagation time for the measurement reference wiring from the ratio of the wiring design length of the wiring board to which the delay time should be set and the length of the measurement reference wiring The time difference between the maximum signal propagation time of the signal propagation times and the signal propagation time estimated for the wiring of the wiring board for which the delay time is to be set is the delay of the wiring of the wiring board for which the delay time is to be set. A delay circuit comprising: calculation means for programming the delay element as time. The wiring board is a mounting board on which a plurality of semiconductor packages are mounted,
The delay circuit according to claim 1, wherein each wiring of the wiring board is a wiring of the mounting board that connects the semiconductor packages. The wiring board is a semiconductor package on which a plurality of semiconductor chips are mounted,
The delay circuit according to claim 1, wherein each wiring of the wiring board is a wiring of the semiconductor package that connects the semiconductor chips. A delay time adjustment method for adjusting a delay time of signal propagation of each wiring of a wiring board,
Based on the signal propagation time measured in advance for the wiring of the wiring board on which the delay time is to be set, it is programmed to an arbitrary delay time provided as a delay circuit at each of the input end and output end of each wiring of the wiring board. A delay time adjusting method, wherein a delay time is programmed for a possible delay element. A delay time adjustment method for adjusting a delay time of signal propagation of each wiring of a wiring board,
In the measurement mode, a propagation time measurement signal is transmitted from the terminal of the wiring board to which the delay time is to be set to the wiring of the wiring board to which the delay time is to be set from the terminal to which the delay circuit is to be connected. Sending step;
In the measurement mode, a reception step of receiving the propagation time measurement signal reflected in the wiring of the wiring board to set the delay time;
In the measurement mode, a time difference between the time when the propagation time measurement signal is received in the reception step and the time when the propagation time measurement signal is transmitted in the transmission step is calculated, and a time half of the time difference is calculated. A measurement step of measuring the delay time as a signal propagation time for the wiring of the wiring board to be set;
The time difference between the maximum signal propagation time among the signal propagation times measured for each wiring of the wiring board and the signal propagation time measured for the wiring of the wiring board for which the delay time should be set is the delay. A calculation step for determining the time as the wiring delay time of the wiring board to be set;
A setting step of programming the delay time to a delay element programmable as an arbitrary delay time provided as the delay circuit connected to the wiring of the wiring board;
A delay time adjustment method comprising: A delay time adjustment method for adjusting a delay time of signal propagation of each wiring of a wiring board,
A transmission step of transmitting a propagation time measurement signal from the measurement terminal provided on the wiring board to which the delay time is to be set to the measurement reference wiring connected to the measurement terminal in the measurement mode; ,
In the measurement mode, a reception step of receiving the propagation time measurement signal reflected by the measurement reference wiring;
In the measurement mode, the time difference between the time at which the propagation time measurement signal is received at the reception step and the time at which the propagation time measurement signal is transmitted at the transmission step is measured, and half the time difference is calculated. Measuring step for measuring signal propagation time for the reference wiring for measurement;
For each wiring of the wiring board estimated using the signal propagation time for the measurement reference wiring from the ratio of the wiring design length of the wiring board to which the delay time should be set and the length of the measurement reference wiring The time difference between the maximum signal propagation time of the signal propagation times and the signal propagation time estimated for the wiring of the wiring board to which the delay time is to be set is determined as the time difference between the wiring of the wiring board to which the delay time is to be set. A calculation step to determine the delay time;
A setting step of programming the delay time in a delay element that is provided as a delay circuit connected to the wiring of the wiring board and can be programmed to an arbitrary delay time;
A delay time adjustment method comprising:   19. The delay time adjusting method according to claim 18, further comprising a forming step of forming the measurement reference wiring on a wiring board provided with a wiring for which a delay time is to be set.   The delay time adjusting method according to claim 19, wherein one end of the measurement reference wiring is connected to the measurement terminal, and the other end is grounded via a resistor.   The delay time adjusting method according to claim 19, wherein one end of the measurement reference wiring is connected to the measurement terminal and the other end is opened. The wiring board is a mounting board on which a plurality of semiconductor packages are mounted,
19. The delay time adjusting method according to claim 16, wherein each wiring of the wiring board is a wiring of the mounting board that connects the semiconductor packages. The wiring board is a semiconductor package on which a plurality of semiconductor chips are mounted,
19. The delay time adjusting method according to claim 16, wherein each wiring of the wiring board is each wiring of the semiconductor package that connects the semiconductor chips.

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