JP2018164242A - Semiconductor integrated circuit, semiconductor device, and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce or eliminate influence of signal reflection in a redistribution layer while suppressing increase in the size of the redistribution layer.SOLUTION: The semiconductor integrated circuit is incorporated in a semiconductor chip connected to external connection terminals via a redistribution layer. The semiconductor integrated circuit includes: measuring means for measuring signal reflection characteristics in the redistribution layer; output means for outputting a signal to the redistribution layer; and adjustment means for adjusting a phase of the signal output by the output means on the basis of the reflection characteristics obtained as a result of the measurement.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit, a semiconductor device, and a method.

  In the market of mass-produced products such as portable terminals and wireless devices, higher electrical performance and thermal management capability, further cost reduction, further miniaturization and higher integration are desired. Under such circumstances, a packaging technique for embedding components at the wafer level / panel level has been attracting attention as a promising technique that can meet the needs of thinning the package, improving the integration capability, and improving the technical performance. In particular, fan-out wafer level packages (hereinafter referred to as “FOWLP”) are highly anticipated, and in the future, the current mainstream flip chip ball grid array (hereinafter referred to as “FCBGA”) is expected. ).

  In general FCBGA, a rewiring layer (Re-Distribution Layer, RDL) is used to connect a die and a package bump, a package substrate is used to connect a package bump and a ball, and a ball is used. A configuration is adopted in which the package and the printed circuit board are connected. On the other hand, FOWLP has a configuration in which a rewiring layer is used to directly connect a die and a printed board.

  In order to establish the FOWLP configuration, the FOWLP redistribution layer additionally has a function of connecting the package bump and the ball carried by the FCBGA package substrate in addition to the function of connecting the conventional die and the package bump. . For this reason, the wiring of the FOWLP rewiring layer is generally longer than the wiring of the FCBGA rewiring layer.

  Due to the increase in the wiring length, signal reflection in the rewiring layer, which has been negligible with FCBGA having a relatively short wiring length, cannot be ignored. Patent Documents 1 and 2 disclose a technique for performing impedance management of a transmission line and impedance matching at the boundary of a die package printed board in a FOWLP redistribution layer.

JP 2010-4219 A JP2011-239467A

  In addition to the methods described in Patent Literature 1 and Patent Literature 2, there is also a method of providing a reference plane and a guard GND as a general impedance management method. However, when the reference plane and the guard GND are provided in the rewiring layer, the size of the rewiring layer is increased, and downsizing which is the original aim is hindered. Also, from the viewpoint of bondability (heat and warpage), an increase in the size of the rewiring layer is not preferable. This is because the bondability with a die or a printed circuit board deteriorates. Therefore, a means for reducing or eliminating the influence of reflection on the rewiring layer on the operation of the semiconductor integrated circuit by a method other than the reference plane and the guard GND is required.

  The present invention has been made in view of these problems, and an object thereof is to provide a technique capable of reducing or eliminating the influence of signal reflection in the rewiring layer while suppressing an increase in the size of the rewiring layer.

  One embodiment of the present invention relates to a semiconductor integrated circuit. This semiconductor integrated circuit is a semiconductor integrated circuit incorporated in a semiconductor chip connected to an external connection terminal via a rewiring layer, and includes a measuring means for measuring the signal reflection characteristics in the rewiring layer, Output means for outputting to the rewiring layer, and adjusting means for adjusting the phase of the signal output by the output means based on the reflection characteristics obtained as a result of the measurement.

  Another embodiment of the present invention is a semiconductor device. The semiconductor device includes a semiconductor chip and a rewiring layer provided between the semiconductor chip and the external connection terminal. The semiconductor chip is output by the output means based on the measurement means for measuring the reflection characteristic of the signal in the rewiring layer, the output means for outputting the signal to the rewiring layer, and the reflection characteristic obtained as a result of the measurement. Adjusting means for adjusting the phase of the signal.

  Yet another embodiment of the present invention is a semiconductor integrated circuit. This semiconductor integrated circuit is a semiconductor integrated circuit incorporated in a semiconductor chip connected to an external connection terminal via a rewiring layer, and measuring means for measuring the signal reflection characteristics in the rewiring layer, and rewiring Input means for receiving a signal input from the layer, and adjusting means for adjusting the phase of the signal received by the input means based on the characteristic of reflection obtained as a result of the measurement.

  Yet another embodiment of the present invention is a semiconductor device. The semiconductor device includes a semiconductor chip and a rewiring layer provided between the semiconductor chip and the external connection terminal. The semiconductor chip has a measuring means for measuring a signal reflection characteristic in the rewiring layer, an input means for receiving a signal input from the rewiring layer, and a signal received by the input means based on a reflection characteristic obtained as a result of the measurement. And adjusting means for adjusting the phase of.

  According to the present invention, it is possible to reduce or eliminate the influence of signal reflection in the rewiring layer while suppressing an increase in the size of the rewiring layer.

Sectional drawing which shows typically FOWLP of the semiconductor chip in which the semiconductor integrated circuit which concerns on 1st Embodiment was integrated. The wave form diagram which shows the data signal and clock signal which are each output from the 1st solder ball and the 2nd solder ball. FIG. 2 is a block diagram showing a basic configuration of the semiconductor integrated circuit of FIG. 1. 2 is a chart showing an operation flow in the semiconductor integrated circuit of FIG. 1. The schematic diagram which shows the voltage of the reflected wave detected by the voltage detection part of FIG. FIG. 4 is a data structure diagram illustrating an example of a voltage table in FIG. 3. FIG. 4 is a flowchart showing a flow of a series of processes in a delay calculation unit in FIG. 3. FIG. The data structure figure showing an example of the 1st table. The data structure figure showing an example of the updated 1st table. FIG. 4 is a data structure diagram illustrating an example of a reference table in FIG. 3. The data structure figure showing an example of the 2nd table. The data structure figure which shows an example of a data setting table. The data structure figure showing an example of a clock setting table. 14A and 14B are explanatory diagrams of a clock output unit. The block diagram which shows the structure of a data output part. The block diagram which shows the basic composition of the semiconductor integrated circuit which concerns on 2nd Embodiment. The block diagram which shows the structure of a clock input part and a data input part. The data structure figure which shows an example of the part of the setting value for input of an input / output setting table. FIG. 5 is a block diagram showing a basic configuration of a semiconductor integrated circuit according to a third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. However, embodiments of the present invention are not limited to the following embodiments. The same or equivalent components, members, processes, and signals shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. In addition, in the drawings, some of the members that are not important for explanation are omitted.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing FOWLP 12 of a semiconductor chip 10 in which the semiconductor integrated circuit according to the first embodiment is incorporated. The FOWLP 12 is a semiconductor device, and includes a semiconductor chip 10, a rewiring layer 14, a sealing resin 16, and solder balls 18. The semiconductor chip 10 is electrically connected to a plurality of solder balls 18 that are external connection terminals via the rewiring layer 14.

  The semiconductor chip 10 includes a first I / O pad 10a that outputs a data signal generated by the semiconductor integrated circuit, and a second I / O pad 10b that outputs a clock signal generated by the semiconductor integrated circuit. Each I / O pad 10a, 10b is connected to the first solder ball 18a and the second solder ball 18b via the rewiring layer 14, respectively. The data signal is generated so that the edge of the data signal corresponds to the edge of the clock signal.

  FIG. 2 is a waveform diagram showing a data signal and a clock signal output from the first solder ball 18a and the second solder ball 18b, respectively. When designing a semiconductor integrated circuit, the rewiring layer 14 is treated as a transmission line without reflection, that is, a transmission line without impedance mismatch. Under this premise, an ideal waveform in which data signals and clock signals (hereinafter referred to as output data signals and output clock signals) respectively output from the first solder balls 18a and the second solder balls 18b are indicated by broken lines in FIG. A semiconductor integrated circuit is designed to have Specifically, the delay of the data signal and the clock signal output from the first I / O pad 10a and the second I / O pad 10b is adjusted.

In an ideal state, the edge of the output data signal and the corresponding edge of the output clock signal are aligned. Specifically, it is as follows. The timing t _m is a timing at which the output clock signal passes the half value Vm of the operating voltage (that is, amplitude). The timing t _L is a timing at which the output data signal passes through the low-side threshold voltage V _L of the semiconductor integrated circuit. The timing t _H, and the timing at which the output data signal passes through the threshold voltage V _H of the high-side of the semiconductor integrated circuit. The phase difference between the data signal and the clock signal is adjusted so that t _m −t _L and t _H −t _m are ideal values.

In the present embodiment, V _L and V _H are 20% and 80% of the operating voltage, respectively. That is, when the operating voltage is 1200 mV, _{V L} is 240 mV, _{V H} is 960 mV, Vm becomes 600 mV.

In reality, as described above, the rewiring layer 14 has a reflection that cannot be ignored. This reflection distorts the data signal and the clock signal. The solid lines in FIG. 2 indicate the waveforms of the output data signal and the output clock signal that are distorted by reflection in the rewiring layer 14. Due to the influence of reflection, the timing t _m becomes the timing t _m ′, the timing t _L becomes the timing t _L ′, and the timing t _H becomes the timing t _H ′. t _m '-t _L ' and t _H '-t _m ' deviate from ideal values, respectively.

In the present embodiment, the reflection characteristic is measured on the assumption that the reflection occurs, instead of reducing the reflection. The semiconductor integrated circuit estimates the amount of deviation from an ideal state based on the measured reflection characteristics, and adjusts the phase of the signal output from the semiconductor chip 10 so as to reduce the deviation. In the example of FIG. 2, since t _m −t _L > t _m ′ −t _L ′ and t _H −t _m <t _H ′ −t _m ′, those signals are delayed so as to delay the data signal with respect to the clock signal. Is adjusted. Thereby, the influence on the signal by reflection can be reduced.

  FIG. 3 is a block diagram showing a basic configuration of the semiconductor integrated circuit 102 according to the first embodiment. As described above, the semiconductor integrated circuit 102 is incorporated in the semiconductor chip 10, and the rewiring layer 14 is provided between the semiconductor integrated circuit 102 and the external device 107. The external device 107 includes a printed circuit board 201 and a counter integrated circuit 202. The rewiring layer 14 connects the semiconductor integrated circuit 102 and the external device 107 by wiring. Specifically, the rewiring layer 14 connects an I / O pad of the semiconductor integrated circuit 102 and a solder ball that is an external connection terminal, and the solder ball is attached to a solder bump of the printed circuit board 201 included in the external device 107. .

  The semiconductor integrated circuit 102 includes a reflection measurement unit 103, a timing adjustment unit 104, an input / output unit 105, and an internal circuit 106. The reflection measuring unit 103 measures the characteristic of signal reflection caused by impedance mismatch in the rewiring layer 14. The reflection measurement unit 103 may output a pulse wave for measurement to the data signal wiring through which the data signal passes among the wirings included in the rewiring layer 14, and measure the reflection characteristics of the wiring. Alternatively, the reflection measuring unit 103 may output a pulse wave to the clock signal wiring through which the clock signal passes to measure the reflection characteristics of the wiring. Alternatively, the reflection measuring unit 103 may output a pulse wave to a wiring dedicated for reflection measurement and measure the reflection characteristics of the wiring. In this case, the semiconductor integrated circuit 102 may apply the measurement result of the wiring dedicated for reflection measurement to the data signal wiring and the clock signal wiring. The timing adjustment unit 104 adjusts the phase of the data signal and / or clock signal output from the input / output unit 105 based on the reflection characteristics obtained as a result of the measurement by the reflection measurement unit 103. For example, the timing adjustment unit 104 calculates a phase adjustment amount. The input / output unit 105 outputs a data signal and a clock signal to the rewiring layer 14 according to the adjustment amount calculated by the timing adjusting unit 104 and receives an input of the data signal and the clock signal from the rewiring layer 14. The internal circuit 106 is a circuit that implements functions such as image processing, compression / decompression processing, encryption / decryption, communication processing, volatile memory, and nonvolatile memory. In many large-scale semiconductor integrated circuits (Large Scale Integration, LSI), dozens of internal circuits are often integrated.

  The reflection measurement unit 103 includes a command transmission / reception unit 401, a pulse wave generation unit 402, a reflection input / output unit 403, and a voltage detection unit 404. The timing adjustment unit 104 includes a timing control unit 601, a voltage table 602, a delay calculation unit 603, a reference table 604, and a setting table 605. The input / output unit 105 includes a clock output unit 1001 and a data output unit 1002. FIG. 4 is a chart showing an operation flow in the semiconductor integrated circuit 102. Hereinafter, the overall operation of the present embodiment will be described with reference to FIGS. The operation of this embodiment is performed in an initialization sequence before the semiconductor integrated circuit 102 starts normal operation.

  In S300, after Power On Reset, the timing control unit 601 transmits a delay adjustment command to the command transmission / reception unit 401, and the command transmission / reception unit 401 receives the delay adjustment command. In S <b> 301, the command transmission / reception unit 401 receives the delay adjustment command and transmits an operation start instruction to the pulse wave generation unit 402. Receiving the instruction, the pulse wave generation unit 402 generates a pulse wave and issues the generated pulse wave to the reflection input / output unit 403. In S <b> 302, the reflection input / output unit 403 outputs the pulse wave received toward the rewiring layer 14 after receiving the pulse wave. Thereafter, the pulse wave propagating through the rewiring layer 14 returns to the reflection input / output unit 403 as a reflected wave at a location where an impedance mismatch has occurred. In step S303, the reflection input / output unit 403 receives the reflected wave that has returned in this manner.

  In S304, the reflection input / output unit 403 outputs the received reflected wave to the voltage detection unit 404, and the voltage detection unit 404 detects the amplitude (that is, voltage) of the reflection wave. In step S <b> 305, the command transmission / reception unit 401 transmits a ready signal indicating that detection data indicating the detection result is ready to the timing adjustment unit 104 after a preset detection period has elapsed. The timing control unit 601 receives a ready signal. The detection period may be derived in advance based on information on the wiring length and the dielectric constant of the material. Further, the command transmission / reception unit 401 may detect the passage of the detection period using a counter circuit (not shown).

  In step S <b> 306, the timing control unit 601 sends a data request signal for requesting detection data to the reflection measurement unit 103 in accordance with the ready signal. The command transmission / reception unit 401 receives a data request signal. In step S <b> 307, the command transmission / reception unit 401 instructs the voltage detection unit 404 to send detection data to the timing adjustment unit 104 in response to the data request signal. In response to the instruction, the voltage detection unit 404 transmits detection data to the timing adjustment unit 104. The timing control unit 601 stores the detection data transmitted from the voltage detection unit 404 in the voltage table 602.

  After the storage of the detection data in the voltage table 602 is completed, in S308, the timing control unit 601 issues a calculation start instruction to the delay calculation unit 603. In step S <b> 309, the delay calculation unit 603 that has received the calculation start instruction calculates a delay amount using the reference table 604 and stores the result in the setting table 605. Details of the operation in the delay calculation unit 603 will be described later.

  In step S <b> 310, the timing control unit 601 transmits the data in the setting table 605 to the input / output unit 105. The input / output unit 105 writes the received data to a register that determines the operation mode of the clock output unit 1001 and the data output unit 1002. Thereby, the influence of reflection on the signals output from the clock output unit 1001 and the data output unit 1002 can be reduced.

  Various parameters used in the measurement of reflection characteristics in the reflection measurement unit 103 will be described. As a premise of the present embodiment, it is assumed that the wiring length from the semiconductor integrated circuit 102 to the external device 107 is about 3.5 cm. First, the detection period in the voltage detection unit 404 is estimated. In this embodiment, the propagation speed of the signal is approximated, and the period necessary for detection is calculated from the calculation result.

This will be specifically described below. First, the propagation speed of the signal is estimated. In this embodiment, the speed of light is estimated to be 300 × 10 ⁸ cm / sec and the effective relative dielectric constant is 3.5. Since the value of the effective relative dielectric constant is determined by the material, it is not necessarily 3.5.
Propagation speed = speed of light / SQRT (effective relative dielectric constant) ≒ 16 cm / nsec

Next, the time required to propagate the wiring length of 3.5 cm is calculated.
Propagation time = wiring length / propagation speed ≒ 219psec
Here, the reflected wave of the propagating signal is detected not when the reflection occurs but after returning to the reflection measuring unit 103, and therefore, the reflected wave is the time until the reflection occurs (one-way propagation time). It cannot be detected unless the time is nearly double. That is, a minimum period of 438 psec (219 psec × 2) is required as the detection period. In this embodiment, the length of the detection period is set to 1000 psec with a margin for reasons described later.

  Further, with respect to the amplitude and slew rate of the pulse wave output from the pulse wave generation unit 402, generally, the higher the slew rate of the pulse wave, the higher the accuracy of reflection detection. However, even when a slew rate that is significantly different from the slew rate used during actual operation is used, such reflection does not occur during actual operation. Therefore, the slew rate of the pulse wave may be determined based on the slew rate during actual operation. The amplitude of the pulse wave may be set to an amplitude that can realize the above-described slew rate and is close to the amplitude during actual operation.

  In this embodiment, the minimum amplitude of the pulse wave generated by the pulse wave generation unit 402 is 500 mV, the sampling period of the voltage detection unit 404 is 50 psec, and the slew rate during actual operation is 20 V / ns, 15 V / ns, 10 V / Ns and 5V / ns. In that case, the pulse wave generation unit 402 needs to generate a pulse wave having an amplitude of 500 mV or more, a rise time earlier than 50 psec, and a slew rate close to 20 V / ns. In this embodiment, the amplitude of the pulse wave is 1000 mV and the slew rate is 20 V / ns.

  Upon receiving an instruction from the command transmission / reception unit 401, the pulse wave generation unit 402 outputs a pulse wave having an amplitude of 1000 mV and a slew rate of 20 V / ns to the rewiring layer 14 via the reflection input / output unit 403. The voltage detection unit 404 determines whether or not the 1000 psec detection period has expired using a counter circuit (not shown) and the like, and detects the reflected voltage of the pulse wave until the detection period expires.

  FIG. 5 is a schematic diagram illustrating the voltage of the reflected wave detected by the voltage detection unit 404. When there is no reflection, the amplitude Ei of the pulse wave is detected as it is, and when the reflection occurs, the amplitude of the pulse wave changes by the reflected amount Er. Er1 to Er6 represent the state of reflection for each sampling period. By recording the time and the detected voltage at that time, the reflection characteristics in the rewiring layer 14 can be obtained. The reflection characteristic may be data indicating how much reflection is present at which time, and may be expressed as a reflection profile.

  Returning to FIG. 3, the timing adjustment unit 104 will be described in more detail. The timing control unit 601 sends a delay adjustment command to the reflection measurement unit 103 to cause the reflection measurement unit 103 to start measurement. When the timing control unit 601 receives a ready signal indicating detection completion from the reflection measurement unit 103, the timing control unit 601 acquires detection data from the voltage detection unit 404 and stores the detection data in the voltage table 602.

  The adjustment target in the timing adjustment unit 104 is reflection in the rewiring layer 14. Therefore, reflection on the printed circuit board 201 and the counter integrated circuit 202 outside the rewiring layer 14 is out of adjustment, and detection data indicating the reflection may not be stored in the voltage table 602. As a result, the amount of memory required for storing the voltage table 602 can be reduced. Note that relatively large reflection occurs at the boundary between the rewiring layer 14 and the printed circuit board 201 and the boundary between the printed circuit board 201 and the counter integrated circuit 202, and thus the reflection measurement unit 103 reflects the reflection of the three elements. It is possible to specify which occurred.

  In this embodiment, in order to make the explanation easy to understand, the detection period corresponding to the rewiring layer 14 is set to 50 psec to 450 psec, but this detection period is determined according to the length of the wiring on the rewiring layer 14. The rewiring layer 14 is different. In the present embodiment, the detection period is set to 1000 psec in order to reliably detect the boundary between the rewiring layer 14 and the printed circuit board 201 and the boundary between the printed circuit board 201 and the counter integrated circuit 202. Thereby, reflection in all elements of the rewiring layer 14, the printed board 201, and the counter integrated circuit 202 can be detected.

  If transmission simulation or the like is used, timing corresponding to the boundary between the rewiring layer 14 and the printed circuit board 201 and timing corresponding to the boundary between the printed circuit board 201 and the counter integrated circuit 202 can be predicted in advance. In that case, a detection period during which only the reflection data of the rewiring layer 14 can be collected may be set in advance.

  FIG. 6 is a data structure diagram showing an example of the voltage table 602 of FIG. The voltage table 602 holds the detection time and the detection voltage at the detection time in association with each other. The data after 450 psec becomes data of the printed circuit board 201 ahead of the rewiring layer 14 and is not stored in this table because it is unnecessary for adjustment in the timing adjustment unit 104. In this embodiment, the sampling period is 50 psec, and the voltage is detected every 50 psec. Therefore, the detection time is 50 psec.

  FIG. 7 is a flowchart showing a flow of a series of processes in the delay calculation unit 603 of FIG. The timing control unit 601 issues a delay calculation instruction to the delay calculation unit 603, and the delay calculation unit 603 starts the processing flow shown in FIG. In S701, the delay calculation unit 603 reads data from the voltage table 602, and converts the data into reflection data including the actual reflection time and reflection amount. The reflected wave is not detected at the time when the reflection actually occurs, but is detected at the round trip time that is the sum of the time when the reflected wave returns to the reflection measuring unit 103 at the time when the reflection occurs. Correction is performed. Specifically, the delay calculation unit 603 converts the detection time into the time (one-way time) at which actual reflection occurs. Further, since the detection voltage is a voltage including reflection, the delay calculation unit 603 subtracts the voltage including reflection from the voltage without reflection to calculate the reflection amount. Specifically, the amplitude of the pulse wave in the present embodiment is 1000 mV. Therefore, the detection voltage when there is no reflection is 1000 mV. For example, when the detection voltage including reflection is 983 mV, the reflection amount is calculated as 1000 mV−983 mV = 17 mV. The delay calculation unit 603 refers to the voltage table 602, calculates the reflection time and the reflection amount as described above, and stores them in the first temporary table 650 for calculation. FIG. 8 is a data structure diagram illustrating an example of the first table 650. The first table 650 holds the reflection time, which is the time when actual reflection occurs, the detection voltage, and the reflection amount in association with each other.

  Returning to FIG. 7, in S702, the delay calculation unit 603 scales the reflection amount according to the operating voltage. The delay calculation unit 603 performs a process of scaling the reflection amount according to the actual operating voltage when the voltage amplitude of the pulse wave and the amplitude of the actual operating voltage are different. When the amplitude of the pulse wave and the amplitude of the actual operating voltage are the same, this processing may be skipped. When the actual operating voltage in this embodiment is 1200 mV, the amplitude of the pulse wave is 1000 mV. Therefore, if the amount of reflection (reflection voltage) detected corresponding to the pulse wave is multiplied by 1.2, the reflection voltage during actual operation is scaled. The delay calculation unit 603 refers to the first table 650 and updates the first table 650 by performing the above-described scaling processing on the reflection amount held there. FIG. 9 is a data structure diagram illustrating an example of the updated first table 650.

  Returning to FIG. 7, in S703, the delay calculation unit 603 reads the data of the reference table 604 for delay calculation, and combines the result obtained in S702 with the read data to generate combined data. The delay calculation unit 603 superimposes (adds) the reflected waveform data derived in S702 on the voltage waveform data that is obtained in advance by simulation or the like and assumes the actual operation, and the voltage waveform during the actual operation taking reflection into consideration. Generate data.

  FIG. 10 is a data structure diagram illustrating an example of the reference table 604. The reference table 604 is derived in advance by performing a simulation such as a transmission line simulation or a timing simulation. The delay calculation unit 603 stores composite data, which is a result of superimposing the updated data in the first table 650 on the data in the reference table 604, in the temporary second table 652 for calculation.

  FIG. 11 is a data structure diagram illustrating an example of the second table 652. The second table 652 holds the time, the non-reflection amplitude that is the amplitude of the waveform when there is no reflection, and the reflected amplitude that is the amplitude of the waveform when there is reflection. In FIG. 11, the column of reflection non-amplitude [mV] contains values derived from a simulation performed in advance on the assumption that there is no reflection in the rewiring layer 14. The column of the reflection amplitude [mV] contains a value obtained by adding the amount of reflection updated in S702 to the value of the column of no reflection amplitude [mV]. Specifically, the reflection no-amplitude corresponding to time = 50 psec is 234 mV, and this is also true for the lookup table 604 shown in FIG. Referring to the updated first table 650 shown in FIG. 9, the updated reflection amount for reflection time = 50 psec is 20 mV. Therefore, in the second table 652 of FIG. 11, the reflection amplitude corresponding to time = 50 psec is 234 mV−20 mV = 214 mV.

In the present embodiment, _VL is 240 mV as described above. Therefore, the closest reflection-free amplitude _{V L} in the second table 652 shown in FIG. 11 is 244MV. Therefore, the timing t _L when the data signal reaches V _L when there is no reflection is 52 psec. On the other hand, the nearest reflecting write amplitude _{V L} in the second table 652 shown in FIG. 11 is 243MV. Therefore, the timing t _L ′ at which the data signal reaches _VL when there is reflection is 56 psec.

In the present embodiment, V _H is 960 mV as described above. Therefore, the reflection non-amplitude closest to V _H in the second table 652 shown in FIG. 11 is 956 mV. Therefore, the timing t _H when the data signal reaches V _H when there is no reflection is 204 psec. On the other hand, in the second table 652 shown in FIG. 11, the reflection amplitude closest to V _H is 963 mV. Therefore, the length of the period until the timing t _H ′ when the data signal reaches V _H when there is reflection is 216 psec.

In the present embodiment, Vm is 600 mV as described above. Therefore, the reflection non-amplitude closest to Vm in the second table 652 shown in FIG. 11 is 600 mV. Therefore, the timing t _m when the clock signal reaches Vm when there is no reflection is 128 psec. On the other hand, the reflection amplitude closest to Vm in the second table 652 shown in FIG. 11 is 599 mV. Therefore, the timing t _m ′ when the clock signal reaches Vm when there is reflection is 130 psec.

Returning to FIG. 7, in S704, the delay calculation unit 603 calculates how much the period until the threshold voltage is reached varies depending on the presence or absence of reflection (delay variation due to reflection). The Figure 11 are shown the calculation result is, _{V L t L} -t _L for '= 4 psec, _t for _{V H H -t H' = 12psec} , t m -t m for Vm '= 2 psec This is the amount of blurring.

In step S <b> 705, the delay calculation unit 603 determines whether or not to adjust the phase of the clock signal and the data signal from the magnitude of the shake amount before the phase adjustment calculated in step S <b> 704. Specifically, the delay calculation unit 603 makes a determination by comparing the timing margin set in the timing verification at the time of design performed on the assumption that there is no reflection with the amount of blur. In this embodiment, the timing margin between the clock signal and the data signal is 9 psec. The timing margin is based on the difference between the timing when the data signal reaches V _H and the timing when the clock signal reaches Vm, and the difference between the timing when the clock signal reaches Vm and the timing when the data signal reaches _VL. Is set. The blur amount, which is the difference between these differences and the design value of the difference, is required to be smaller than the timing margin. In the example of FIG. 11, when t _H −t _m and t _m −t _L when there is no reflection are equal to the design values,
(T _H '−t _m ') -design value =
t _H '-t _m '-(t _H -t _m ) =
(T _H '-t _H )-(t _m ' -t _m ) =
12psec-2psec =
10 psec> 9 psec
The amount of blur exceeds the timing margin. Therefore, in S705, the delay calculation unit 603 determines to adjust the phase difference between the clock signal and the data signal.
If the blur amount does not deviate from the timing margin, the delay calculation unit 603 determines that no adjustment is performed, and skips S706 and S707, which will be described later.

  In step S <b> 706, the delay calculation unit 603 derives a phase adjustment amount between the clock signal and the data signal for canceling timing fluctuation due to reflection. The influence of the phase adjustment of the clock signal tends to be more extensive than the influence of the phase adjustment of the data signal. Therefore, in this embodiment, first, the data signal is phase-adjusted, and if the adjustment amount is still insufficient, the clock signal is phase-adjusted. It is not always necessary to follow this policy.

  The signal phase adjustment in this embodiment is performed by adjusting the delay amount of the signal set by the delay circuit, buffer, or capacitor capacity provided in the signal output stage of the semiconductor integrated circuit 102. In the present embodiment, the setting table 605 includes a data setting table 605a for data signals and a clock setting table 605b for clock signals.

FIG. 12 is a data structure diagram showing an example of the data setting table 605a. The data setting table 605a holds the data delay setting ID, the buffer driving force, the capacity of the on-die capacitor, and the delay amount achieved by these settings in association with each other. For example, when the data delay setting ID during actual operation is “00011100”, the setting of driving force = 8 mA and on-die capacity = 1.0 nF is selected, resulting in a delay of 40 psec. When this is changed to the data delay setting ID “00011101”, the setting is changed to driving force = 8 mA, on-die capacity = 1.2 nF, and the delay becomes 35 psec. As a result, the delay can be shortened by 5 psec by changing the setting. When this delay setting change is applied to the data signal, the difference between (t _H '-t _m ') and the design value is 10 psec-5 psec = 5 psec, and is suppressed to less than 9 psec. Thereby, the timing margin is satisfied. Even if the data delay setting ID is changed to “00111011” or “00011110”, the delay can be shortened as described above and the timing margin can be satisfied. At this time, which delay setting should be selected as the change destination is determined by conducting a simulation in advance to examine the effect on the signal quality when the driving force is changed and the effect on the signal quality when the on-die capacity is changed. You may decide according to a result. Note that if it is not possible to cope with only the delay adjustment of the data signal, the delay of the clock signal may be adjusted together.

  FIG. 13 is a data structure diagram showing an example of the clock setting table 605b. The clock setting table 605b holds the clock delay setting ID, the additional delay, the buffer driving force, the capacity of the on-die capacitor, and the delay amount achieved by these settings in association with each other.

  Returning to FIG. 7, in S707, the delay calculation unit 603 selects a delay setting ID corresponding to the delay amount derived in S706 from the setting table 605. The delay calculation unit 603 selects one of the 8-bit clock delay setting IDs with reference to the clock setting table 605b shown in FIG. The delay calculation unit 603 refers to the data setting table 605a shown in FIG. 12 for the data signal, and selects one of the 8-bit data delay setting IDs.

  After the processing of the delay calculation unit 603 is completed, the timing control unit 601 transmits the delay setting ID selected by the delay calculation unit 603 to the input / output unit 105. Thus, the operation of the timing adjustment unit 104 is completed.

  14A and 14B are explanatory diagrams of the clock output unit 1001. FIG. FIG. 14A is a block diagram showing a configuration of the clock output unit 1001, and FIG. 14B is a waveform diagram showing an image of a delayed clock. FIG. 15 is a block diagram illustrating a configuration of the data output unit 1002. Note that the configurations of the clock output unit 1001 and the data output unit 1002 are not limited to this, and any configuration may be employed as long as the circuit can generate a delay.

  The clock output unit 1001 includes a delay buffer unit 1101, a clock selection unit 1102, a clock delay setting unit 1103, and a clock buffer 1104. The delay buffer unit 1101 includes multi-stage delay buffers connected in series, and generates a plurality of delay clocks CD0, CD1, CD2, and CD3 with respect to the input clock CI (FIG. 14B). The plurality of delay clocks CD0, CD1, CD2, and CD3 are delayed from each other by a predetermined amount.

  The clock selection unit 1102 selects a specific delay clock from the plurality of delay clocks CD0, CD1, CD2, and CD3 provided from the delay buffer unit 1101. The clock selection unit 1102 selects a delay clock corresponding to the additional delay selected in the clock setting table 605 b and outputs the selected delay clock to the clock buffer 1104. Specifically, the clock selection unit 1102 receives the clock delay setting ID from the timing adjustment unit 104. The clock selection unit 1102 refers to the clock setting table 605b and identifies an additional delay corresponding to the received clock delay setting ID. The clock selection unit 1102 selects a delay clock that gives the specified additional delay from the plurality of delay clocks CD0, CD1, CD2, and CD3. In the example of FIG. 14B, a plurality of delay clocks CD0, CD1, CD2, and CD3 give additional delays of 0 psec, 25 psec, 50 psec, and 75 psec, respectively.

  The clock delay setting unit 1103 finely adjusts the delay by changing the operation setting of the clock buffer 1104, for example, the slew rate. The clock delay setting unit 1103 receives the clock delay setting ID from the timing adjustment unit 104. The clock delay setting unit 1103 refers to the clock setting table 605b and identifies the driving force and on-die capacity corresponding to the received clock delay setting ID. The clock delay setting unit 1103 sets the driving power and on-die capacity of the clock buffer 1104 to the specified driving power and on-die capacity. The clock buffer 1104 receives and buffers the delayed clock selected by the clock selection unit 1102 and outputs a clock signal CL. In addition to or instead of adjusting the driving force and the on-die capacity, the operating voltage of each delay buffer included in the delay buffer unit 1101 may be adjusted.

  The data output unit 1002 includes a data delay setting unit 1301 and a data buffer 1302. The data delay setting unit 1301 adjusts the delay of the data signal DT by changing the operation setting of the data buffer 1302, for example, the slew rate. The data delay setting unit 1301 receives the data delay setting ID from the timing adjustment unit 104. The data delay setting unit 1301 refers to the data setting table 605a and identifies the driving force and on-die capacity corresponding to the received data delay setting ID. The data delay setting unit 1301 sets the driving power and on-die capacity of the data buffer 1302 to the specified driving power and on-die capacity. The data buffer 1302 receives and buffers the data signal DI generated by the internal circuit 106, and outputs a data signal DT.

  According to the semiconductor integrated circuit 102 according to the present embodiment, the reflection characteristic in the rewiring layer 14 is measured, and the phase of the signal output from the semiconductor integrated circuit 102 is adjusted based on the measurement result. Thereby, the fluctuation | variation of the timing which arises by reflection of a signal can be suppressed. As a result, the reliability of the operation of the semiconductor integrated circuit 102 can be improved.

  Usually, there are individual differences in the reflection characteristics in the rewiring layer 14 due to manufacturing variations and the like, and it is difficult to predict with high accuracy. Even if reflection measures such as impedance matching are taken at the design stage, the effect of reflection is often not negligible in actual devices for the same reason. In this embodiment, it is possible to measure rather than suppress reflection and adaptively adjust the signal for each package according to the measurement result, so that signal quality can be improved even in situations where it is difficult to predict reflection characteristics. Can do.

(Second Embodiment)
FIG. 16 is a block diagram showing a basic configuration of a semiconductor integrated circuit 1905 according to the second embodiment. The semiconductor integrated circuit 1905 is incorporated in the semiconductor chip 1906, and the rewiring layer 14 is provided between the semiconductor integrated circuit 1905 and the external device 107. The semiconductor integrated circuit 1905 includes a reflection measurement unit 103, a timing adjustment unit 1904, an input / output unit 1907, and an internal circuit 106. The timing adjustment unit 1904 includes an input / output setting table 1903 instead of the setting table 605 of the first embodiment. The input / output unit 1907 includes a clock output unit 1001, a data output unit 1002, a clock input unit 1901, and a data input unit 1902.

  FIG. 17 is a block diagram showing the configuration of the clock input unit 1901 and the data input unit 1902. The clock input unit 1901 includes a clock termination setting unit 2001 and a clock input buffer 2003. The data input unit 1902 includes a data end setting unit 2002 and a data input buffer 2004.

  The clock input buffer 2003 receives the input clock signal CLI from the counter integrated circuit 202 via the printed circuit board 201 and the rewiring layer 14. The clock input buffer 2003 performs a predetermined termination process set by the clock termination setting unit 2001 on the received input clock signal CLI and transmits the processed clock signal CLA to the internal circuit 106. The phase of the post-processing clock signal CLA is adjusted by the termination process.

  The input / output setting table 1903 holds setting values for adjusting the phase of the input signal, in addition to the output setting values shown in the first embodiment. FIG. 18 is a data structure diagram showing an example of a setting value portion 1903a for input in the input / output setting table 1903. The input / output setting table 1903 holds the input delay setting ID, the capacitance of the on-die capacitor, and the delay amount in association with each other for the input clock signal. The input / output setting table 1903 also holds an input delay setting ID, an on-die capacitor capacity, and a delay amount in association with each other for the input data signal.

  Returning to FIG. 17, the timing adjustment unit 1904 calculates the delay amount to be given to each of the input clock signal and the input data signal from the measurement result of the reflection characteristic, and inputs and outputs the input delay setting ID corresponding to the delay amount. It is specified from the setting table 1903. The timing adjustment unit 1904 notifies the specified input delay setting ID to the clock termination setting unit 2001 and the data termination setting unit 2002.

  The clock termination setting unit 2001 refers to the input / output setting table 1903 and identifies the clock termination setting, that is, the on-die capacity corresponding to the acquired clock input delay setting ID. The clock termination setting unit 2001 applies the specified termination setting to the clock input buffer 2003. Specifically, the clock termination setting unit 2001 sets the on-die capacity of the clock input buffer 2003 to the specified on-die capacity. Thereby, a desired phase is given to the post-processing clock signal CLA.

  The data input buffer 2004 receives the input data signal DTI from the counter integrated circuit 202 via the printed circuit board 201 and the rewiring layer 14. The data input buffer 2004 performs predetermined termination processing set by the data termination setting unit 2002 on the received input data signal DTI and transmits the processed data signal DTA to the internal circuit 106. The phase of the post-processing data signal DTA is adjusted by the termination process.

  The data end setting unit 2002 refers to the input / output setting table 1903 and identifies the data end setting corresponding to the acquired input delay setting ID for data, that is, the on-die capacity. The data end setting unit 2002 applies the specified end setting to the data input buffer 2004. Specifically, the data termination setting unit 2002 sets the on-die capacity of the data input buffer 2004 to the specified on-die capacity. Thereby, a desired phase is given to the processed data signal DTA.

  According to the semiconductor integrated circuit 1905 according to the present embodiment, the same operational effects as the operational effects exhibited by the semiconductor integrated circuit 102 according to the first embodiment are exhibited. In addition, by providing the clock input unit 1901 and the data input unit 1902, phase adjustment can be performed not only on the transmission side but also on the reception side. Therefore, finer phase adjustment than in the first embodiment can be performed.

(Third embodiment)
FIG. 19 is a block diagram showing a basic configuration of a semiconductor integrated circuit 2102 according to the third embodiment. A rewiring layer 14 is provided between the semiconductor integrated circuit 2102 and the external device 107. The semiconductor integrated circuit 2102 includes a reflection measurement unit 2201, a timing adjustment unit 104, an input / output unit 2202, and an internal circuit 106. In the third embodiment, the first path for removing the pulse wave generation unit 402 and the reflection input / output unit 403 from the reflection measurement unit 103 of the first embodiment and communicating with the input / output unit 2202 instead. 2203 and the second path 2204 are provided. The first path 2203 is for a pulse generation command, and the second path 2204 is for reflected wave data.

  The input / output unit 2202 has the functions realized by the pulse wave generation unit 402 and the reflection input / output unit 403 of the first embodiment, the input / output function during normal operation, and the input / output function during reflection detection operation. It is configured to be switchable. By adopting such a configuration, it is possible to perform reflection measurement using the input / output unit for actual operation, and for reflection measurement separately from the input / output unit for actual operation as in the first embodiment. It is no longer necessary to have an input / output section. Thereby, the circuit scale can be reduced.

  The reflection measurement unit 2201 includes a command transmission / reception unit 401 and a voltage detection unit 404. The input / output unit 2202 includes a pulse generation unit 2301, an input / output data selection unit 2302, a data input unit 1902, and a data output unit 1002. The command transmission / reception unit 401 receives the command from the timing adjustment unit 104 and starts reflection measurement. The command transmission / reception unit 401 transmits a pulse issuance command PC to the pulse generation unit 2301 via the first path 2203. Upon receiving the pulse issuing command PC, the pulse generation unit 2301 generates an instructed pulse wave and outputs it to the input / output data selection unit 2302. The pulse generation unit 2301 outputs a pulse issue command PC to the input / output data selection unit 2302.

  The input / output data selection unit 2302 selects and outputs one of the data generated by the internal circuit 106 and the pulse wave generated by the pulse generation unit 2301. The input / output data selection unit 2302 switches the data to be output according to the pulse issue command PC. For example, in response to the pulse issue command PC, the input / output data selection unit 2302 determines to output a pulse wave. The pulse wave output from the input / output data selection unit 2302 enters the data output unit 1002 and is output from the data output unit 1002 to the rewiring layer 14. In this embodiment, the data output unit 1002 is used as the output unit. However, there is no particular limitation as long as the output unit is used, and for example, the clock output unit 1001 may be used.

  Thereafter, the pulse wave output to the rewiring layer 14 returns as a reflected wave at a location where impedance mismatching occurs. The reflected wave is input to the data input unit 1902 and sent from the data input unit 1902 to the input / output data selection unit 2302. In this embodiment, the reflected wave is received by the data input unit 1902. However, there is no particular limitation as long as it is an input unit, and for example, it may be received by the clock input unit 1901.

  The input / output data selection unit 2302 that has received the reflected wave sends the reflected data to the voltage detection unit 404 via the second path 2204. The subsequent processing is the same as the processing in the first and second embodiments.

  The configuration and operation of the semiconductor integrated circuit according to the embodiment have been described above. These embodiments are exemplifications, and it is understood by those skilled in the art that various modifications can be made to each component and combination of processes, and such modifications are within the scope of the present invention. .

  The table values shown in the first to third embodiments are exemplary values set for the purpose of explanation, and are not limited thereto. The table value may vary depending on the application.

  In the first to third embodiments, the semiconductor integrated circuit has a measurement mode for measuring the characteristic of reflection in the rewiring layer 14 and a normal operation mode for inputting / outputting a data signal and a clock signal. May be. As a sequence, as shown in the first embodiment, the measurement mode may be entered after the power-on reset, and the normal operation mode may be entered when the measurement is completed and the delay setting is completed. Alternatively, the semiconductor integrated circuit may enter a measurement mode in response to an external command. Alternatively, the semiconductor integrated circuit may periodically enter the measurement mode.

  In the first to third embodiments, the case where FOWLP is adopted as a package has been described. However, the present invention is not limited to this, and the technical idea according to the embodiment can be equally applied to a package having a redistribution layer. . For example, the technical idea according to the embodiment may be applied to WLCSP (Wafer level Chip Size Package) or FCBGA.

  10 semiconductor chip, 12 FOWLP, 14 rewiring layer, 16 sealing resin, 18 solder ball.

Claims (16)

A semiconductor integrated circuit incorporated in a semiconductor chip connected to an external connection terminal through a rewiring layer,
Measuring means for measuring the reflection characteristics of the signal in the rewiring layer;
An output means for outputting a signal to the rewiring layer;
A semiconductor integrated circuit comprising: adjusting means for adjusting a phase of a signal output by the output means based on a reflection characteristic obtained as a result of measurement. The output means outputs a data signal and a clock signal;
The semiconductor integrated circuit according to claim 1, wherein the adjustment unit adjusts a phase difference between the clock signal and the data signal based on a reflection characteristic obtained as a result of the measurement.   The adjusting means is arranged so that the edge of the data signal output from the output means and passed through the rewiring layer is aligned with the corresponding edge of the clock signal output from the output means and passed through the rewiring layer. 3. The semiconductor integrated circuit according to claim 2, wherein a phase difference between the clock signal and the data signal is adjusted.   The adjustment unit is configured to adjust an edge of the data signal output from the output unit and passed through the rewiring layer and a corresponding edge of the clock signal output from the output unit and passed through the rewiring layer. 4. The semiconductor integrated circuit according to claim 2, wherein adjustment is performed when the magnitude of the deviation amount exceeds a threshold value, and adjustment is not performed otherwise.   5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor chip, the redistribution layer, and the external connection terminal together constitute a fan-out type wafer level package. 6. The measuring means includes
Pulse wave generating means for generating a pulse wave for measurement;
6. The semiconductor integrated circuit according to claim 1, further comprising: a detecting unit that detects a reflected wave from the rewiring layer corresponding to the generated pulse wave.   The semiconductor integrated circuit according to claim 6, wherein the adjustment unit includes a conversion unit that converts a detection result of the detection unit into reflection data including a timing at which reflection occurs and a magnitude of the reflection. The adjusting unit synthesizes the waveform data of the signal after passing through the rewiring layer when the rewiring layer is treated as a transmission path without reflection and the reflection data obtained as a result of conversion by the converting unit. A synthesis means for acquiring the synthesized data by
The semiconductor integrated circuit according to claim 7, further comprising: a determining unit that determines a phase adjustment amount based on the obtained combined data.   9. The semiconductor integrated circuit according to claim 1, wherein the phase of the signal output by the output means is adjusted by changing the driving force of the output buffer.   10. The semiconductor integrated circuit according to claim 1, wherein the phase of the signal output by the output unit is adjusted by changing a capacitor provided in an output stage of the signal. 11.   11. The phase of the signal output by the output means is adjusted by selecting one of the signals output from each of a plurality of delay buffers connected in series. A semiconductor integrated circuit according to 1.   The semiconductor integrated circuit according to claim 1, wherein the adjustment unit adjusts a phase of a signal input from the rewiring layer based on a reflection characteristic obtained as a result of measurement.   13. The semiconductor integrated circuit according to claim 12, wherein the phase of the signal input from the redistribution layer is adjusted by termination setting means for impedance matching provided in the semiconductor integrated circuit. A semiconductor integrated circuit incorporated in a semiconductor chip connected to an external connection terminal through a rewiring layer,
Measuring means for measuring the reflection characteristics of the signal in the rewiring layer;
Input means for receiving a signal input from the rewiring layer;
A semiconductor integrated circuit comprising: adjusting means for adjusting a phase of a signal received by the input means based on a reflection characteristic obtained as a result of measurement. A semiconductor chip;
A rewiring layer provided between the semiconductor chip and the external connection terminal,
The semiconductor chip is
Measuring means for measuring the reflection characteristics of the signal in the rewiring layer;
An output means for outputting a signal to the rewiring layer;
Adjusting means for adjusting a phase of a signal output by the output means based on a reflection characteristic obtained as a result of the measurement. A semiconductor chip;
A rewiring layer provided between the semiconductor chip and the external connection terminal,
The semiconductor chip is
Measuring means for measuring the reflection characteristics of the signal in the rewiring layer;
Input means for receiving a signal input from the rewiring layer;
Adjusting means for adjusting a phase of a signal received by the input means based on a reflection characteristic obtained as a result of the measurement.

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