JP2010198328A - System and control method of synchronous data transfer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous data transfer system for achieving stable synchronous data transfer even under the operation of the system or even under an environment that size reduction and a high speed operation are required. <P>SOLUTION: In the synchronous data transfer system, when data are transferred from a memory 2 through a data bus 31a synchronously with a clock 32 for data transfer, delay time measurement data 23a to 23c stored in a delay time measurement data storage part 23 are transferred to a data bus 31a by using a data output stand-by time until the initial data are extracted from a memory core 22 after a data transfer request is accepted so that the delay time of the data bus 31a can be measured by a delay time measurement part 12 of a control LSI10. A delay adjustment control part 17 adjusts a data fetch timing for fetching the data from a memory core 22 to be transferred through a data bus 31a on the basis of the measured delay time, and supplies it to a memory controller 11. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a synchronous data transfer system and a synchronous data transfer control method.

  In recent years, mobile devices such as mobile phones, PHS (Personal Handy-Phone System), PDA (Personal Digital Assistants), and game consoles have been reduced in size, multifunction, high functionality, and power saving in response to user needs. However, due to the following factors, it has become difficult to ensure reliability in data transfer between components (electronic components) such as an interface between a CPU and a memory.

  In other words, multi-functionalization does not reduce the number of components and reduce the size of components, but on the other hand, miniaturization is forced, so that higher density mounting is required in portable devices. As a result, the rate of temperature rise in the portable device tends to be high, and the temperature fluctuation increases when used outdoors in winter.

  In addition, the signal wiring, power supply, and GND (ground) pattern on the board cannot provide a sufficient margin for current and noise, and the mounting area is small. It is difficult to do so, and consideration for fluctuations in the power supply voltage is insufficient.

  In order to increase the functionality and functionality while addressing such problems, a data transfer interface between components (electronic components) is disclosed in Japanese Patent Application Laid-Open No. 6-282525, “Synchronous Bus Device”, A high-speed and high-efficiency synchronous data transfer system is employed as disclosed in Japanese Patent Application Laid-Open No. 10-340222 “Input circuit and output circuit of memory device”. However, as the data transfer rate becomes higher, the signal delay of data transfer requires higher accuracy and is more susceptible to power supply voltage fluctuations and temperature fluctuations.

  For example, in recent years, synchronous data transfer methods used in SDRAM (Synchronous Dynamic Random Access Memory) and FLASH ROM (Read Only Memory) have increased data transfer speed. The data transfer frequency has reached several hundred MHz.

  For this reason, the timing of each signal in data transfer requires very high accuracy, but the length of each signal line in the data transmission path, the difference in load capacity, the data transmission side, the data reception side semiconductor and other parts A difference in transfer delay time between each signal line in the data transfer path due to manufacturing variation or the like occurs, so that a margin (margin) with respect to timing decreases.

  In order to secure a larger margin with respect to this timing, a data delay adjustment circuit is provided inside a component (electronic component) that performs data transfer, as in Patent Document 2, and data is captured on the data receiving side. A function to guarantee

  However, the difference in the transfer delay time between each signal line in the data transmission path is also affected by fluctuations in the power supply voltage, fluctuations in the ambient temperature, aging, etc. It is impossible to always maintain high-accuracy data capture timing by following these fluctuations only with the method disclosed in Patent Document 2.

  Furthermore, as described above, since measures for power supply voltage fluctuations and temperature fluctuations cannot be sufficiently implemented in order to reduce the size of portable devices, it is difficult to ensure reliability for data transfer.

JP-A-6-282525 (page 2-3) Japanese Patent Laid-Open No. 10-340222 (page 6-8)

  As described above, the conventional synchronous data transfer technology is in a state where measures for miniaturization and high speed are insufficient.

  The present invention has been made in view of such circumstances, and realizes stable synchronous data transfer even when the system is in operation, or even in an environment that requires downsizing and speeding up. It is an object of the present invention to provide a synchronous data transfer system and a synchronous data transfer control method that can be used.

In order to solve the above-mentioned problems, the synchronous data transfer system and the synchronous data transfer control method according to the present invention employ the following characteristic configuration. The numbers (1) and (9) below correspond to the item numbers in the claims.
(1) In a synchronous data transfer system that transfers data via a data transmission path in synchronization with a data transfer clock, using a data output waiting time until the first data is transferred after a data transfer request is made, A synchronous data transfer system comprising delay time measuring means for measuring a delay time of the data transmission path.
(9) A synchronous data transfer control method for controlling an operation of transferring data via a data transmission path in synchronization with a data transfer clock, wherein data output until the first data is transferred after a data transfer request is made A synchronous data transfer control method for measuring a delay time of the data transmission path by using a waiting time.

  According to the synchronous data transfer system and the synchronous data transfer control method of the present invention, the following effects can be obtained.

  Measurement of the delay time of the data transmission path (for example, memory bus) prior to the start of data transfer using the data output waiting period (that is, the latency period) from the data transfer request to the first data transmission It is possible to perform stable data capture by determining the optimal data capture timing based on the measurement results.

  Thus, to adjust the delay of the data transmission path (for example, memory bus) even when the system is in operation, or even in an environment where downsizing and high speed are required, Without increasing the access cycle unnecessarily, it is always stable, following the deterioration of LSI (Large Scale Integration Circuit) characteristics due to external factors such as power supply voltage fluctuations, ambient temperature fluctuations, etc. Data can be taken in at the same timing, and high reliability for data transfer can be obtained.

It is a time chart which shows the general data transfer timing in a synchronous type data transfer system. It is a schematic diagram which shows the connection structure for performing synchronous data transfer between CPU and memory. 3 is a timing chart showing data transfer timing between a CPU and a memory shown in FIG. 2. 3 is a timing chart for explaining an operation in which the CPU shown in FIG. It is a block diagram which shows the specific structural example of the synchronous data transfer system which concerns on this invention. FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of a control LSI illustrated in FIG. 5. 6 is a timing chart for explaining a signal transmission / reception state between a control LSI and a memory in the synchronous data transfer system shown in FIG. 5. 7 is a timing chart for explaining an operation of a delay time measuring unit of a control LSI in the synchronous data transfer system shown in FIGS.

  Preferred embodiments of a synchronous data transfer system and a synchronous data transfer control method according to the present invention will be described below with reference to the accompanying drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention uses a data output waiting period (latency period: latency period) in a synchronous data transfer system, outputs arbitrary delay time measurement data from a data transmission side, and measures the delay time on a data reception side. It is characterized by measuring the delay time of the data transmission path by receiving data, determining the optimum data capture timing based on the measurement result, and constructing a mechanism that enables stable data capture .

  For example, in order to enable high-speed memory access, when performing data transfer with a memory by a synchronous data transfer method, the following mechanism is provided.

  In general, a memory using a synchronous data transfer system such as SDRAM or FLASH ROM has an arbitrary change point of a data transfer clock (in the case of FIG. 1) as shown in the time chart of FIG. Is synchronized with the rising edges t1, t2, t3,...), And performs burst transfer in which data is sequentially transferred via the data bus through the first data, the second data, the third data,. Transfer is possible. FIG. 1 is a time chart showing general data transfer timing in the synchronous data transfer system.

  That is, as shown in FIG. 2, for example, in a system in which the CPU 1 reads data from the memory 2, as shown in the time chart of FIG. 3, the CPU 1 on the data receiving side is connected to the memory 2 on the data transmitting side. On the other hand, at any change point of the data transfer clock 32 (in the example of FIG. 3, the rising edge time t0), the chip select signal 33 and the read signal 34 are set to predetermined logic (in the example of FIG. 3, Change from 'HIGH' level to 'LOW' level) to request data transfer. FIG. 2 is a schematic diagram showing a connection configuration for performing synchronous data transfer between the CPU and the memory. FIG. 3 shows data transfer timing between the CPU 1 and the memory 2 shown in FIG. It is a timing chart.

  When the memory 2 detects a data transfer request due to a change between the chip select signal 33 and the read signal 34, the memory 2 starts preparation for data transmission. After that, when the memory 2 is ready for data transmission, the memory 2 sequentially transfers data for transfer from the memory core 22 (memory cell) to the external interface unit 21. The external interface unit 21 transfers the received data to the data transfer unit. For example, the first data, the second data, the third data,... Are sequentially transmitted at the timing of the rising edges of the data transfer clock 32 at the times t1, t2, t3,. The data is output via the data bus 31a of the memory bus 31 that is a path.

Furthermore, the memory 2 generally requires a preparation time for enabling an access operation to the memory core 22 before the data transfer operation from the memory core 22 (memory cell) to the external interface unit 21 is started. Therefore, when the CPU 1 tries to read data from the memory 2, the CPU 1 waits for a time from when the memory 2 receives the data transfer request from the CPU 1 until the transmission of the first data as the first data is started. Have to do. This data output waiting time is called a latency period (latency period), and is shown as a latency period _TL in FIG.

  Once the access operation to the first first data becomes possible, the data transfer from the memory core 22 (memory cell) to the external interface unit 21 is normally adopted as the memory 2 by the pipeline method. Therefore, after the first data is transmitted at time t1, the data is continuously transmitted from the memory 2 to the CPU 1 in accordance with the second data, the third data,..., And the times t2, t3,. Can be sent.

In the case of such a synchronous data transfer system, generally, the data bus 31a is not used during the latency period _TL. Therefore, in the present invention, the CPU 1 effectively utilizes the latency period _TL. A mechanism for measuring the delay time of the data bus 31a is provided. In other words, the CPU 1 receives the delay time measurement first data, the delay time measurement second data, and the delay time measurement third data transferred from the memory 2 during the latency period _TL , so that the data bus 31a Measure the delay time. Further, based on the measurement result of the delay time, the CPU 1 determines the optimum data capture timing with respect to the data transmitted via the data bus 31a, so that the first data and the subsequent data from the memory 2 are determined. A system for reliably capturing data has been established.

A specific example of the method for determining the data capture timing is shown in FIG. FIG. 4 is a timing chart for explaining the operation of the CPU 1 shown in FIG. As shown in FIG. 3, when the CPU 1 makes a data transmission request to the memory 2 using the chip select signal 33 and the read signal 34, the memory 2 that has received the data transmission request receives data via the memory core 22. The delay time measurement first data and the delay time measurement second are transmitted via the data bus 31a using the latency period _TL until the data is read from the memory core 22 at the same time when the read (read) operation is started. Data and delay time measurement third data are sequentially transmitted to the CPU 1 in synchronization with the data transfer clock 32.

  Here, the first data of the delay time measurement, the second data of the delay time measurement, and the third data of the delay time measurement are all the signal lines of the data bus 31a from “0” to “1” or “1” to “1”. It is assumed that the data has a format that changes to 0 ″. For example, when the data bus 31a is a bus composed of an 8-bit signal line, the delay time measurement first data, the delay time measurement second data, and the delay time measurement third data are “00”. Data such as “h (hexadecimal notation) →“ FF ”h →“ 00 ”h or“ 55 ”h →“ AA ”h →“ 55 ”h” is transmitted in order.

  The CPU 1 measures the delay time of each signal line of the data bus 31a with respect to the data transfer clock 32 by sequentially receiving the delay time measurement first data, the delay time measurement second data, and the delay time measurement third data. The maximum delay time and the minimum delay time are extracted from each delay time. Although there are various means for measuring the delay time, it is not mentioned here because it is not directly related to the present invention.

The optimum data fetch timing when fetching data from the data bus 31a calculated based on the extracted maximum delay time and minimum delay time is as shown in FIG. In FIG. 4, the data bus 31a has an 8-bit width and 8 signal lines D0 to D7. Among the 8 signal lines D0 to D7, the first signal line D1 is the minimum delay time. This shows a case where the signal line is Tmin and the seventh signal line D7 is a signal line with the maximum delay time Tmax. That is, as shown in FIG. 4, the delay time measurement first data, the delay time measurement second data,... Are sequentially transmitted in synchronization with the rising edges t _0A , t _0B,. In this case, the first signal line D1 changes from “0” → “1” or “1” → “0” at the time t _0A1 , t _0B1,. The case where the delay time changes from “0” → “1” or “1” → “0” at the time t _0A7 , t _0B7,.

  Here, the maximum delay time Tmax shown in FIG. 4 is the maximum delay time of the received data, and affects the setup time (Setup Time) Ts of the data capturing unit when the CPU 1 captures data. The minimum delay time Tmin is the minimum delay time of the received data, and the data end time is obtained by subtracting the minimum delay time Tmin from one data transfer time, that is, one cycle time of the data transfer clock 32. This affects the hold time Th of the data fetching unit when the CPU 1 fetches data.

In consideration of the above conditions, as shown in FIG. 4, the time calculated by the following equation (1) can be obtained as a data capture margin Tm when capturing data.
Data capture margin Tm
= Clock cycle time Tc for data transfer
− {(Maximum delay time Tmax + setup time Ts)
+ (Minimum delay time Tmin + Hold time Th)} (1)

Therefore, as shown in FIG. 4, that is, from the rising edges t0A, t0B,... Of the data transfer clock 32 so as to be positioned at the middle of the data capture margin Tm shown in the equation (1), time delayed by the time of the clock delay amount Td given by (2) becomes the optimum data acquisition timing t _g.
Clock delay amount Td from data transfer clock 32
= {(Maximum delay time Tmax + setup time Ts)
+ (Data capture margin Tm × 1/2)}
= {Data transfer clock cycle time Tc
+ (Maximum delay time Tmax + setup time Ts)
− (Minimum delay time Tmin + hold time Th)} × (1/2) (2)

CPU1, the data acquisition so that the timing becomes t _g, by delaying the data transfer clock 32 by clock delay amount Td, Latency period T _L data of the first data and later transferred from the memory 2 after a Can be taken in sequentially and reliably and stably.

(Configuration example of embodiment)
Next, a specific configuration example of the synchronous data transfer system according to the present invention will be further described with reference to FIGS. FIG. 5 is a block diagram showing a specific configuration example of the synchronous data transfer system according to the present invention, in which the control LSI (Large Scale Integration Circuit) 10 incorporating the CPU 1 and the memory 2 are configured. Show. FIG. 6 is a circuit diagram showing an example of the circuit configuration of the control LSI 10 shown in FIG.

  5 and 6, since the memory 2 performs continuous data transfer (burst transfer) to the control LSI 10 between the control LSI 10 and the memory 2, as in the case shown in FIG. A signal line for synchronous data transfer is connected. That is, a data transfer clock 32 which is a reference clock for transferring data, a chip select signal 33 indicating that the memory 2 is selected as an access target, and a read indicating that the access from the control LSI 10 is a read (read). A signal 34, an 8-bit data bus 31a to which data is transferred, and an address bus 31b for outputting an address indicating a data storage destination are connected. As shown in FIGS. 5 and 6, the data bus 31a and the address bus 31b constitute the memory bus 31 shown in FIG.

In the data transfer between the control LSI 10 and the memory 2 shown in FIGS. 5 and 6, the control LSI 10 waits for data output from when the control LSI 10 makes a data transfer request to the memory 2 until the first data is output from the memory 2. Although the time is the latency period _TL , the latency period _TL is assumed to be five clocks of the data transfer clock 32 in FIGS. Further, the time width that the latency period _TL is five clocks of the data transfer clock 32 is commonly recognized on both the memory 2 side and the control LSI 10 side.

  The chip select signal 33, the read signal 34, and the address bus 31b are all output from the control LSI 10 in synchronization with the rising edge of the data transfer clock 32, and the data bus 31a is synchronized with the rising edge of the data transfer clock 32. Then, the data is output from the memory 2 for reading data.

  As in the case shown in FIG. 2, the memory 2 shown in FIG. 5 includes an external interface unit 21 for interfacing with the control LSI 10 and a memory core 22 in which data is stored. .

  Further, in the memory 2, delay time measurement data (delay time measurement first data 23a, delay time measurement second data 23b, delay time measurement third data 23c) for measuring the delay time on the data bus 31a is provided. ) Stored in the delay time measurement data storage unit 23 and the data bus 31a from the output terminal of the memory 2 to the input terminal of the control LSI 10 using the delay time measurement data stored in the delay time measurement data storage unit 23. In order to measure the above delay time, the path for transferring the data of the delay time measurement data control unit 24, the memory core 22 or the delay time measurement data storage unit 23 for performing each control in the memory 2 is switched. A selector 25 is also included at least.

  On the other hand, in the control LSI 10 shown in FIG. 5 and FIG. 6, the CPU 1 and the data transfer clock 32 for reading data from the memory 2, the chip select signal 33, the read signal 34, the data bus 31a, the address A memory controller 11 that controls the bus 31b, a delay time measurement unit 12 that measures the delay time on the data bus 31a, and a maximum delay time determination that determines the maximum delay time based on the measurement result of the delay time measurement unit 12. And a minimum delay time determination unit 14 that determines the minimum delay time based on the measurement result of the delay time measurement unit 12.

  Further, the control LSI 10 includes delay time measurement data (delay time measurement first data 15a, delay time measurement second data 15b, delay time measurement third data 15c) for measuring the delay time on the data bus 31a. ) Stored in the delay time measurement data storage unit 15, the clock delay unit 16 for delaying the data transfer clock 32 at an arbitrary timing in order to generate the timing for capturing data, and the delay time on the data bus 31a Measurement, delay time calculation, delay adjustment control unit 17 for controlling the data fetching timing in the memory controller 11, and setup time (Setup Time) of the data fetching unit necessary for calculating the data fetching timing in the memory controller 11 Ts and hold time (Hold Time) A setup / hold time data storage unit 18 that stores Th parameters is also included.

  The same delay time measurement data is stored in the respective delay time measurement data storage units 15 and 23 of the control LSI 10 and the memory 2, and the delay time measurement first data 15a and 23a are “55” h, the delay. It is assumed that the time measurement second data 15b and 23b are set to “AA” h, and the delay time measurement third data 15c and 23c are set to “55” h.

(Description of operation of embodiment)
Next, an example of the operation of the synchronous data transfer system shown in FIGS. 5 and 6 will be described with reference to the drawings.

  When the CPU 1 in the control LSI 10 reads (reads) continuous data stored at an arbitrary address in the memory 2, the timing chart of FIG. Signals as shown are transmitted and received. FIG. 7 is a timing chart for explaining a signal transmission / reception state between the control LSI 10 and the memory 2 in the synchronous data transfer system shown in FIG.

  First, the CPU 1 notifies the memory controller 11 of the head address and data amount of data to be read from the memory 2 and sends a read request to read the data from the memory 2.

  The memory controller 11 that has received the read request from the CPU 1 changes the chip select signal 33 and the read signal 34 from the “HIGH” level at the timing of the rising edge t1 of the data transfer clock 32 as shown in the timing chart of FIG. At the timing of the rising edge of the data transfer clock 32, the head address storing the first data is output from the address bus 31b and a read request is made to the memory 2 at the “LOW” level. .

  The memory 2 captures the above-described signals from the control LSI 10 at the timing of the rising edge t2 of the data transfer clock 32 in the external interface unit 21, and the external interface unit 21 determines from the control LSI 10 from the state of these captured signals. It is determined that a read request has been transmitted.

When the external interface unit 21 receives a read request from the control LSI 10, the external interface unit 21 starts a read operation. First, the memory interface 22 starts an operation of fetching data at the head address designated by the control LSI 10. Until the first data (first data) is fetched from the memory core 22 to the external interface unit 21, it takes a time corresponding to 5 clocks of the data transfer clock 32 as the latency period _TL .

  Therefore, the external interface unit 21 notifies the delay time measurement data control unit 24 that the read operation from the memory core 22 has started simultaneously with the start of the data fetch operation from the memory core 22.

  Upon receiving the read operation start notification, the delay time measurement data control unit 24 switches the selector 25 in order to transfer the delay time measurement data from the delay time measurement data storage unit 23 to the external interface unit 21. Then, the delay time measurement data control unit 24 converts the delay time measurement data stored in the delay time measurement data storage unit 23 into the delay time measurement first data 23a, the delay time measurement second data 23b, and the delay time measurement third. The data 23c is transferred to the external interface unit 21 in the order.

  The external interface unit 21 receives the delay time measurement data, the delay time measurement first data 23a, the delay time measurement second from the rising edge t3 of the data transfer clock 32 which is the next timing when the read request from the control LSI 10 is recognized. The data 23b and the delay time measurement third data 23c are output from the data bus 31a to the control LSI 10 in synchronization with the rising edges t3, t4, and t5 of the data transfer clock 32, respectively.

  The delay time measurement data control unit 24 can transfer read data from the memory core 22 to the external interface unit 21 after transferring all the delay time measurement data from the delay time measurement data storage unit 23 to the external interface unit 21. Thus, the selector 25 is switched.

  After that, the external interface unit 21 sequentially fetches the data from the memory core 22 that has been requested to read from the first first data, and the next data transfer clock 32 after the output of the delay time measurement third data 23c is completed. Starting from the rising edge t7 of the data transfer, the first data, the second data,... Sequentially from the data bus 31a to the control LSI 10 in synchronization with the rising edges t7, t8,. Output.

  On the other hand, in the control LSI, the delay adjustment control unit 17 captures the chip select signal 33 and the read signal 34 output from the memory controller 11 at the rising edge t2 of the data transfer clock 32, and the memory controller 11 Then, it is detected that a read request has been sent, and a delay time measurement operation in data transfer on the memory bus, that is, the data bus 31a is started.

  The delay adjustment control unit 17 uses the delay time measurement data in the delay time measurement data storage unit 15 from the rising edge t3 next to the rising edge t2 of the data transfer clock 32 that has detected the read request, and the rising edge t3 of the data transfer clock. , T4, and t5, the delay time measurement first data 15a, the delay time measurement second data 15b, and the delay time measurement third data 15c are output to the delay time measurement unit 12 in this order.

  In the delay time measurement unit 12, as shown in the circuit diagram of FIG. 6, the delay time measurement data transmitted from the memory 2 via the data bus 31a and the delay time measurement data storage unit 15 are output. The delay time measurement data is subjected to an EXOR (exclusive OR) operation with a different EXOR circuit for each of the 8-bit bits D0 to D7, thereby comparing whether or not the two data match each other.

  Thereafter, as shown in FIG. 6, the output of each EXOR circuit is input to the NOR circuit 12A and the NAND circuit 12B, and the delay time measurement data from the memory 2 and the delay time measurement data from the delay time measurement data storage unit 15 are input. As a result of the EXOR (exclusive OR) operation, the signal indicating that the data of both of the 8 bits is the same is output, and it is connected to the subsequent stage of each EXOR circuit. The NAND circuit 12B switches from the “LOW” level to the “HIGH” level and outputs it as the minimum delay detection signal 12b. On the other hand, when a signal indicating that the data of both of the 8 bits match is output, the NOR circuit 12A connected to the subsequent stage of each EXOR circuit changes from “LOW” level to “HIGH”. The signal is switched to the “level” and output as the maximum delay detection signal 12a.

  Further, as shown in FIG. 6, a NOR circuit is obtained by sampling clock 1, sampling clock 2,..., Sampling clock 8 output from clock delay unit 16 by sequentially delaying data transfer clock 32 using a delay element. The maximum delay detection signal 12a output from 12A and the minimum delay detection signal 12b output from the NAND circuit 12B are sampled and input to the maximum delay time determination unit 13 and the minimum delay time determination unit 14, respectively. The maximum delay time determination unit 13 and the minimum delay time determination unit 14 determine the maximum delay time Tmax and the minimum delay time Tmin in the data transfer from the memory 2 via the data bus 31a, respectively.

  FIG. 8 is a timing chart for explaining the operation of the delay time measurement unit 12 of the control LSI 10 in the synchronous data transfer system shown in FIGS. 5 and 6. As a result of measurement using the delay time measurement data, data Taking as an example a case where the delay of the second bit D2 of the bus 31a is minimum and the delay of the first bit D1 is maximum, the maximum delay detection signal 12a and the NAND circuit 12B output from the NOR circuit 12A of the delay time measurement unit 12 The respective output waveforms of the minimum delay detection signal 12b output from the sampling delay, and the output waveforms of the sampling clock 1, sampling clock 2,..., Sampling clock 8 output from the clock delay unit 16 are shown.

Maximum delay time Tmax and minimum delay time Tmin obtained by maximum delay time determination unit 13 and minimum delay time determination unit 14 are sent to delay adjustment control unit 17, respectively. Based on the received maximum delay time Tmax and minimum delay time Tmin, the delay adjustment control unit 17 sets the setup time (Setup Time) Ts and hold time of the data capture unit stored in the Setup / Hold Time data storage unit 18. (Hold Time) Clock delay that should be delayed from the data transfer clock 32 in order to obtain the optimum data capture timing t _g using the following formulas (1) and (2) in consideration of data with Th The amount Td is calculated.
Data capture margin Tm
= Clock cycle time Tc for data transfer
− {(Maximum delay time Tmax + setup time Ts)
+ (Minimum delay time Tmin + Hold time Th)} (1)
Clock delay amount Td from data transfer clock 32
= (Maximum delay time Tmax + setup time Ts)
+ (Data capture margin Tm x 1/2)
= {Data transfer clock cycle time Tc
+ (Maximum delay time Tmax + setup time Ts)
− (Minimum delay time Tmin + hold time Th)} × (1/2) (2)

That is, the delay adjustment control unit 17, a timing delayed from the data transfer clock 32 shown in equation (2) by the clock delay amount Td, is acquired as the optimum data acquisition timing t _g.

The delay adjustment control unit 17 switches the selectors in the clock delay unit 16 so that the delay time of the data transfer clock 32 shown in Expression (2) is reached, thereby transferring data by one or more delay elements. the use clock 32 generates data latch timing t _g of the delayed outputs to the memory controller 11.

As shown in FIG. 7, a data transfer period T in which data stored in the memory core 22 is transferred from the memory 2 after a latency period _TL of 5 clocks has elapsed after reception of the read request on the memory 2 side. _{At D} , the memory controller 11 uses the data fetch timing t _g output from the clock delay unit 16 (the rising edge of the clock obtained by delaying the data transfer clock 32 as shown in equation (2)), The first data, the second data, the third data,... On the data bus 31a are taken in at the timings of the rising edges t _g1 , t _g2 , t _g3,. The captured first data, second data, third data,... Are sequentially transferred to the CPU 1.

  When the fetching of the last n-th data designated as the read request to the memory 2 is completed, the memory controller 11 sends the chip select signal 33 and the read signal 34 at the timing of the rising edge of the data transfer clock 32. Then, the "LOW" level is switched to the "HIGH" level, the end of data transfer is notified to the memory 2, and the data read operation is completed.

  In the above-described embodiment, the case of synchronous data transfer between the CPU 1 and the memory 2 has been described. However, the present invention is not limited to such synchronization on the memory bus 31 (data bus 31a, address bus 31b). For example, a data channel bus for transmitting / receiving data to / from an external storage device such as a hard disk device, and any data transmission path that requires synchronous data transfer is exactly the same. Can be applied.

(Description of the effect of this embodiment)
As described in detail above, in the synchronous data transfer system of the present embodiment, the data output waiting period (i.e., the latency period T _L ) from the data transfer request until the first data is transmitted is used. Prior to the start of transfer, the delay time of the data transmission path (for example, memory bus) is measured, and based on the measurement result, the optimum data capture timing is determined, thereby obtaining stable data capture. Can be done.

  Thus, to adjust the delay of the data transmission path (for example, memory bus) even when the system is in operation, or even in an environment where downsizing and high speed are required, Without increasing the access cycle unnecessarily, it is always stable, following the deterioration of LSI (Large Scale Integration Circuit) characteristics due to external factors such as power supply voltage fluctuations, ambient temperature fluctuations, etc. Data can be taken in at the same timing, and high reliability for data transfer can be obtained.

The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such examples are merely illustrative of the invention and do not limit the invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention. For example, the embodiment of the present invention can be expressed as the following configuration in addition to the configurations (1) and (9) in the means for solving the problem. The numbers (2)-(8) and (10)-(15) below correspond to the item numbers in the claims.
(2) The delay time measurement means receives the delay time measurement data transmitted from the data transmission side via the transmission path at a predetermined timing in the data output waiting time, thereby transmitting the transmission. The synchronous data transfer system according to (1), wherein the delay time of the path is measured.
(3) The delay time measurement data is the synchronous data of (2), which is composed of a data format having both changes from “0” to “1” and from “1” to “0”. Transfer system.
(4) Delay adjustment means for adjusting the data acquisition timing for acquiring the data transferred through the transmission line based on the delay time of the transmission line measured by the delay time measurement means. The synchronous data transfer system according to any one of (1) to (3) above.
(5) The delay adjusting means further adjusts the data capturing timing in consideration of a setup time and a hold time of a data capturing unit that captures data transferred via the transmission path. Synchronous data transfer system.
(6) When the transmission path is composed of a plurality of signal lines, the delay time measuring means is based on a delay time measurement result of the delay time measurement data transmitted via each of the plurality of signal lines. The maximum delay time and the minimum delay time are acquired, and the delay adjusting unit is configured to acquire the maximum delay time and the minimum delay time acquired by the delay time measuring unit, and the setup time and the hold time of the data capturing unit. In consideration of the above, the synchronous data transfer system according to (5), wherein the data fetch timing is adjusted.
(7) The delay adjusting means is equivalent to a clock delay amount Td calculated by the following equation:
Clock delay amount Td
= {Tc + (Tmax + Ts)-(Tmin + Th)} × (1/2)
Tc: clock cycle time for data transfer
Tmax: Maximum delay time of the data transmission path
Tmin: Minimum delay time of the data transmission path
Ts: Setup time of data capture unit
Th: The synchronous data transfer system according to (6), wherein the data capture timing is a timing delayed from the data transfer clock by the hold time of the data capture unit.
(8) The synchronous data transfer system includes at least a memory bus system between the memory and the CPU and a data channel bus system between the memory and the external storage device. Synchronous data transfer system.
(10) The delay time of the transmission path is measured by receiving delay time measurement data transmitted from the data transmission side via the transmission path at a predetermined timing in the data output waiting time. The synchronous data transfer control method according to (9) above.
(11) The delay time measurement data is the synchronous data according to (10), which is composed of a data format having both changes from “0” to “1” and from “1” to “0”. Transfer control method.
(12) Based on the measured delay time of the transmission path, the synchronization according to any one of the above (9) to (11) for adjusting the data capture timing for capturing the data transferred through the transmission path Type data transfer control method.
Synchronous data transfer control method.
(13) The synchronous data transfer control method according to (12), wherein the data capture timing is adjusted in consideration of the setup time and hold time of the data capture unit that captures data transferred via the transmission path. .
(14) When the transmission path is composed of a plurality of signal lines, the maximum delay time and the minimum delay time are determined from the delay time measurement results of the delay time measurement data transmitted via the plurality of signal lines. The synchronous data transfer according to (13), wherein the data acquisition timing is adjusted in consideration of the maximum delay time and the minimum delay time, and the setup time and the hold time of the data acquisition unit. Control method.
(15) Only the clock delay amount Td calculated by the following equation:
Clock delay amount Td
= {Tc + (Tmax + Ts)-(Tmin + Th)} × (1/2)
Tc: clock cycle time for data transfer
Tmax: Maximum delay time of the data transmission path
Tmin: Minimum delay time of the data transmission path
Ts: Setup time of data capture unit
Th: The synchronous data transfer control method according to (14), wherein the hold time of the data capturing unit is a timing delayed from the data transfer clock as the data capturing timing.

1 CPU
2 Memory 10 Control LSI
11 Memory Controller 12 Delay Time Measurement Unit 12A NOR Circuit 12B NAND Circuit 12a Maximum Delay Detection Signal 12b Minimum Delay Detection Signal 13 Maximum Delay Time Determination Unit 14 Minimum Delay Time Determination Unit 15 Delay Time Measurement Data Storage Unit 15a Delay Time Measurement First Data 15b Delay time measurement second data 15c Delay time measurement third data 16 Clock delay unit 17 Delay adjustment control unit 18 Setup / Hold Time data storage unit 21 External interface unit 22 Memory core (memory cell)
23 Delay time measurement data storage unit 23a Delay time measurement first data 23b Delay time measurement second data 23c Delay time measurement third data 24 Delay time measurement data control unit 25 Selector 31 Memory bus 31a Data bus 31b Address bus 32 Data transfer clock 33 Chip select signal 34 Read signal

Claims (15)

  In a synchronous data transfer system that transfers data via a data transmission path in synchronization with a data transfer clock, the data transmission is performed using a data output waiting time until the first data is transferred after a data transfer request is made. A synchronous data transfer system comprising delay time measuring means for measuring a delay time of a road.   The delay time measuring means receives delay time measurement data transmitted from the data transmission side via the transmission path at a predetermined timing in the data output waiting time, thereby delaying the transmission path. 2. The synchronous data transfer system according to claim 1, wherein time is measured.   3. The delay time measurement data is composed of a data format having both changes from “0” to “1” and from “1” to “0”. Synchronous data transfer system.   A delay adjusting unit configured to adjust a data capturing timing for capturing data transferred through the transmission line based on the delay time of the transmission line measured by the delay time measuring unit; A synchronous data transfer system according to any one of claims 1 to 3.   5. The delay adjusting unit further adjusts the data capturing timing in consideration of a setup time and a hold time of a data capturing unit that captures data transferred through the transmission path. The synchronous data transfer system described in 1.   When the transmission line is composed of a plurality of signal lines, the delay time measuring means determines the maximum delay time from the measurement result of the delay time of the delay time measurement data transmitted via each of the plurality of signal lines. And the delay adjusting means takes into account the maximum delay time and the minimum delay time acquired by the delay time measuring means, and the setup time and the hold time of the data capturing unit. 6. The synchronous data transfer system according to claim 5, wherein the data capture timing is adjusted. The delay adjusting means is equivalent to a clock delay amount Td calculated by the following equation:
Clock delay amount Td
= {Tc + (Tmax + Ts)-(Tmin + Th)} × (1/2)
Tc: clock cycle time for data transfer
Tmax: Maximum delay time of the data transmission path
Tmin: Minimum delay time of the data transmission path
Ts: Setup time of data capture unit
The synchronous data transfer system according to claim 6, wherein: Th: Hold time of a data capture unit The timing delayed from the data transfer clock is set as the data capture timing.   8. The synchronous data transfer system includes at least a memory bus system between a memory and a CPU and a data channel bus system between a memory and an external storage device. Synchronous data transfer system.   A synchronous data transfer control method for controlling an operation of transferring data through a data transmission path in synchronization with a data transfer clock, wherein a data output waiting time until the first data is transferred after a data transfer request is made A synchronous data transfer control method characterized in that the delay time of the data transmission path is measured.   The delay time of the transmission line is measured by receiving delay time measurement data transmitted from the data transmission side via the transmission line at a predetermined timing in the data output waiting time. The synchronous data transfer control method according to claim 9.   The delay time measurement data is composed of a data format having both changes from "0" to "1" and from "1" to "0". Synchronous data transfer control method. 12. The data fetching timing for fetching data transferred through the transmission path is adjusted based on the measured delay time of the transmission path. Synchronous data transfer control method.
Synchronous data transfer control method.   The synchronous data according to claim 12, further comprising adjusting the data capture timing in consideration of a setup time and a hold time of a data capture unit that captures data transferred via the transmission path. Transfer control method.   When the transmission path is composed of a plurality of signal lines, the maximum delay time and the minimum delay time are obtained from the delay time measurement results of the delay time measurement data transmitted via the plurality of signal lines. The synchronization according to claim 13, wherein the data capture timing is adjusted in consideration of the maximum delay time and the minimum delay time, and the setup time and the hold time of the data capture unit. Type data transfer control method. Only the clock delay amount Td calculated by the following equation:
Clock delay amount Td
= {Tc + (Tmax + Ts)-(Tmin + Th)} × (1/2)
Tc: clock cycle time for data transfer
Tmax: Maximum delay time of the data transmission path
Tmin: Minimum delay time of the data transmission path
Ts: Setup time of data capture unit
The synchronous data transfer control method according to claim 14, wherein Th: a hold time of a data capturing unit is a timing delayed from the data transfer clock as the data capturing timing.

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