KR20070030691A - Semiconductor integraged circuit device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and inputs a data strobe signal to a first input circuit and inputs data formed in synchronization with the signal change timing to a second input circuit. Receiving the data strobe signal input through the first input circuit and determining the arrival delay time for the internal clock in the predetermined determination region by a second delay time determination circuit and sampling the second input by using the data strobe signal; Synchronize data input through the circuit to the internal clock. A first delay time determination circuit for determining a signal delay time by a test clock through a dummy input / output circuit set equal to the signal delay time of the first output circuit and the first and second input circuits; The present invention provides a technique having an interface circuit which realizes the speed of changing the time in time based on the determination result of the first delay time determination circuit.

Description

Semiconductor integrated circuit device {SEMICONDUCTOR INTEGRAGED CIRCUIT DEVICE}

1 is a block diagram showing one embodiment of a semiconductor integrated circuit device in accordance with the present invention.

2 is a waveform diagram for explaining an example of the operation of the memory interface circuit 3 according to the present invention.

3 is a waveform diagram illustrating another example of the operation of the memory interface circuit 3 according to the present invention.

4 is a waveform diagram for explaining another example of the operation of the memory interface circuit 3 according to the present invention.

Fig. 5 is a block diagram showing another embodiment of the semiconductor integrated circuit device in accordance with the present invention.

FIG. 6 is a diagram illustrating correction of one embodiment by the correction circuit of FIG. 5.

7 is a representative explanatory diagram of a delay time determination operation and an update operation of synchronization control information based on the determination result and a memory access operation according to the present invention.

8 is a flowchart of timing adjustment operation control using the delay time determination circuits 41 and 43 shown in FIG.

Fig. 9 is another representative explanatory diagram of a delay time determination operation and an update operation diagram of synchronization control information based on the determination result and a memory access operation according to the present invention.

FIG. 10 is a flowchart of timing adjustment operation control using the delay time determination circuits 41 and 43 shown in FIG.

11 is a block diagram showing a specific example of the sampling circuit 28 used in the present invention.

12 is a block diagram showing a concrete example of the synchronization circuit 45 used in the present invention.

Fig. 13 is an explanatory diagram of data DQ and data strobe signal DQS during write access and read access to the MB-DDR_SDRAM used in the present invention.

14 shows a block diagram of an example of the delay time determination circuit 43 used in the present invention.

Fig. 15 is a block diagram showing another embodiment of the semiconductor integrated circuit device in accordance with the present invention.

16 is a connection diagram of the MCU and the memory examined before the present invention.

17 is an explanatory diagram of a delay time between the MCU and the memory of FIG. 16.

FIG. 18 is a waveform diagram illustrating the memory lead of FIG. 16.

19 is a block diagram of another embodiment of a semiconductor integrated circuit device in accordance with the present invention.

FIG. 20 is a waveform diagram illustrating an operation of the memory interface circuit of FIG. 19.

21 is a waveform diagram illustrating an example of a training operation of the memory interface circuit 3 of FIG. 19.

* Description of key symbols indicating major parts *

One… MCU

2… CPU

3... Memory Interface Circuit

4… External memory controller

5... Clock generation circuit

6... MB-DDR 'SDRAM

16... Output circuit

17, 18, 23... Input and output circuit

27... 90 ° phase shift circuit

28... Sampling circuit

40... Pulse controller

41, 43. Delay time determination circuit

42, 44... Hold circuit

45... Synchronization circuit

50... Output circuit

Q1... MOSFET

R1... resistance

The present invention particularly relates to a semiconductor integrated circuit device such as a microcontroller having a memory interface controller to which a mobile Double Data Rate-Synchronous Dynamic Random Access Memory (DDR-SDRAM) is connected, in particular a synchronization for synchronizing read data to an internal clock. It relates to a valid technology applied to the circuit.

In the present invention, Japanese Patent Application Laid-Open No. 2005-78547 proposes a technique for synchronizing read data with an internal clock on the memory interface controller in a semiconductor integrated circuit such as a data processor having a memory interface controller to which DDR-SDRAM is connected. have. In this synchronization technique, as shown in Fig. 1 of Patent Document 1, the arrival delay of the data strobe signal with respect to the internal clock is determined using the data strobe signal input in the read cycle for the DDR-SDRAM, and the phase of the data strobe signal reached from the memory is determined. The read data is sampled based on the shifted signal and the sampled read data is synchronized with the internal clock based on the determination result of the arrival delay. In addition, as shown in Fig. 11 of Patent Document 1, the pulse controller circuit measures the signal delay in the input / output buffer and uses it to synchronize the signals DQ and DQS.

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-78547

In the DDR-SDRAM, a clock synchronizing circuit such as a DLL (or PLL) is incorporated, and an external clock and an internal clock are synchronized. Nevertheless, so-called DDR-SDRAMs of mobile specifications have been proposed for minimizing power consumption by eliminating clock synchronization circuits such as DLL or PLL for mobile-oriented small electronic devices such as mobile phones. In the present inventors, the memory interface of Patent Document 1 is mounted in a microcontroller (hereinafter referred to simply as MCU) as shown in Fig. 16 and connected to the mobile DDR-SDRAM (hereinafter simply referred to as MB-DDR_SDRAM). Reviewed. In this examination, the following problems were found to occur.

In Fig. 16, the delay time td1 occurs on the clock (/ CK, CK) with respect to the internal clock on the output side of the MCU, and the clock (/ CK, CK) because the clock synchronization circuit is not mounted in the MB-DDR_SDRAM. The delay time td2 occurs from the input of the signal to the signal output of the DQ and DQS, and the delay time td3 occurs in the DQin and DQSin for the signals DQ and DQS on the input side of the MCU. As shown in Fig. 17A, in the MCU, there is a variation in the delay time (td1 + td3) of the worst case and the best case in consideration of process imbalance power supply voltage fluctuations and temperature change. As shown in Fig. 17B, even in the MB-DDR_SDRAM, there is a variation in the delay time td2 of the worst case and the best case in consideration of process unbalanced power supply voltage variation and temperature change. As seen from the internal clock of the MCU, as shown in Fig. 17C, a large variation occurs in the delay time (td1 + td2 + td3) of the best case and the worst case plus A and B.

As shown in Fig. 18A, when the delay times td1 to td3 are small, the point at which the DQSin changes from low level to high level is determined by timing determination points t1 to t5 synchronized with the internal clock ckb. between (t1) and (t2); It can be determined that the point of change from the high level to the low level is between the decision points t3 and T4. However, as shown in Fig. 18B, when the delay times td1 to td3 become large, the signal irregularity period of DQSin is included in the determination region of the timing determination points t1 to t5.

This reason is as follows. In the write mode from the MCU to the MB-DDR_SDRAM, the MCU generates a DQS and supplies the MB-DDR_SDRAM with the write data. In the read mode from the MCU to the MB-DDR_SDRAM, the MB-DDR_SDRAM generates a DQS and supplies the read data to the MCU. Thus, since the DQS signal can be bidirectionally communicated between the MCU and MB-DDR_SDRAM, the DQS signal is in a floating (high impedance (HiZ)) state before the memory access starts.

In the read mode, the DQS is brought to the low level by the MB-DDR_SDRAM as a result of the read mode being transmitted from the MCU to the MB-DDR_SDRAM. Therefore, the DQS floats over a long time in response to the increase in the delay time (td1 to td3). It becomes For this reason, the first determination point t1 becomes the signal irregularity area | region by the said floating state with respect to MCU. For example, if the input circuit puts DQSin at a high level with an indefinite level, the judging circuit makes an incorrect determination that the DQSin has already changed to the high level at the determination point t1. If the determination point t1 is delayed therein, as shown in Fig. 18A, the active point of DQSin cannot be determined when the delay times td1 to td3 are small. As a result, in the technique of Patent Document 1, since the minimum period of the internal clock is determined with respect to the fluctuation range of the delay times td1 to td3, there is a limit to speeding up the clock.

An object of the present invention is to provide a semiconductor integrated circuit device having an interface circuit that realizes high speed. These and other objects and novel features of the invention will be apparent from the description and the accompanying drawings.

Representative but briefly outlined among the inventions disclosed herein are as follows. Supplying an external clock to the external device than the first output circuit, input the data strobe signal formed by the external device corresponding to the external clock to the first input circuit and the data formed in synchronization with the signal change timing of the second input circuit Enter Receiving the data strobe signal input through the first input circuit and determining the arrival delay time for the internal clock in the predetermined determination region by the second delay time determination circuit and using the data strobe signal based on the determination result The data input through the sampled second input circuit is synchronized with the internal clock. The dummy input / output circuit and the dummy input / output circuit which supply test clocks to the dummy input / output circuit and the dummy input / output circuit in which either one of the first output circuit and the first and second input circuits are equally set, respectively, and the dummy. A first delay time determining circuit for receiving a test clock through an input / output circuit and determining a signal delay time is provided, and the determination area of the second delay time determining circuit is temporally determined based on the determination result of the first delay time determining circuit. To change.

Other representative but briefly outlined among the inventions disclosed herein are as follows. The semiconductor integrated circuit device has an interface circuit data processing circuit and a clock generation circuit. The clock generation circuit generates an internal clock and an external clock. The following circuits are provided as the interface circuit. The first output circuit supplies the external clock to the external device through the first external terminal. The second output circuit supplies a control signal formed by the data processing circuit to the external device through a second external terminal. The third output circuit supplies a first data strobe signal corresponding to the external clock to the external device through a third external terminal. The fourth output circuit supplies data synchronized with the signal change timing of the first data strobe signal to the external device through a fourth external terminal. In the first input circuit, a second data strobe signal corresponding to the external clock is input to the external device via the third external terminal. In the second input circuit, data synchronized with the signal change timing of the second data strobe signal is input to the external device via the fourth external terminal. The delay time determination circuit receives a second data strobe signal input through the first input circuit to determine an arrival delay time for the internal clock. The sampling circuit samples the data input through the second input circuit by a timing signal preferably shifting the phase of the second data strobe signal input through the first input circuit by 90 °. The synchronization circuit synchronizes the sampled data to the internal clock based on the determination result of the delay time determination circuit. The third output circuit and the fourth output circuit are tri-state output circuits in which the output control signal performs an output operation at one level and the output control signal is in an output high impedance state at one level. The third output circuit is provided with a circuit for setting the third output external terminal to a high level or a low level fixed level by a predetermined signal in an output high impedance state by the output control signal. The judgment operation by the judgment circuit is performed.

The reason for using the timing signal of shifting the second data strobe signal by "90 degrees" when sampling the data input through the second input circuit is to secure the setup / hold time for the data signal in the sampling circuit and It is possible to secure the most temporal margin regardless of the period of? And to use the signal obtained by shifting the second data strobe signal by 90 ° as a signal for determining the sampling period. For this reason, when the period of the data signal is longer, the setup / hold time can be more secured. Therefore, the shift amount can be changed appropriately without being limited to 90 °.

Figure 1 shows a block diagram of one embodiment of a semiconductor integrated circuit device in accordance with the present invention. The same figure also shows the memory 6 as an external device accessed by it. The semiconductor integrated circuit device 1 of the same figure is not particularly limited but constitutes an MCU (microcontroller) and is formed by, for example, a complementary MOS integrated circuit manufacturing technique on one semiconductor substrate such as single crystal silicon.

The MCU 1 has a CPU (central processing unit) 2 memory interface circuit 3 as a typical data processing circuit, an external memory controller 4 and a clock generation circuit 5. The CPU 2 has an instruction control unit and an operation unit which controls instruction fetch and decodes the fetched instruction. The calculation unit executes the instruction by performing a data operation or an address operation using the decode result of the instruction or the operand specified by the instruction. The memory interface circuit 3 can be directly connected to the memory 6 composed of other chips. The memory 6 becomes, for example, the MB-DDR_SDRAM.

The memory interface circuit 3 is connected to the external memory controller 4. This external memory controller 4 performs interface control for accessing the MB-DDR_SDRAM 6 above. The MB-DDR_SDRAM 6 is not particularly limited but excludes a clock synchronization circuit such as a DLL or a PLL from a known DDR_SDRAM as described above. Although the details are not described, the MB-DDR_SDRAM 6 may include: a row address strobe signal (/ RAS); a column address strobe signal (/ CAS); Various control signals (commands) such as the write enable signal / WE are latched to the active edge of the clock CK as the memory clock. The input / output data DQ is transmitted together with the data strobe signal DQS as a bidirectional strobe signal. The data strobe signal DQS becomes a reference clock of the data input / output operation during the read / write operation.

In the read operation, the MB-DDR_SDRAM 6 outputs the data strobe signal DQS by matching the edge (change point) with the edge of the read data. In the write operation, the external memory controller 4 of the MCU 1 places the edge of the data strobe signal DQS at the center of the write data and outputs it toward the MB-DDR_SDRAM 6. In Fig. 1, the MB-DDR_SDRAM 6 includes input terminals 10 and 11 for clocks CK and / CK; input and output terminals 12 for data DQ; The input / output terminal 13 of the data strobe signal DQS is representatively shown. The clock generation circuit 5, together with the operation reference clock CLK of the CPU 2 and the external memory controller 4, an internal clock such as clocks (cka, ckb) which are clocks used for synchronous control of the MB-DDR_SDRAM. Create For example, clock (b) has twice the frequency of clock (a).

The memory interface circuit 3 includes a data strobe signal DQS and read data DQ output from the MB-DDR_SDRAM 6 together with an input / output circuit for directly connecting the MB-DDR_SDRAM 6 as an external device. Has a synchronization circuit for synchronizing with an internal clock (ckb).

An output circuit (15, 16) of a clock (CK, / CK) typically as the input / output circuit; Input / output circuit 17 of data DQ; The input / output circuit 18 of the data strobe signal DQS is illustrated. In response to the read operation instruction (READ command) to the MB-DDR_SDRAM 6, the output circuits 15 and 16 output clocks CK and / CK from the clock output terminals 19 and 20 to the outside. The input / output circuit 17 is connected to the data terminal 12 of the MB-DDRSDRAM 6 via the external terminal 21. The input / output circuit 18 is connected to the data strobe terminal 13 of the MB-DDR_SDRAM 6 via the external terminal 22. A delay time determining circuit (43) as a circuit for synchronizing the data strobe signal (DQS) and read data (DQ) with an internal clock; Hold circuit 44; Phase shift circuit 27; The sampling circuit 28 and the synchronization circuit 45 are provided.

Since the delay time determination circuit 43 synchronizes the signals DQS and DQ output from the MB-DDR_SDRAM 6 with an internal clock, it measures the arrival time of the data strobe signal DQS itself. The delay time (DQSin system) from the input / output circuit 18 of the DQS terminal 22 to the delay time determination circuit 43 and the phase shift circuit 27 is determined by the input / output circuit 17 of the DQ terminal 21. To the sampling circuit 28 is delayed (the system of DQin) to be substantially the same (clock skew # 0). The delay time determining circuit 43 measures the arrival time of the signal DQSin (delay time (td1 + td2 + td3)) on the basis of the internal clock. For example, both the rising edge and the falling edge of the clock (ckb) of the double cycle, for example, faster than the clock (cka) that defines the operation cycle of the MB-DDR_SDRAM 6, and the DQS at any timing is used. The arrival time (delay time) of the DQSin is measured by determining whether it has changed from the low level to the high level (logic 0 to logic 1) 1. It is preferable that measurement for the determination of the delay time is performed when the read bus cycle is not continuous so that the wrong edge is not recognized when the changing edges of the DQS are continuous.

The delay time of the DQS measured by the delay time determination circuit 43 is set in the hold circuit 26 as the synchronization control information CNTsyc between bus cycles, for example, in the memory refresh cycle period and the memory write cycle. The synchronization control information CNTsyc set in the hold circuit 26 is used for subsequent memory read cycles. The operation instruction of the delay time measurement operation by the delay time determination circuit 43 is given, for example, from the external memory controller 4 as the calibration start instruction signal 30.

The phase shift circuit 27 becomes a variable phase shift circuit using a variable delay circuit. Since the phase shift circuit 27 performs a phase shift of 90 degrees with respect to the cycle of the clock ckb, a delay setting (adjustment delay time) for the variable delay circuit is necessary. The delay time adjustment is performed when no memory lead cycle occurs, for example, during a memory refresh cycle or a memory write cycle. For example, the operation instruction is given in the calibration start instruction signal 30 from the external memory controller 4. The 90 ° phase shifted data strobe signal (DQSin) is represented by DQS-90. The sampling circuit 28 uses the rising edge of the DQS and the rising edge of the pole edge both of which are delayed by 90 ° in the phase shift circuit 27, and samples the read data DQ.

The synchronization circuit 45 has a plurality of paths in which the series stages of the flip flops for latching operations are performed with the normal and reverse phase clocks of the clock ckb, and one path is selected as the synchronization control information CNTsyc. . As a result, the synchronization circuit 45 is measured by the delay time determination circuit 43, updated in sequence among the bus cycles, and is transferred to the sampling circuit 28 by the synchronization control information CNTsyc held by the hold circuit 26. The sampled data (DQ, DQsmp) is synchronized to the internal clock (ckb). The data DQSsyc is internally clocked into the synchronization circuit 45 in accordance with the output of the hold circuit 26 holding the synchronization control information CNTsyc, which has calculated the data DQsap by the delay time determination circuits 27 and 41. It is data synchronized to (clock (ckb)).

In this embodiment, the delay time td1 at the output of the MCU 1 as described above and the delay time td2 in the MB-DDR_SDRAM 6 not having the clock synchronization circuit are determined by the delay time determination circuit ( It is included in the delay time (td1 + td2 + td3) of DQS measured by 43). As a result, the variation in the measured delay time becomes larger as shown in Fig. 17C, and consequently limits the clock period.

In this embodiment, in order to make the variation of the delay time equivalently small, a dummy input / output circuit 23; Pulse control circuit 40; The delay time determination circuit 41 and the hold circuit 42 are provided. The dummy input / output circuit 23 serves as a so-called replica circuit that is equivalent to the input / output circuit 17 or 18 and the input circuit 15 as the input circuit 15. The output terminal of the output circuit of the input / output circuit 23 and the input terminal of the input circuit are connected to the external terminal 24. Although not particularly limited to the external terminal 24 concerned, a capacity in which an input capacity of the MB-DDR_SDRAM 6 is added or a capacity corresponding to a wiring capacity between the MCU 1 and the MB-DDR_SDRAM 6 is added. The equivalent dummy capacitance DC is connected.

Input circuits and output circuits such as the input and output circuits 23 and 15 and 16 are connected to the respective external terminals 24, 19 and 20 via pads PAD (not shown). This PAD is a metal region having a predetermined size formed on a semiconductor substrate, and has a capacity according to the size, and is connected by bonding with a lead frame and a gold wiring, which is partially exposed as an external terminal of the semiconductor integrated circuit device.

The pulse control circuit 40 supplies a test pulse RPout to an input of an output circuit of the input / output circuit 23. The test pulse RPin transmitted through the input circuit of the input / output circuit 23 is input to the delay time determination circuit 41. In this delay time determination circuit 41, the input / output circuit 23 is a replica circuit as described above, and the dummy capacitor CD is connected so that the output circuit of the MCU 1 and the input circuit are connected. Delay time (td1 + td3) is measured. The measurement result td1 + td3 is put in the hold circuit 32 and sent to the delay time determination circuit 43 so that the delay time determination circuit 43 performs the measurement operation of the delay time td2 substantially.

2 shows a waveform diagram for explaining an example of the operation of the memory interface circuit 3 according to the present invention. Referring to FIG. 2, td1 is the terminal of the timing clocks CKBout and CKout from the end of the clock points to the CK terminals 10 and 11 of the MB-DDR_SDRAM 6 via the output circuits 15 and 16. Delay time. The crosspoints of the clocks CK and / CK at the terminals 10 and 11 become reference timings of the data strobe signal DQS and the data DQ. The MB-DDR_SDRAM 6 outputs the delay time td2 with respect to the clocks CK and / CK at the terminals 10 and 11 without embedding the DLL circuit in the output terminal of the data strobe signal DQS. Consists of. The delay time td3 represents the delay time from the DQS terminal 22 to the delay time determination circuit 43 or the phase shift circuit 27 via the input circuit 18. These delay times td1 and td3 are such that the delay times td1 and td3 in the dummy input / output circuit are equal.

2A shows an example of the best / best combination of the MCU 1 and the MB-DDR_SDRAM 6 having the smallest delay times td1, td3, and td2. The variable timing determination points t1 to t5 are set on the basis of the associated knitting. In FIG. A, it is detected that DQSin is changed from low level to high level between decision points t1 and t2. In contrast, in Fig. 2B, the delay times td1 and td3 in the MCU 1 are the best; The delay time td2 in MB-DDR_SDRAM 6 shows an example of Worst / West combination. In this example, the delay times td1 and td3 in the MCU 1 are the best states, and the variable timing determination points t1 to t5 in the delay time determination circuit 43 are kept as they are. Therefore, the delay time determining circuit 43 corresponds to the delay time td2 in the MB-DDR_SDRAM 6 and changes the DQSin from low level to high level between the decision points t3 and t4. Detect.

3 shows a waveform diagram for explaining another example of the operation of the memory interface circuit 3 according to the present invention. 3A shows an example of the best / best combination of the MCU 1 and the MB-DDR_SDRAM 6 having the smallest delay times td1, td3, and td2, similarly to FIG. 2A. On the other hand, in FIG. 3B, the delay time td1 and td3 in the MCU 1 are shown as examples, and the delay time td2 in the MB-DDR_SDRAM 6 is the best combination of worst / best. . In this example, the delay time determination circuit 41 determines the delay times of the delay times td1 and td3 in the MCU 1, and the delay time determination circuit 43 corresponds to the determination result. The variable timing determination points t1 to t5 are changed (shifted) so as to slow down the period of 1.5 cycles (3 points) of the internal clock ckb. As a result of this, if the determination point t1 remains, the malfunction of throwing the negative level of the DQSin is avoided, and the DQSin goes from the low level to the high level between the determination points t1 and t2 as in Fig. 3A. Detect changes. That is, in the example of FIG. 3B, the determination result in the delay time determination circuit 43 is determined in the determination time (for 1.5 cycles) in the delay time determination circuit 41 while preventing the above-described determination malfunction of DQSin. It is reflected and performs a synchronization operation.

4 shows a waveform diagram for explaining another example of the operation of the memory interface circuit 3 according to the present invention. In Fig. 4A, as in Fig. 2A, an example of the best / best combination of the MCU 1 and the MB-DDR_SDRAM 6 having the smallest delay times td1, td3 and td2 is shown. On the other hand, in Fig. 4B, an example is shown in which the delay times td1 and td3 in the MCU 1 and the delay time td2 in the MB-DDR_SDRAM 6 are worse than the best in Fig. 4A. In this example, the delay time determination circuit 41 determines the delay times of the delay times td1 and td3 in the MCU 1, and the delay time determination circuit 43 corresponds to the determination result. The variable timing determination points t1 to t5 are changed (shifted) so as to delay 1.0 cycle (two points) of the internal clock ckb. As a result, a malfunction that the negative level of DQSin is taken into account is avoided if the decision point t1 remains, and the DQSin is low level between the decision points t3 and t4 in response to the increase in the delay time td2. The change to high level is detected from. That is, in the example of Fig. 4B, the determination result (1. 0 cycles) in the delay time determination circuit 41 is determined by the determination result in the delay time determination circuit 43 while preventing the determination malfunction of the DQSin as described above. It is reflected and performs a synchronization operation.

5 shows a block diagram of another embodiment of a semiconductor integrated circuit device in accordance with the present invention. In this embodiment, the external terminal 24 is not provided in the dummy input / output circuit 23. As a result, the delay time td1 '+ td3' of the test pulse RPin does not include the signal delay at the dummy capacitor CD corresponding to the input capacitance of the external terminal and the external device. There, a correction circuit 46 is provided. The correction circuit 46 performs an operation of correcting the signal delay. For example, as shown in FIG. 6, the correction time is added to the measurement time of the delay time determination circuit 41 by using the correction table or calculated to similarly form the delay time td1 + td3, and the hold circuit 46 is formed. Let's see. The other configuration is the same as the embodiment of FIG. In this configuration, the external terminal and the dummy capacitor can be omitted.

Fig. 7 shows an operation for updating the synchronization control information based on the delay time determination operation and the determination result and a representative explanatory diagram for the memory access operation. The MB-DDR_SDRAM 6 requires memory refresh at regular intervals in the same manner as a normal dynamic RAM, and performs normal memory access for the rest of the period. In the read access period in this memory access period, the delay time determination circuit 43 performs the delay time determination (DQS arrival timing determination) of the strobe signal DQS, and the holding value of the hold circuit 44 according to the determination result. The internal delay measurement using the update (control information update) or the delay time determination circuit 41 may be performed in a memory refresh period in which no memory access occurs or in a write access period in which no read cycle occurs.

However, it can be considered that the memory read access does not occur even once in the memory refresh interval. In that case, the synchronization control information CNTsyc held by the hold circuit 44 cannot be updated. To avoid using too old synchronization control information (CNTsyc) held by the hold circuit 44, a dummy read access cycle is automatically performed just before starting the memory refresh cycle when no memory read access occurs in the memory refresh interval. Generates. As a result, the synchronization control information CNTsyc can be avoided. When the MCU is powered on, memory refresh is performed to perform internal delay measurements, dummy reads, and clear internal states.

The internal delay or DQS determination timing determination and control information update are performed before.

FIG. 8 shows a flowchart of timing adjustment operation control using the delay time determination circuits 41 and 43 shown in FIG. By the delay time determination circuit 41 using the test pulse following a power on reset; 1) internal delay measurement; 2) Set the window for the DQS timing judgment at the time of memory read. 3) A dummy read cycle is generated and the determination operation by the delay time determination circuit 43 is performed. 4) Memory refresh is performed immediately after that. 5) Clear the memory read access flag, and 6) set the internal delay measurement 7) set the window for the DQS timing determination at the time of memory read.

8) After the memory access period starts, 9) A memory refresh request is determined. If there is no refresh request, 10) Memory read access request is determined. If there is no memory read request, the process returns to step 9). 11) If there is a memory read request, perform a memory read. At this time, memory response speed measurement is performed. 12) The memory read flag is set and the process returns to step 9).

If there is a memory refresh request, 17) the memory access period end is set. 18) The memory flag determination is made, and it is determined whether there is a memory read even once in the immediately preceding memory access period. If there is no memory lead, 19) Dummy read occurs and memory response speed measurement is performed. 13) Memory refresh (synchronization mechanism timing setting) is performed when the memory lead exists and when the dummy read ends. 14) The memory read flag is cleared in this synchronization mechanism timing setting. 15) Make an internal delay measurement. 16) DQS timing determination window is set during memory read. After the memory refresh, the process shifts to the step 8) Memory access period start.

In this configuration, the delay time and its own are used by using the data strobe signal DQS output from the MB-DDR_SDRAM 6 without performing phase alignment between the clock CK supplied to the MB-DDR_SDRAM 6 and the internal clock. The delay time in the input / output operation is measured, and the timing correction of the data inserted from the MB-DDR_SDRAM 6 is performed based on the information obtained therefrom.

Since the measurement of the delay time of the data strobe signal DQS is performed at any time between the bus cycles, and reflecting the information to the actual timing adjustment mechanism is performed during a period such as a memory refresh cycle, When the information of the delay time of the data strobe signal itself is used to adjust the timing of the data, the timing of delay measurement and the reflection of the measurement result can be suppressed. If a data read cycle which becomes the original information for timing measurement does not occur even once between memory refresh cycles, a check is performed at the start of the memory refresh cycle and a dummy read cycle is inserted.

In this way, the misjudgment avoidance caused by the indeterminate level of the DQS for measuring the timing DQS itself of the data strobe signal to be synchronized internally by the variable timing determination window (variable timing determination point) considering the delay time in its input / output operation. A highly reliable piece of information can be used to synchronize to the internal clock. In addition, since the DQS signal is determined using the variable timing determination window, the operation timing of the MB-DDR_SDRAM 6 can be known without worrying about problems such as reflection. Since the data strobe signal (DQS) that MB-DDR_SDRAM (6) outputs is measured by using the signal (DQS) itself to be adjusted for timing, unnecessary errors do not enter and there is no problem such as a crisis path. This makes it possible to maximize the operating margin, making it easier to stabilize the operation. In addition, timing measurement becomes more accurate by using the delay time in its input / output operation, which eliminates the need for unnecessary design margins for external devices that do not have clock synchronization circuits, such as general-purpose DDRRAMSDRAM, resulting in a faster DDR interface. It becomes possible.

Fig. 9 shows an operation for updating the synchronization control information based on the delay time determination operation and the determination result, and another representative explanatory diagram for the memory access operation. This embodiment is a modified example of the embodiment of Fig. 7, and does not perform internal delay measurement (DQS timing setting window timing determination by delay time measurement) every memory refresh. In other words, the internal delay measurement (DQS timing setting window timing determination by delay time measurement) is performed at a ratio of a plurality of memory refreshes. Therefore, the dummy read in the case where there is no read at the time of memory access is performed under the condition that the internal delay measurement is performed in the memory refresh immediately after that.

10 shows a flowchart of timing adjustment operation control using the delay time determination circuits 41 and 43 used in the present invention. Steps 1) to 19) are the same as those in Fig. 8 above, and 6) 7 ms) internal delay measurement count counter clear is added after the internal delay measurement, and 15) 16 ms) internal delay measurement count counter clear is added after the internal delay measurement. do. Then, after 18) and 19), it is determined whether the number of internal delay measurement times exceeds the prescribed value, and if it exceeds the specified value, the process proceeds to 13) memory refresh. If the specified value is not exceeded, 21) memory refresh (synchronization mechanism timing setting) is performed, and as this synchronization mechanism timing setting, 22) memory read flag clear internal delay measurement count counter +1 24) DQS timing determination window setting at memory read is performed. Step 8) The process proceeds to the memory access period start.

11 shows a specific example of the sampling circuit 28 used in the present invention. The data DQ is, for example, 64 bits. The input is DQin [63: 0], latched to the other flip-flop circuits (FFr, FFf) at the rising edge DQS-r90 and the pole edge DQS-f90 of the 90 ° phase shifted signal (DQS-90) for each bit. It is supposed to sample. DQS-f90 is the pole edge sync pulse of the 90 ° phase shifted signal (DQS-90), and DQS-r90 is the rise edge sync pulse of the 90 ° phase shifted signal (DQS-90). The output of the sampling circuit 28 is output as data (DQ) smp-r [63: 0] synchronized at the rise edge and as data (DQ) smp-f [63: 0] synchronized at the pole edge.

12 shows a specific example of the synchronization circuit 45 used in the present invention. The synchronizing circuit 45 stores the data DQsm-r [63: 0] and DQsmp-f [63: 0] output from the sampling circuit 28 in accordance with the synchronization control information CNTsyc in an internal clock at a variable delay (FIFO). ckb). FFt1 is a flip flop for performing a latch operation to the rising edge of the normal clock of ckb; FFt2 is a flip-flop which performs a latch operation to the rising edge of the normal clock of ckb; FFb3 is a flip-flop that performs a latch operation at the rising edge of the ckb reverse phase clock. SEL1, SEL2, and SEL3 are selectors. The selectors SEL2 and SEL3 select the paths PAS1, PAS2, and PAS3 as the synchronization control information CNTsyc from the hold circuit 44. The selector SEL1 alternately selects input in synchronization with the rise / fall change control.

For example, the high and low levels of cka change the input selection. In the case where the data DQ reaches the internal clock fastest in view of the delay time determined by the delay time determining circuit 41 and the delay time determining circuit 43, the output from the selectors SEL2 and SEL3 is selected by selecting the path PAS1. Is delayed by one cycle of ckb to synchronize to the internal ckb. If it is a little late, select pass PAS2 and delay 1/2 cycle of ckb. If it is later, select pass PAS3 and avoid unnecessary delays. The outputs of the selectors SEL2 and SEL3 are latched in synchronization with ckb in FFt1, whereby DQsyc is supplied to the rear end as data synchronized in ckb.

FIG. 13 shows the relationship between the data DQ and the data strobe signal DQS during write access and read access to the MB-DDR_SDRAM. In write access, the phase of the data strobe signal DQS is delayed by 90 degrees with respect to the data DQ. The MB-DDR_SDRAM 6 receiving this samples the data DQ in synchronization with the edge of the data strobe signal DQS. During read access, the MB-DDR_SDRAM 6 outputs data DQ and data strobe signal DQS simultaneously. The interface circuit 3 receives them as described above and performs sampling of the data DQ with the data strobe signal DQS-90 whose phase is delayed by 90 °.

An example of the delay time determination circuit 43 is shown in FIG. The delay time determination circuit 43 is constituted by a logic circuit 33 that determines the delay time from its output to the serial circuit 32 of the flip flop and outputs two bits of synchronization control information CNTsyc. The series circuit 32 of the flip flops has a four-stage series circuit of flip flops FFa, FFb, FFc, and FFd and a four-stage series circuit of flip flops FFe, FFf, FFg, and FFh. The flip flops FFa and FFb perform a latch operation on the rising edge of the ckb reverse phase clock (ckb reverse phase), and the flip flops FFc to FFh perform the latch operation on the rise edge of the normal clock ckb of ckb.

The logic circuit 33 inputs the output of (FFc, FFd, FFf, FFg, FFh) and determines at what timing the data (DQSin) in hand has changed to 1 for ckb and synchronizes the result with 2 bits. The control information CNTsyc is output to the hold circuit 26. The delay time determination circuit 41 also determines in what timing the data rpin held in this way has changed to 1 with respect to ckb. The number of stages of the flip-flop circuit is selected in relation to the period of the clock ckb, the delay time td1 + td3, and td2.

Fig. 15 shows a block diagram of another embodiment of a semiconductor integrated circuit device in accordance with the present invention. In this embodiment, the dummy input / output circuit 23 is connected to the pads PAD (24 kPa) on the semiconductor substrate. Since the pad 24 'has a parasitic capacitance Cp of the pad itself, the capacitor Cp is synchronously connected to the pad 24' in the same figure. This capacitance Cp may include a capacitance formed on a semiconductor substrate. It is also conceivable that the parasitic capacitance of the pad 24 'and the capacitance formed on the semiconductor substrate can be formed only in small capacity as compared with the capacitance DC connected to the outside. In such a case, the delay time td1 + td3 may be formed by correction by the correction values described in the embodiment of FIG. 5 with respect to the delay time td1 '+ td3'.

19 is a block diagram of another embodiment of a semiconductor integrated circuit device in accordance with the present invention. In this embodiment, the dummy input / output circuit 23 shown in Figs. 1, 5 and 15 is omitted. Corresponding to this, the pulse control 40, the delay time determination circuit 41, the correction circuit 46 and the hold circuit 42 are also omitted. Instead, a pull-up circuit is added to the input / output circuit 18 of the data strobe signal DQS. In other words, the resistor R1 and the P-channel MOSFET Q1 are provided in series between the external terminal 22 and the power supply voltage. The pull-up control signal DQSpu formed by the external memory controller 4 is supplied to the gate of the MOSFET Q1. 1, 5 and 15, an output circuit 50 for outputting an address ADD, a command COM, and the like, and an external terminal 51 thereof are also shown.

20 is a waveform diagram for explaining an example of the operation of the memory interface circuit 3 of FIG. Immediately after powering up, a training session is established. The external memory controller 4 sets the pull-up control signal DQSpu low when entering this training period. As a result, the MOSFET Q1 is turned on to pull up the external terminal 22 to a high level. In other words, the signal DSQ is fixed at the high level by the pull-up from the negative level at the high impedance HiZ. Dummy leads are conducted during this training period. When the training period ends and enters the normal period, the pull-up control signal DQSpu returns to the high level. As a result, in the normal period, the external terminal 22 becomes a negative level at high impedance HiZ when the MCU does not perform an output operation or when the MB-DDR_SDRAM does not perform an output operation. When writing from the MCU to the MB-DDR_SDRAM in this normal period, the output circuit of the input / output circuit 18 is put into an operating state and the data strobe signal DQS for the write operation is output. On the contrary, when the read operation from the MB-DDR_SDRAM to the MCU is performed, the data strobe signal DQS from the MB-DDR_SDRAM is input to the input circuit of the input / output circuit 18.

The training period may be performed immediately after the power is turned on, or in a dummy lead inserted before the memory refresh as shown in FIGS. 7 and 9, or when the MCU ends a low power consumption mode such as a sleep mode or a standby mode. It is installed before starting the signal processing operation and performing memory access. Alternatively, the training period may be provided when the operating conditions (power supply voltage or temperature) in the MCU or MB-DDR_SDRAM are greatly changed or when a memory error occurs frequently. In this way, the training period may be set as necessary in consideration of the memory access operation.

21 shows a waveform diagram for explaining an example of the training operation of the memory interface circuit 3 of FIG. 19, td1 denotes the CK terminals 10 and 11 of the MB-DDR_SDRAM 6 via the output circuits 15 and 16 from the ends of the clock points of the clocked clocks CKBout and CKout as described above. Delay time to) is shown. The crosspoints of the clocks CK and / CK at the terminals 10 and 11 become reference timings of the data strobe signal DQS and the data DQ. The MB-DDR_SDRAM 6 outputs the delay time td2 with respect to the clocks CK and / CK at the terminals 10 and 11 without embedding the DLL circuit in the output terminal of the data strobe signal DQS. Consists of. The delay time td3 represents the delay time from the DQS terminal 22 to the delay time determination circuit 43 or the phase shift circuit 27 via the input circuit 18.

21A shows an example of the best / best combination of the MCU with the smallest delay times td1, td3 and td2 and MB-DDR_SDRAM. In Fig. 21B, an example of the combination of the worst time / best of the delay time td1 and td3 in the MCU and the delay time td2 in the MB-DDR_SDRAM is shown. In this embodiment, as described above, since the signal DQS is pulled up at the training period and is at a high level, there is no period of the negative level of the signal DQS as described above. Therefore, it is not necessary to make the decision point variable so as to avoid a negation level. Thus, the number of decision points is not limited as seen previously.

In the example of FIG. A, it is detected that DQSin is changed from low level to high level between decision points t2 and t3. On the other hand, in Fig. 21B, it is possible to detect that the delay times td1 and td3 in the MCU are delayed by the time of Worst, so that DQSin changes from low level to high level between decision points t6 and t7. Also, if the delay times td1, td3, and td2 are the Worsts / Wast combinations of the largest MCU and the MB-DDR_SDRAM, the determination point is delayed by the worst of the delay time td2, for example. It's only late, like t7 and t8 or t8 and t9. And even if the above (td1) and (td3) are as late as Worst minutes, the pull-up operation is recognized as the high level (H) at the determination point (t1) (t2), and is negated as in the determination point (t1) in FIG. Judging the level can be avoided.

In this embodiment, the terminal 22 of the MCU is added with a pull-up circuit capable of simply selectively turning on / off a bidirectional data strobe signal in the high impedance period of the terminal 13 of the MB-DDR_SDRAM. And a pull-up function for only the training period, and the like, using a simple clock synchronization high level / low level decision circuit having the fixed decision point, etc., to find a change point from the low level to the high level, It is possible to determine the arrival timing.

In addition to the large memory of timing fluctuations such as mobile DDR SDRAM as described above, high / low levels are correctly set even when a DDR1-SDRAM or DDR2-SDRAM memory is connected in which the clock frequency is high and the variation of the delay value of the controller's own input / output device is relatively large. High-impedance period of data strobe signal by adding pull-up function that can be selectively turned on / off to data strobe signal that cannot be determined and turning on only the training period such as initialization It is possible to completely avoid misrecognition by

As described above, the embodiment of Fig. 19 responds to a large variation in the delay time td2 when a DLL or the like is not embedded in the memory, but in addition, the delay time td2 is relatively small and relatively stable by embedding the DLL. Even if the variation of the delay time (td1 + td3) on the MCU side is relatively large due to the high frequency of the clock (ckb) or the like, the problem caused by the addition of the simple pull-up circuit and the setting of the training period can be solved. have.

As described above, a mobile DDR SDRAM that does not have a DLL can reduce a relatively large current consumption in a DLL circuit. This makes it very suitable for a battery driven memory such as a cellular phone device. When a plurality of memory chips are mounted in one package and a memory having a standby capacity is configured, heat generation due to current consumption becomes a big problem. Attention is drawn to the fact that the consumption current of the mobile DDR SDRAM having no DLL as mentioned above is small, and it is advantageous to assemble a plurality of memory chips in one package to form an image memory or the like. In this case, a problem arises in the high-speed access due to the above-described variation in delay time, but the problem associated with using the interface circuit according to the present invention as the interface circuit of the memory controller can be solved.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the said embodiment, this invention is not limited to the said embodiment, A various change is possible about the range which does not deviate from the summary. For example, the specific structure of the pulse control 40 (; delay time determination circuits 41 and 43; the synchronization circuit 45, the sampling circuit 28, and the 90 degree phase shift circuit 27) which generate a test pulse is various. For example, the synchronization circuit 45 is based on the timing of PRout in FIGS. 2 to 4 and the DQSin is determined from the determination result of the 43 by the delay time determination circuit 41. As long as it finds the active point of ckb immediately after changing from the low level to the high level, DQsmp can be taken out. It is okay to use it as it is.

Instead of the pull-up circuit shown in Fig. 19, a pull-down circuit may be used. At this time, the resistor R1 may be composed of a polysilicon resistor, a diffusion resistor, or a MOSFET. It is also possible to use the on-resistance value as the resistor R1 to make the MOSFET Q1 smaller in size and to have both functions of resistance and switch.

In addition to the CPU and external memory controller shown in Figs. The external device may be anything as long as it returns data (DQ) to the MCU in synchronization with both the clock sent from the MCU and the corresponding edges of the DQS formed in correspondence with the MB-DDR_SDRAM.

By the temporal change of the determination area corresponding to the delay time in the input / output circuit, the fluctuation range of the signal delay is reduced to the equivalent, and the speed can be increased. The indefinite level in the output high impedance state becomes a fixed level at the time of the delay determination, and input data can be synchronized without being influenced by the variation of the delay time in the input / output circuit.

Claims (27)

An interface circuit, a data processing circuit and a clock generation circuit, The clock generation circuit generates an internal clock and an external clock, The interface circuit, A first output circuit for supplying the external clock to an external device; A first input circuit for inputting a data strobe signal formed corresponding to the external clock to the external device; A second input circuit for inputting data formed in synchronization with the signal change timing of the data strobe signal to the external device; A dummy input / output circuit in which signal delay times with either of the first output circuit and the first and second input circuits are equally set, respectively; A pulse control circuit for supplying a test clock to the dummy input / output circuit; A first delay time determining circuit that receives a test clock through the dummy input / output circuit and determines a signal delay time; A second delay time determination circuit for receiving a data strobe signal input through the first input circuit and determining an arrival delay time for the internal clock in a predetermined determination region; A sampling circuit for sampling data input through the second input circuit by a timing signal shifted by 90 ° of a phase of the data strobe signal input through the first input circuit; A synchronization circuit for synchronizing the sampled data to the internal clock based on a determination result of the second delay time determination circuit, And the determination region of the second delay time determination circuit changes in time based on a determination result of the first delay time determination circuit. The method according to claim 1, The interface circuit, A second output circuit having an output terminal connected to the input terminal of the first input circuit, and a third output circuit having an output terminal connected to the input terminal of the second input circuit, The second output circuit supplies a data strobe signal to the external device, And the third output circuit supplies data to the external device in synchronization with a signal change timing of a data strobe output through the second output circuit. The method according to claim 2, And an output terminal of an output circuit constituting the dummy input / output circuit and an input terminal of the input circuit are connected to an external terminal. The method according to claim 2, A correction circuit which receives an output signal of said first delay time determination circuit, The determination output of the first delay time determining circuit can be matched to a signal delay time of either the first output circuit or the first and second input circuits by the correction circuit. . The method according to claim 3, And said external device is a mobile DDR SDRAM having no clock synchronization circuit. The method according to claim 5, And a memory controller which is provided corresponding to the interface circuit and performs access control of the mobile DDR_SDRAM. The method according to claim 6, And the memory controller generates a dummy read cycle for performing a determination operation of the second delay time determination circuit when there is no read cycle at a predetermined refresh interval of the mobile DDR_SDRAM. The method according to claim 7, And the memory controller generates a dummy read cycle for performing a determination operation of the second delay time determination circuit in response to a power-on reset. The method according to claim 8, And the determination operation of the first delay time determination circuit is performed in the refresh cycle of the mobile DDR_SDRAM. The method according to claim 9, And the determination operation of the first delay time determination circuit is performed every plural refresh cycles. An interface circuit data processing circuit and a clock generation circuit, The clock generation circuit generates an internal clock and an external clock, The interface circuit, A first output circuit for supplying the external clock to an external device; A first input circuit for inputting a data strobe signal formed corresponding to the external clock to the external device; A second input circuit for inputting data formed in synchronization with the signal change timing of the data strobe signal to the external device; A third input / output circuit connected to the first capacitor, A pulse control circuit capable of outputting a pulse signal to the third input / output circuit; A first delay time determination circuit for receiving a pulse signal through the third input / output circuit and determining a signal delay time; A second delay time determination circuit for receiving a data strobe signal input through the first input circuit and determining an arrival delay time for the internal clock in a predetermined determination region; A sampling circuit for sampling data input through the second input circuit by a timing signal shifted by 90 ° of a phase of the data strobe signal input through the first input circuit; A synchronization circuit for synchronizing the sampled data to the internal clock based on a determination result of the second delay time determination circuit, And the determination region of the second delay time determination circuit changes in time based on a determination result of the first delay time determination circuit. The method according to claim 11, The interface circuit, A second output circuit having an output terminal connected to the input terminal of the first input circuit, and a third output circuit having an output terminal connected to the input terminal of the second input circuit, The second output circuit supplies a data strobe signal to the external device, And the third output circuit supplies data to the external device in synchronization with the signal change timing of the data strobe output through the second output circuit. The method according to claim 12, The third input / output circuit has an output circuit and an input circuit, And an output terminal of the output circuit is connected in parallel to the first capacitor portion and an input terminal of the input circuit. The method according to claim 13, And said first capacitor is a PAD terminal formed on a semiconductor substrate to which an output terminal of said output circuit is connected. The method according to claim 12, A correction circuit which receives an output signal of said first delay time determination circuit, The determination output of the first delay time determining circuit can be matched to the signal delay time of either the first output circuit or the first and second input circuits by the correction circuit. . The method according to claim 13, And said external device is a mobile DDR SDRAM having no clock synchronization circuit. The method according to claim 16, And a memory controller provided corresponding to the interface circuit to perform access control of the mobile DDR_SDRAM. The method according to claim 17, And the memory controller generates a dummy read cycle for performing a determination operation of the second delay time determination circuit when there is no read cycle at a predetermined refresh interval of the mobile DDR_SDRAM. The method according to claim 18, And the memory controller generates a dummy read cycle for performing a determination operation of the second delay time determination circuit in response to a power-on reset. The method according to claim 19, And the determination operation of the first delay time determination circuit is performed in the refresh cycle of the mobile DDR_SDRAM. The method of claim 20, And the determination operation of the first delay time determination circuit is performed every plural refresh cycles. An interface circuit, a data processing circuit and a clock generation circuit, The clock generation circuit generates an internal clock and an external clock, The interface circuit, A first output circuit for supplying the external clock to an external device through a first external terminal; A second output circuit for supplying a control signal formed by the data processing circuit to the external device through a second external terminal; A third output circuit configured to supply a first data strobe signal corresponding to the external clock to the external device through a third external terminal; A fourth output circuit for supplying data synchronized with a signal change timing of the first data strobe signal to the external device through a fourth external terminal; A first input circuit to which the second data strobe signal corresponding to the external clock is input to the external device via the third external terminal; A second input circuit into which the data synchronized with the signal change timing of the second data strobe signal is input to the external device via the fourth external terminal; A delay time determination circuit for receiving a second data strobe signal input through the first input circuit and determining an arrival delay time for the internal clock; A sampling circuit for sampling data input through the second input circuit by a timing signal shifted by 90 ° of a phase of the second data strobe signal input through the first input circuit; A synchronization circuit for synchronizing the sampled data with the internal clock based on a determination result of the delay time determination circuit, The third output circuit and the fourth output circuit comprise a tri-state output circuit in which the output control signal performs an output operation at one level and the output control signal is in an output high impedance state at the other level; , The third output circuit is provided with a circuit for setting the third output external terminal to a high level or a low level fixed level by a predetermined signal in an output high impedance state by the output control signal. A semiconductor integrated circuit device characterized by performing a determination operation by a determination circuit. The method according to claim 22, And the external device is a DDR? SDRAM having no clock synchronization circuit. The method according to claim 23, And a memory controller which is provided in correspondence with the interface circuit and performs access control of the DDR_SDRAM not having the clock synchronization circuit. The method of claim 24, And the memory controller executes a dummy read cycle for generating the predetermined signal in response to a power-on reset to perform a determination operation of a delay time determination circuit. The method according to claim 25, And the memory controller generates the predetermined signal to perform the determination operation of the delay time determination circuit when instructing the refresh cycle of the DDR_SDRAM not having the clock synchronization circuit. The method of claim 26, And the determination operation of the delay time determination circuit is performed every plural refresh cycles.

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