JP2011253501A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for accurately calculating a phase difference between a clock signal and a control signal in a memory which operates synchronously with the clock signal.SOLUTION: A Slave DLL13 delays and outputs a control signal within a prescribed range. On the basis of a sampling result from a sampling circuit in a DDR3 DIMM2 obtained while making the Slave DLL13 change the delay amount of the control signal, a DQS output phase adjustment circuit 12 extracts the undefined range of the sampling result generated when the setup time or hold time of the sampling circuit is not satisfied, and calculates a phase difference between a clock signal and the control signal on the basis of the extracted undefined range, and adjusts the delay amount of the control signal. Therefore, it is possible to accurately calculate the phase difference between the clock signal and the control signal.

Description

  The present invention relates to a technique for controlling a memory that reads and writes data in synchronization with a clock signal, and more particularly to a semiconductor device that controls a memory by adjusting the phase of a control signal and a clock signal.

  In recent years, the functions and functions of computers and portable terminals have been increasing, and accordingly, high-speed access to memory has been required. One method for speeding up SDRAM (Synchronous Dynamic Random Access Memory) is DDR (Double Data Rate). In the DDR SDRAM, the SDRAM has a bank configuration, so that the operating frequency of the internal bus can be lowered compared to the operating frequency of the external bus, and the SDRAM can be operated at a speed with less burden.

  Such a DDR SDRAM has been further increased in speed, and a DDR3 SDRAM (hereinafter also referred to as DDR3 DIMM (Dual Inline Memory Module)) having an 8-bank configuration of SDRAM has been developed.

  In the DDR3 SDRAM, in order to improve the waveform quality of the signal in each memory module, a fly-by topology (Fly-by Topology) in which signal lines common to each memory module are connected in a single line is adopted. . By adopting this method, it is possible to shorten the wiring in the DIMM. However, on the other hand, there is a difference in the time that the clock propagates to each memory module in the DIMM, and the clock signal and the data strobe (DQS) ) A phase difference occurs between the signal and the signal.

  Therefore, it is necessary for the memory controller that controls each memory module in the DIMM to delay the input timing of the DQS signal in accordance with the propagation delay of the clock signal. As technologies related to this, there are inventions disclosed in the following Patent Documents 1 to 3.

  Patent Document 1 aims to provide a memory interface circuit that does not erroneously latch data signals even when transmission conditions are deteriorated or mismatched. The memory interface circuit includes an oscillation circuit, a delay circuit, a phase comparator, and a data latch, and can connect a DDR-SDRAM that outputs a DQS signal and a data signal in synchronization with a clock. The delay circuit delays the clock output from the oscillation circuit and outputs it as a read clock. The phase comparator measures the phase difference between the input data strobe signal and the read clock, the delay circuit adjusts the read clock delay time according to the measured phase difference, and the data latch synchronizes the read clock with the data signal. take in.

  In Patent Document 2, when a read operation is controlled for a plurality of memories in which clock signal lines are wired in a daisy chain, input times of data signals output from the plurality of memories are easily aligned. For the purpose. The memory control circuit has a write leveling function and controls a read / write operation by supplying a clock signal via a clock signal line to a plurality of memories having clock signal lines wired in a daisy chain. . A first variable delay unit that delays the data strobe signal DQS output to the memory by a first delay time set by using the write leveling function during a write operation and a read operation corresponding to a plurality of memories, respectively. The second variable delay unit delays the data signal DQ input from the memory by a second delay time set based on the first delay time.

  Patent Document 3 aims to capture data correctly. In a memory control device including three DIMMs, an SPD (Serial Presence Detect) on which DIMMs are mounted is accessed to acquire the number of DIMMs and the like. The delay time of the synchronous clock CLK of the DIMM is set according to the number of acquired DIMMs and the like, and data is taken in synchronization with this clock.

JP 2008-071018 A JP 2009-077562A JP 2002-278825 A

  As described above, it is necessary on the memory controller side to delay the input timing of the DQS signal in accordance with the propagation delay of the clock signal. The DDR3 SDRAM has a function for assisting so-called write leveling in which the memory controller corrects the phase of the clock signal and the DQS signal.

  Each memory module of the DDR3 SDRAM has a function of sampling a clock signal at the rising edge of the DQS signal and outputting the sampling result to a data (DQ) signal. On the memory controller side, the sampling result from each memory module is acquired while shifting the phase of the DQS signal, and the phase difference when the sampling result changes from “0” to “1” is set as the delay amount of the DQS signal.

  However, in the sampling circuit for write leveling provided in the DDR3 SDRAM, the setup (tWLS) time and the hold (tWLH) time are specified. In the case of DDR3-800, the value is about 325 ps. Is stipulated. Therefore, it is conceivable that the sampling circuit operates without satisfying tWLS and tWLH, and there is a problem that the phase difference between the clock signal and the DQS signal cannot be measured with high accuracy.

  In addition, when the clock signal or the DQS signal includes noise or jitter, the adjustment accuracy is further deteriorated due to the influence.

  In addition, when read leveling is not performed, it is necessary to read data using the phase difference measured by write leveling, which further deteriorates accuracy and makes it impossible to read data correctly. There was also a point.

  The present invention has been made to solve the above problems, and an object of the present invention is to accurately calculate a phase difference between a clock signal and a control signal in a memory operating in synchronization with the clock signal. A semiconductor device is provided.

  According to an embodiment of the present invention, there is provided a semiconductor device that operates in synchronization with a clock signal and controls a memory having a sampling circuit that samples the clock signal at the rising edge of the control signal. The SlaveDLL outputs the control signal with a delay within a predetermined range. Based on the sampling result from the sampling circuit obtained by changing the delay amount of the control signal in Slave DLL, the DQS output phase adjustment circuit is indefinite of the sampling result caused by not satisfying the setup time or hold time of the sampling circuit. Extract range. Then, the phase difference between the clock signal and the control signal is obtained based on the extracted indefinite range, and the delay amount of the control signal is adjusted.

  According to one embodiment of the present invention, the DQS output phase adjustment circuit extracts an indefinite range of the sampling result caused by not satisfying the setup time or hold time of the sampling circuit, and the phase difference between the clock signal and the control signal is extracted. Therefore, the phase difference between the clock signal and the control signal can be accurately calculated.

1 is a block diagram illustrating a configuration example of a system including a semiconductor device according to a first embodiment of the present invention. 4 is a flowchart for explaining a processing procedure of a DQS output phase adjustment circuit 12; FIG. 3 is a block diagram showing a functional configuration of a part that performs screening processing in a DQS output phase adjustment circuit 12; FIG. 4 is a flowchart (No. 1) for explaining the processing procedure of the screening processing unit shown in FIG. 3. It is a flowchart (the 2) for demonstrating the process sequence of the screening process part shown in FIG. It is a figure which shows the place where scanning data are updated by the process shown in FIG. 4 and FIG. It is a figure which shows the relationship between a screening process result and the delay amount of a DQS signal. It is a block diagram which shows the structural example of the system containing the semiconductor device in the 3rd Embodiment of this invention.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a system including a semiconductor device according to the first embodiment of the present invention. This system includes a semiconductor device (hereinafter referred to as a control circuit) 1 and a DDR3 DIMM2.

  The DDR3 DIMM 2 includes eight Ram modules 0 to 7 (21-0 to 21-7). Each of the Ram modules 0 to 7 (21-0 to 21-7) has a sampling circuit. In the write leveling mode, each of the sampling circuits samples the clock signal at the rising edge of the data strobe (DQS) signal. The sampling result is output as a data (DQ) signal.

  The control circuit 1 generates eight DQS signals corresponding to each of the Ram modules 0 to 7 (21-0 to 21-7) in the DDR3 DIMM 2, and from the Ram module corresponding to each of the DQS signals. A phase difference from the clock signal is obtained based on the obtained sampling result, and the delay amount of each DQS signal is determined.

  The control circuit 1 includes a master DLL (Delay Locked Loop) 11, a DQS output phase adjustment circuit 12, a slave DLL 13, a READ FIFO 14, a DQ output circuit 15, a DQS output circuit 16, a CLK output circuit 17, and an input / output buffer. 18 and 19.

  The MasterDLL 11 is a circuit for correcting an error generated between the external clock and the internal clock due to a change in the environment (power supply voltage, temperature, etc.) or an internal cause. When a phase difference is detected, The delay code is output to the DQS output phase adjustment circuit 12.

  The DQS output phase adjustment circuit 12 determines the level of the CLK signal and each DQS signal according to the DQ signal (sampling result) output from the Ram modules 0 to 7 (21-0 to 21-7) in the DDR3 DIMM2. The phase difference is obtained, and the delay amount of the DQS signal is calculated as a delay code output from the MasterDLL 11. The details of the DQS output phase adjustment circuit 12 will be described later.

  The Slave DLL 13 is a circuit capable of shifting the reference clock by 180 ° or more (half clock or more), and delays the reference clock according to the delay amount output from the DQS output phase adjustment circuit 12.

  The READ FIFO 14 holds the data (DQ) read from the DDR3 DIMM 2 and outputs it to the outside according to the clock signal output from the Slave DLL 13 and the DQS signal output from the DDR3 DIMM 2.

  The DQ output circuit 15 outputs data (DQ) to the DDR3 DIMM 2 according to the clock signal output from the Slave DLL 13.

  The DQS output circuit 16 generates and outputs a DQS signal to be given to each of the Ram modules 0 to 7 (21-0 to 21-7) in the DDR3 DIMM 2 in accordance with the clock signal output from the Slave DLL 13.

  The input / output buffer 18 outputs the data (DQ) received from the DQ output circuit 15 to the DDR3 DIMM 2 and outputs the data (DQ) received from the DDR3 DIMM 2 to the DQS output phase adjustment circuit 12 and the READ FIFO 14.

  The input / output buffer 19 outputs the DQS signal received from the DQS output circuit 16 to the DDR3 DIMM 2 and outputs the DQS signal received from the DDR3 DIMM 2 to the READ FIFO 14.

  FIG. 2 is a flowchart for explaining the processing procedure of the DQS output phase adjustment circuit 12. First, the DQS output phase adjustment circuit 12 sequentially shifts the phase of the reference clock from 0 ° to 180 ° in the Slave DLL 13 to each of the Ram modules 0 to 7 (21-0 to 21-7) in the DDR3 DIMM2. The phase of the given DQS signal is sequentially shifted from 0 ° to 180 °. Then, by obtaining the data (DQ) output from the DDR3 DIMM 2 at that time, the 180 ° section is measured (S1).

  For example, if 65 pieces of sampling data are obtained in a 180 ° section, the 180 ° section is measured while the DQS signal is shifted by 180 ° / 65. It should be noted that the measurement is performed a plurality of times with the DQS signal of the same phase. When all are “0”, the scan data is “0”, and when all are “1”, the scan data is “1”. "" And "1" are mixed, the scan data is "both".

  Next, the DQS output phase adjustment circuit 12 screens the measurement result and becomes indefinite by not satisfying the setup time or hold time of the sampling circuit in the Ram modules 0 to 7 (21-0 to 21-7). The range is specified (S2). Details of this screening process will be described later.

  Finally, the DQS output phase adjustment circuit 12 obtains the delay amount of the DQS signal from the result obtained by the screening process, performs an operation on the delay code output from the Master DLL 11, and obtains the phase amount by the Slave DLL 13 (S3).

  FIG. 3 is a block diagram showing a functional configuration of a portion that performs screening processing in the DQS output phase adjustment circuit 12. This screening processing unit may be realized by hardware, or may be realized by a CPU (Central Processing Unit) executing a program.

  The screening processing unit includes a scan data storage unit 31, a scan data acquisition unit 32, a change interval calculation unit 33, a minimum change interval extraction unit 34, a boundary number count unit 35, a boundary number determination unit 36, and scan data. And an update unit 37.

  The scan data storage unit 31 stores the scan data measured in step S1 of the flowchart shown in FIG. As described above, when sampling is performed 65 times in the 180 ° section, data indicating any one of “0”, “1”, and “both” corresponds to each of the Ram modules. 65 are stored in 31.

  The scan data acquisition unit 32 sequentially acquires scan data having a phase amount of 0 ° to 180 ° in the scan data stored in the scan data storage unit 31 to obtain a change interval calculation unit 33, a boundary number counting unit 35, and The data is output to the scan data update unit 37.

  The change interval calculation unit 33 calculates an interval when the scan data sequentially acquired by the scan data acquisition unit 32 changes, and outputs the change interval to the minimum change interval extraction unit 34 and the scan data update unit 37.

  The minimum change interval extraction unit 34 extracts the minimum change interval from the change intervals calculated by the change interval calculation unit 33 and outputs the minimum change interval to the scan data update unit 37.

  The boundary number counting unit 35 counts the number of boundaries when the scan data sequentially acquired by the scan data acquisition unit 32 changes, and outputs the boundary number to the boundary number determination unit 36.

  The boundary number determination unit 36 determines whether or not to continue the screening process according to the number of boundaries received from the boundary number counting unit 35. When the screening process ends, the scanning data acquisition unit 32 is notified of this.

  The scan data update unit 37 updates the scan data acquired by the scan data acquisition unit 32 based on the change interval output from the change interval calculation unit 33 and the minimum change interval output from the minimum change interval extraction unit 34. The data is written back to the scan data storage unit 31.

  4 and 5 are flowcharts for explaining the processing procedure of the screening processing unit shown in FIG. Here, the variables described in the flowchart will be briefly described. min_interval [6: 0] is 7-bit information indicating the minimum change interval when the scan data changes.

  border [2: 0] is 3-bit information indicating the number of boundaries when the scan data changes. dat [64: 0] [1: 0] is 2-bit information indicating the contents of 65 pieces of scan data. “01” is stored when the scan data is “0”, “10” is stored when the scan data is “1”, and “11” is stored when the scan data is “both”.

  pre_state [1: 0] is 2-bit information indicating the value of the previous scan data. pre_state_num [7: 0] is 8-bit information indicating a value corresponding to the frequency (phase amount) of the previous scan data, and a value of 0 to 64 is set. The actual frequency is obtained by multiplying the value by 180 ° / 65.

  The interval [6: 0] is 7-bit information indicating the change interval of the scan data currently being investigated. counter [7: 0] and counter2 [7: 0] are 8-bit counters serving as pointers for sequentially acquiring scan data.

  The flowchart shown in FIG. 4 mainly performs extraction of the minimum change interval and determination of the number of boundaries. First, “7′h3F” is set in min_interval [6: 0], “3′h0” is set in border [2: 0], and “8′h00” is set in counter [7: 0]. Initialization is performed (S11). In addition, the description of a setting value is based on HDL (Hardware Description Language) description.

  Next, the scanning data acquisition unit 32 determines whether or not the value of the counter is “0” (S12). If the value of counter is “0” (S12, Yes), the scanning data acquisition unit 32 acquires the scanning data dat [0] [1: 0] from the scanning data storage unit 31 and pre_state [1: 0]. And the counter value “0” is substituted for pre_state_num [7: 0] (S13), and the process proceeds to step S14. If the value of counter is not “0” (S12, No), the process proceeds to step S14.

  In step S14, the change interval calculation unit 33 determines whether or not the current scan data dat [counter] is the same as the previous scan data pre_state. If they are the same (S14, Yes), the process proceeds to step S20.

  If not the same (S14, No), the change interval calculation unit 33 subtracts the value of pre_state_num from the value of counter and substitutes it for interval. Further, the boundary number counting unit 35 increments the value of the boundary number border (S15). If the value of border [2: 0] is “3′h7”, processing is performed so as not to overflow without further incrementing.

  Next, an AND operation is performed on each bit of the previous scan data to determine whether it is “1′b0” (S16). If the calculation result is not “0”, that is, if the previous scan data is “both” (S16, No), the process proceeds to step S19.

  If the calculation result is “0”, that is, if the previous scan data is “0” or “1” (Yes in S16), the minimum change interval extraction unit 34 determines whether min_interval is greater than interval. Is determined (S17). If min_interval is equal to or less than interval (S17, No), the process proceeds to step S19.

  If min_interval is larger than interval (S17, Yes), the minimum change interval extraction unit 34 updates the minimum change interval by substituting the interval value for min_interval (S18), and the process proceeds to step S19.

  In step S19, the scanning data acquisition unit 32 substitutes the counter value for the frequency pre_state_num at the previous scanning, and substitutes the scanning data dat [counter] value for the previous scanning data pre_state (S20). Then, the scanning data acquisition unit 32 increments the value of counter (S21).

  Next, the scanning data acquisition unit 32 determines whether the value of counter is larger than “64” (S22). If the value of counter is “64” or less (S22, No), the process returns to step S12 and the subsequent processing is repeated.

  If the counter value is greater than “64” (S22, Yes), the boundary number determination unit 36 determines whether the border value is greater than “2” (S23). If the value of border is larger than “2” (S23, Yes), the process proceeds to step S24 in FIG. If the value of border is “2” or less (S23, No), the boundary number determination unit 36 notifies the scanning data acquisition unit 32 of the end of processing, and the processing ends.

  The flowchart shown in FIG. 5 mainly replaces scan data whose change interval matches the minimum change interval with “both”. In step S24, "8'h00" is set in counter [7: 0] and initialization is performed (S24).

  Next, the scanning data acquisition unit 32 determines whether or not the value of the counter is “0” (S25). If the value of counter is “0” (S25, Yes), the scanning data acquisition unit 32 acquires the scanning data dat [0] [1: 0] from the scanning data storage unit 31 and pre_state [1: 0]. The counter value “0” is substituted into pre_state_num [7: 0] (S26), and the process proceeds to step S27. If the value of counter is not “0” (S25, No), the process proceeds to step S27.

  In step S27, the change interval calculation unit 33 determines whether or not the current scan data dat [counter] is the same as the previous scan data pre_state. If they are the same (S27, Yes), the process proceeds to step S36.

  If not the same (S27, No), the change interval calculation unit 33 updates the change interval by subtracting the value of pre_state_num from the value of counter and substituting it into interval (S28).

  Next, the minimum change interval extraction unit 34 determines whether min_interval is the same as the interval (S29). If min_interval is not the same as interval (S29, No), the process proceeds to step S35.

  If min_interval is the same as interval (S35, Yes), an AND operation is performed on each bit of the previous scan data to determine whether or not “1′b0” (S30). If the calculation result is not “0”, that is, if the previous scan data is “both” (S30, No), the process proceeds to step S35.

  If the calculation result is “0”, that is, if the previous scan data is “0” or “1” (S30, Yes), the scan data update unit 37 sets the previous count to counter2 [7: 0]. The value of the frequency pre_state_num at the time of scanning is substituted (S31).

  Next, the scan data update unit 37 updates the scan data by substituting “2′b11” (both) into the scan data dat [counter2], and writes it back to the scan data storage unit 31 (S32). Then, the value of counter2 is incremented (S33), and it is determined whether or not the value of counter2 is equal to or greater than the value of counter (S34). If the value of counter2 is less than the value of counter (S34, No), the process returns to step S32 and the subsequent processing is repeated.

  If the value of counter2 is equal to or greater than the value of counter (S34, Yes), the scanning data acquisition unit 32 substitutes the value of counter for the frequency pre_state_num at the previous scanning (S35), and scan data dat [counter] Is substituted into the previous scan data pre_state (S36). Then, the scanning data acquisition unit 32 increments the value of counter (S37).

  Next, the scanning data acquisition unit 32 determines whether the value of counter is larger than “64” (S38). If the value of counter is “64” or less (S38, No), the process returns to step S25 and the subsequent processing is repeated. If the value of counter is larger than “64” (S38, Yes), the process returns to step S11 in FIG. 4 and the subsequent processing is repeated.

  In this way, scanning data whose change interval and minimum change interval coincide with each other until the number of boundaries becomes 2 or less is replaced with “both”, and sampling in the Ram modules 0 to 7 (21-0 to 21-7) is performed. The range in which the measurement result is indefinite by not satisfying the setup time or hold time of the circuit is specified. Here, the measurement result being indefinite means that the measurement result changes at a short interval or that the measurement result has a different value even though the measurement result is measured at the same phase.

  FIG. 6 is a diagram showing the location where the scan data is updated by the processing shown in FIGS. 4 and 5. The column “scan data” on the left side of FIG. 6 describes the first scan data stored in the scan data storage unit 31. In FIG. 6, only the scan data near the rising edge of the clock signal is shown, but there are actually 65 pieces of data.

  The column “first time” in FIG. 6 describes a state after the scan data is updated in the first time of the processing shown in FIGS. 4 and 5. The value where the scan data change interval coincides with the minimum change interval “1” is replaced with “both”.

  The column “second time” in FIG. 6 describes a state after the scan data is updated in the second time of the processing shown in FIGS. 4 and 5. The value where the scan data change interval matches the minimum change interval “2” is replaced with “both”.

  The column “third time” in FIG. 6 describes a state after the scan data is updated in the third time of the processes shown in FIGS. 4 and 5. The value where the scan data change interval coincides with the minimum change interval “3” is replaced with “both”. In this third state, the scan data has changed from “0” to “both” and from “both” to “1”, and since the number of boundaries is “2”, the processing is completed. The range in which the third “both” is described is a range in which the measurement result is indefinite because the setup time or hold time of the sampling circuit is not satisfied.

  FIG. 7 is a diagram showing the relationship between the screening processing result and the delay amount of the DQS signal. For example, patterns (12) to (14) show a case where the rising edge of the clock signal is delayed by about 180 °, and when the phase amount of the DQS signal is 0 °, the DQS signal rises at T1. It is shown that. Among the Ram modules 0 to 7 (21-0 to 21-7), it is considered that the Ram module 7 (21-7) arranged at the end is close to such a state.

  Pattern (12) shows a case where only one boundary that changes from “0” to “1” is detected by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so as to coincide with the point where the rising edge of the DQS signal changes from “0” to “1”.

  Pattern (13) shows a case where only one boundary that changes from “0” to “both” is detected by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal is at the midpoint of “both”.

  Pattern (14) shows a case where all the scan data is “0” and no boundary is detected. In this pattern, the phase amount (delay amount) of the DQS signal is determined to be 180 °.

  Patterns (4) to (6) show a case where the rising edge of the clock signal is slightly delayed, and shows that the DQS signal rises at T2 when the phase amount of the DQS signal is 0 °. ing.

  Pattern (4) shows a case where two boundaries are detected by changing from “both” to “1” and further from “1” to “0” by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal is 0 ° which is the midpoint of “both”.

  Pattern (5) shows a case where two boundaries are detected by changing from “both” to “1” and further from “1” to “both” by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal is 0 ° which is the midpoint of the first “both”.

  Pattern (6) shows a case where only one boundary that changes from “both” to “1” is detected by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal is 0 ° which is the midpoint of “both”.

  Patterns (2) to (3) show a case where the rising edge of the DQS signal is delayed from the rising edge of the clock signal. When the phase amount of the DQS signal is 0 °, the DQS signal is displayed at T3. It shows that it has stood up.

  Pattern (2) shows a case where only one boundary that changes from “1” to “both” is detected by the screening process. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal becomes a value obtained by subtracting 180 ° from the midpoint of “both”.

  Pattern (3) shows a case where all the scan data is “1” and no boundary is detected. In this pattern, the phase amount (delay amount) of the DQS signal is determined to be 0 °.

  In FIG. 7, the width of the scan data is described so as to be different for each pattern, but this is because only the pattern change of the scan data is mainly shown, and the width of the scan data is not necessarily the scan data. It does not correspond to the number of.

  In the above description, the delay amount of the DQS signal is determined so as to coincide with the midpoint of “both” where the measurement result is indefinite. This is because it is assumed that the setup time and hold time of the sampling circuit are the same. When the setup time and the hold time are different, the phase amount may be determined within the range of “both” according to the ratio instead of the midpoint of “both”.

  As described above, according to the semiconductor device in the present embodiment, the DQS output phase adjustment circuit 12 determines the setup time or hold time of the sampling circuit in the Ram modules 0 to 7 (21-0 to 21-7). The range of “both”, which is indefinite due to not being satisfied, is specified, and the delay amount is determined so that the rising edge of the DQS signal becomes the midpoint of the range of “both”. Therefore, the delay amount of the DQS signal can be calculated with high accuracy.

  In addition, since the phase can be controlled by accurately calculating the delay amount of the DQS signal, the accuracy of the timing of the DQS signal at the time of data reading can be maintained to a certain degree even when the read leveling is not performed, and the data Can be read.

  Furthermore, since the phase of the clock signal is controlled by the MasterDLL11 and SlaveDLL13, it becomes possible to absorb delay changes caused by environmental changes.

(Second Embodiment)
In the first embodiment, when the phase difference between the clock signal and the DQS signal is 180 ° or more, the same pattern as the pattern near the phase difference of 0 ° appears. For example, the patterns (20) to (31) in FIG. 7 are those when the phase difference exceeds 180 °, and the same pattern as the patterns (1) to (19) appears, so the delay amount of the DQS signal Cannot be calculated correctly.

  In the second embodiment of the present invention, the delay amount of the DQS signal is correctly calculated by reading the SPD (Serial Presence Detect) information held by the DDR3 DIMM 2 and determining the DIMM type. The configuration of the control circuit, the screening process, and the screening processing unit in the second embodiment of the present invention are the same as those shown in FIGS. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  When calculating the delay amount of the DQS signal from the pattern after the screening process, the DQS output phase adjusting circuit 12 reads the SPD information from the DDR3 DIMM 2 and acquires the number of Ram modules arranged. Thus, since the delay amount of the clock signal can be grasped to some extent, when the phase difference is expected to exceed 180 °, 180 ° is added to the delay amount of the DQS signal.

  For example, although patterns (20) to (31) in FIG. 7 show a case where the angle exceeds 180 °, 180 ° is further added when calculating the delay amount of the DQS signal. For example, the pattern (24) changes from “1” to “both” by the screening process to indicate that only one boundary is detected. In this pattern, the phase amount (delay amount) of the DQS signal is determined so that the rising edge of the DQS signal is obtained by adding 180 ° to the midpoint of “both”.

  As described above, according to the semiconductor device of the present embodiment, when the delay amount of the clock signal is assumed to exceed 180 ° by referring to the SPD information, 180 ° is further added. The delay amount of the DQS signal is set. Therefore, in addition to the effects described in the first embodiment, the delay amount of the DQS signal can be calculated with higher accuracy.

(Third embodiment)
The semiconductor devices according to the first and second embodiments are intended for DDR3-DIM equivalent to DDR3-800, and when the frequency of the reference clock becomes higher, the description will be given in the first and second embodiments. With this method, the delay amount of the DQS signal cannot be accurately calculated.

  In the semiconductor device according to the third embodiment of the present invention, the reference clock is switched to the write leveling measurement clock only at the time of write leveling. Note that the procedure of the screening process and the configuration of the screening processing unit in the third embodiment of the present invention are the same as those shown in FIGS. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 8 is a block diagram showing a configuration example of a system including a semiconductor device according to the third embodiment of the present invention. Compared with the control circuit 1 in the first embodiment shown in FIG. 1, the only difference is that a multiplexer (MUX) 20 is added. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  During normal operation, the MUX 20 selects and outputs a reference clock. At the time of write leveling, the MUX 20 selects and outputs a write leveling measurement clock. For example, when the reference clock is 800 MHz, a 400 MHz clock is used as the write leveling measurement clock. Thereby, the delay amount of the DQS signal can be calculated by the same operation as that described in the first and second embodiments.

  As described above, according to the semiconductor device in the present embodiment, since the MUX 20 switches between the reference clock and the write leveling measurement clock, the effects described in the first and second embodiments can be obtained. In addition, it has become possible to deal with DDR3-1600, which can operate at higher speed than DDR3-800.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Control circuit, 2 DDR3 DIMM, 11 MasterDLL, 12 DQS output phase adjustment circuit, 13 SlaveDLL, 14 READ FIFO, 15 DQ output circuit, 16 DQS output circuit, 17 CLK output circuit, 18, 19 I / O buffer, 20 MUX, 21-0 to 21-7 Ram module, 31 scan data storage unit, 32 scan data acquisition unit, 33 change interval calculation unit, 34 minimum change interval extraction unit, 35 boundary number count unit, 36 boundary number determination unit, 37 scan data Update department.

Claims (5)

A semiconductor device that operates in synchronization with a clock signal and controls a memory having a sampling circuit that samples the clock signal at the rising edge of a control signal,
Delay means for delaying and outputting the control signal within a predetermined range;
Based on the sampling result from the sampling circuit obtained by changing the delay amount of the control signal by the delay means, an indefinite range of the sampling result caused by not satisfying the setup time or hold time of the sampling circuit. Extracting means for extracting;
A semiconductor device comprising: an adjustment unit that obtains a phase difference between the clock signal and the control signal based on an indefinite range extracted by the extraction unit and adjusts a delay amount of the control signal. The extraction means sets the scan data to the first state when all the plurality of sampling results obtained with the control signal having the same delay amount are the first value, and the plurality of sampling results all have the second value. In this case, the scan data is set to the second state, and the scan data is set to the third state when the first value and the second value are mixed in the plurality of sampling results. Scanning data storage means for storing the scanning data in
Scan data update means for updating the scan data stored in the scan data storage means by replacing a portion of the scan data stored by the scan data storage means at a predetermined interval with a third state. When,
Boundary number determination means for causing the scan data update means to update the scan data while increasing the predetermined interval until the number of boundaries at which the scan data changes is equal to or less than a predetermined number;
The semiconductor device according to claim 1, further comprising: a range extracting unit that extracts a range in which the third state in the updated scan data continues as the indefinite range.   The semiconductor device according to claim 2, wherein the adjustment unit adjusts a delay amount of the control signal so that a rising edge of the control signal coincides with a midpoint of the indefinite range extracted by the range extraction unit.   The said adjustment means determines whether to add a predetermined amount to the delay amount of the said control signal by reading the arrangement | positioning information of the memory module which the said memory hold | maintains. Semiconductor device.   5. The semiconductor device according to claim 1, further comprising selection means for selecting any one of a reference clock and a write leveling measurement clock during normal operation and outputting the selected clock signal as the clock signal. .

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