CN1933015A

CN1933015A - Semiconductor integrated circuit device

Info

Publication number: CN1933015A
Application number: CN 200610151516
Authority: CN
Inventors: 松井重纯
Original assignee: Renesas Technology Corp
Current assignee: Renesas Technology Corp
Priority date: 2005-09-13
Filing date: 2006-09-12
Publication date: 2007-03-21

Abstract

The present invention provides a semiconductor integrated circuit device provided with an interface circuit, which has realized speeding-up. A first input circuit inputs a data strobe signal therein, and a second input circuit inputs therein data formed in sync with the timing of a change in the data strobe signal. A second delay time determination circuit determines an arriving delay time relative to an internal clock in a predetermined determination region in response to the data strobe signal inputted through the first input circuit. The data sampled using the data strobe signal and inputted through the second input circuit is synchronized with the internal clock. A first delay time determination circuit is provided which determines each signal delay time in accordance with a test clock sent via a dummy input/output circuit equally set to signal delay times of a first output circuit and the first and second input circuits. The determination region is changed in time on the basis of the result of determination by the first delay time determination circuit.

Description

Semiconductor device

The cross reference of related application

The application requires the right of priority of Japanese patent application No.2006-169485 that submitted on June 20th, 2006 and the Japanese patent application No.2005-265819 that submitted on September 13rd, 2005, here its content is introduced among the application as reference.

Background of invention

The present invention relates to semiconductor device, as have the microcontroller of the memory interface controller that is connected with for example mobile DDR-SDRAM (double data rate (DDR)-Synchronous Dynamic Random Access Memory), and relate in particular to otherwise effective technique when being applied to make the synchronous synchronizing circuit of reading of data and internal clocking.

Present inventors etc. have proposed a kind of technology, wherein in SIC (semiconductor integrated circuit) such as the data processor of being introduced in as patent documentation (Japanese unexamined patent publication No. communique No.2005-78547) with the memory interface controller that is connected with DDR-SDRAM, in memory interface controller one side, make reading of data and internal clocking synchronous.This simultaneous techniques is intended to use the data strobe signal of importing in read cycle about the DDR-SDRAM shown in Figure 1 as patent documentation 1 to come the specified data gating signal to postpone with respect to the arrival of internal clocking, the signal that obtains based on the phase place by the entrained data strobe signal of mobile memory comes reading of data is sampled, and makes the reading of data and the internal clocking of being sampled synchronous based on arriving the definite result who postpones.Shown in Figure 11 as patent documentation 1, pulse control circuit is measured each signal delay of input/output (i/o) buffer, and uses it to make signal DQ and DQS synchronous.

In DDR-SDRAM, the clock synchronization circuit as DLL (or PLL) is set therein, and makes external clock and internal clocking synchronized with each other.Yet, the DDR-SDRAM of so-called mobile specification has been proposed, wherein in order to realize mobile miniaturized electronics, save clock synchronization circuit as DLL or PLL to realize low-power consumption by the portable phone representative.The memory interface that the present inventor has discussed patent documentation 1 is installed on as shown in figure 16 this microcontroller (hereinafter referred is " MCU "), and mobile DDR-SDRAM (hereinafter referred is " MB-DDR SDRAM ") is connected with it.According to these argumentations, disclose and following problem occurred.

In Figure 16, at the outgoing side of MCU, td1 time delay with respect to internal clocking appears in clock/CK and CK.Because clock synchronization circuit is not installed on the MB-DDRSDRAM, between the output of the input of clock/CK and CK and signal DQ and DQS, produce td2 time delay.At the input side of MCU, td3 time delay with respect to signal DQ and DQS appears in DQin and DQSin.Under the situation of MCU, shown in Figure 17 (A), considering that technique change, source voltage change and the worst case of temperature variation etc. and exist the fluctuation width time delay under the best-case among the td1+td3.Even under the situation of MB-DDR SDRAM, shown in Figure 17 (B), considering that technique change, source voltage change and the worst case of temperature variation etc. and also exist the fluctuation width among the td2 time delay under the best-case.When the internal clocking of MCU is observed, by shown in Figure 17 (C) with above-mentioned (A) and (B) best-case that obtains of addition and big fluctuation width occurs among the td1+td2+td3 time delay under the worst case.

Shown in Figure 18 (A), can determine when time delay td1 to td3 than hour, according to and the synchronous timing of internal clocking ckb determine that some t1 changes to high level to t5DQSin from low level point determining between some t1 and the t2, and that DQSin changes to from high level is low level between definite some t3 and t4.Yet, when shown in Figure 18 (B) time delay td1 when td3 becomes big, regularly determine some t1 comprise in definite zone of t5 the signal of DQSin uncertain during.

Its reason is as follows: writing from MCU under the pattern of MB-DDR SDRAM, MCU produces DQS, and it is offered MB-DDR SDRAM together with writing data.Reading from MCU under the pattern of MB-DDR SDRAM, MB-DDR SDRAM produces DQS, and it is offered MCU together with reading of data.Therefore, because DQS signal transmitted in both directions between MCU and MB-DDR SDRAM, it is placed in unsteady (high impedance HiZ) state before the beginning storage access.

Under read mode, read mode is transferred to MB-DDR SDRAM from MCU.As a result and since by MB-DDR SDRAM make DQS on level for low, therefore in response to the increase of time delay td1 each in the td3, DQS is being maintained at quick condition in long-time section.Therefore, because the quick condition among the MCU makes first to determine some t1 entering signal uncertain region.For example when input circuit is obtained uncertain level as the DQSin of high level, determine that circuit makes DQSin and determining that some t1 has become the false judgment of high level.Therefore, when attempting to postpone to determine some t1, can not determine DQSin as Figure 18 (A) shown in time delay td1 to td3 than hour rising point.Finally, in patent documentation 1 disclosed technology, exist restriction, because the minimum period of internal clocking is to determine with respect to the fluctuation width of td1 time delay each in the td3 for the acceleration of clock.

Summary of the invention

The purpose of this invention is to provide the semiconductor device of being furnished with the interface circuit of having realized acceleration.By the explanation and the accompanying drawing of this instructions, above-mentioned, other purposes of the present invention and novel feature will become apparent.

Below with the content of disclosed in this application typical case of brief description or representative invention.First output circuit offers external devices with external clock.The input of first input circuit is corresponding to the data strobe signal of the external clock formation at external devices place.Input of second input circuit and the synchronous data that form of the moment of data strobe signal variation.Determine that circuit is in response to the arrival time delay of determining via the data strobe signal of first input circuit input in predetermined definite zone with respect to internal clocking second time delay.Based on its result who determines, make and utilize data strobe signal to sample and synchronous by the data and the internal clocking of the input of second input circuit.Provide wherein with first output circuit and first and second input circuits in any one corresponding signal delay time of the virtual input/output circuitry that equally is provided with respectively, test clock is offered the pulse control circuit of virtual input/output circuitry and determines to determine first time delay of signal delay time circuit in response to the test clock that sends by virtual input/output circuitry.Definite zone of determining circuit second time delay changes in time based on the definite result who determines circuit first time delay.

Below with the content of disclosed in this application another the representative invention of brief description: semiconductor device is equipped with interface circuit, data processor and clock generator.Clock generator produces internal clocking and external clock.As interface circuit, provide following circuit.First output circuit offers external devices by first outside terminal with external clock.Second output circuit offers external devices by second outside terminal with the control signal that data processor forms.The 3rd output circuit will offer external devices with corresponding first data strobe signal of external clock by the 3rd outside terminal.The 4th output circuit by all round portion's terminal will offer external devices with the moment data in synchronization that first data strobe signal changes.First input circuit is by external clock corresponding second data strobe signal of the 3rd outside terminal input with the external devices place.Second input circuit is by the moment data in synchronization that change of second gating signal at the input of portion's terminal and external devices place all round.Determine that circuit is in response to the arrival time delay of determining by second data strobe signal of first input circuit input with respect to internal clocking time delay.Sample circuit is according to by preferably coming 90 ° of timing signals that obtain of phase shifts of second data strobe signal of first input circuit input data of second input circuit input are sampled.Synchronizing circuit makes the data and the internal clocking of being sampled synchronous based on the definite result who determines circuit time delay.In the 3rd output circuit and the 4th output circuit each all is a tristate output circuit, and it carries out output function when the output control signal is a kind of level, and makes it be in output high impedance state when the output control signal is another level.The 3rd output circuit is provided with a circuit, and it is set to the 3rd output outside terminal corresponding to high level or low level fixed level according to prearranged signals when making this circuit be in output high impedance state owing to the output control signal.During this period, carry out and to determine definite operation that circuit carries out time delay.

When being sampled, the data by second input circuit input use reason to be: in order to ensure foundation/retention time with respect to the data-signal at sample circuit place by second data strobe signal being offset " 90 ° " resulting timing signal, and the cycle that does not rely on data-signal in order to make it possible to guarantee the time tolerance of fullest, use with 90 ° of resulting signals of second data strobe signal skew as be used for definite sampling period or during signal.Therefore, for example when longer, can guarantee that the foundation/retention time is more much longer in the cycle of data-signal.Thus, can suitably change the side-play amount of signal, and it need not be restricted to 90 °.

Owing to each time delay of input/output circuitry corresponding definite zone in Iterim Change, the fluctuation width of each signal delay all reduces lessly in the same manner, and makes it possible to quicken.Uncertain level in the output high impedance state is according to postponing to determine to cause fixed level.Import data synchronization under the situation of the influence that can change in the time delay that is not subjected to input/output circuitry.

Description of drawings

Fig. 1 is the block scheme that illustrates according to an embodiment of semiconductor device of the present invention;

Fig. 2 is the oscillogram that is used to illustrate according to an example of the operation of via memory interface circuit 3 of the present invention;

Fig. 3 is the oscillogram that is used to illustrate according to another example of the operation of via memory interface circuit 3 of the present invention;

Fig. 4 is the oscillogram that is used to illustrate according to another example of the operation of via memory interface circuit 3 of the present invention;

Fig. 5 is the block scheme that illustrates according to another embodiment of semiconductor device of the present invention;

Fig. 6 is the correction key diagram according to an embodiment of correcting circuit shown in Figure 5;

Fig. 7 illustrates the operation of determining each time delay according to the present invention and determines result's the degree of renewal operation of synchronically controlling information and the exemplary illustration figure of memory access operations according to it;

Fig. 8 is used to illustrate that use shown in Figure 7 determines that the timing of

circuit

41 and 43 regulates the process flow diagram of operation control time delay;

Fig. 9 illustrates the operation of determining each time delay according to the present invention and determines result's the degree of renewal operation of synchronically controlling information and another exemplary illustration figure of memory access operations according to it;

Figure 10 is used for the process flow diagram that the timing adjusting operation control of

circuit

41 and 43 is determined in the use shown in the key diagram 9 time delay;

Figure 11 is the block scheme of the object lesson of the sample circuit 28 that illustrates in the present invention to be adopted;

Figure 12 is the block scheme of the object lesson of the synchronizing circuit 45 that illustrates in the present invention to be adopted;

Figure 13 is used for illustrating data DQ when the MB-DDR SDRAM that the present invention adopted is carried out write access and read access and the figure of data strobe signal DQS;

Figure 14 is the block scheme of determining an example of circuit 43 time delay that illustrates in the present invention to be adopted;

Figure 15 is the block scheme that illustrates according to another embodiment of semiconductor device of the present invention;

Figure 16 is the MCU that discussed before the present invention and the connection layout of storer;

Figure 17 is the figure that is used to illustrate the time delay between MCU and the storer;

Figure 18 is the oscillogram that is used to illustrate that the storer of Figure 16 reads;

Figure 19 is the block scheme that illustrates according to another embodiment of semiconductor device of the present invention;

Figure 20 is the oscillogram that is used to illustrate the operation of via memory interface circuit shown in Figure 19 3; And

Figure 21 is the oscillogram of an example of training (training) operation that is used to illustrate via memory interface circuit shown in Figure 19 3.

Embodiment

The block scheme of an embodiment according to semiconductor device of the present invention shown in Figure 1.Also show as the storer 6 that carries out the external devices of access thus together with this semiconductor device in the figure.Although be not particularly limited, the semiconductor device 1 shown in has constituted MCU (microcontroller) in the figure.By complementary MOS ic manufacturing technology etc. semiconductor device 1 is formed on the block semiconductor substrate of monocrystalline silicon for example.

MCU 1 has CPU (CPU (central processing unit)) 2, via memory interface circuit 3, external storage controller 4 and the clock generator 5 as the data processor shown in the typical case.CPU 2 has instruction control unit and arithmetic element.The instruction control unit steering order is extracted, and the instruction of extracting is decoded.Arithmetic element use each freely specified operand or the instruction of the decoded result of this instruction carry out data manipulation or address function, with execution command thus.Via memory interface circuit 3 can be directly connected to the storer 6 that is made of another chip.Storer 6 is configured to for example MB-DDR SDRAM.

Via memory interface circuit 3 is connected to external storage controller 4.The control of external storage controller 4 executive's interfaces is to obtain the visit to MB-DDR SDRAM 6.Although be not particularly limited, MB-DDR SDRAM 6 is equivalent to the SDRAM that has wherein removed as the clock synchronization circuit of DLL or PLL from aforesaid this known DDRSDRAM.In MB-DDR SDRAM 6, although not concrete the introduction, but on rising edge, latched various control signals (order) as the clock CK of memory clock, for example rwo address strobe signals (/RAS), column address gating signal (/CAS), write enable signal (/WE) etc.I/O data DQ is transmitted with the data strobe signal DQS as two-way gating signal.Data strobe signal DQS is defined as being used for the reference clock according to the data I/O operation of read.

When read operation, the edge (change point) that MB-DDR SDRAM 6 allows data strobe signal DQS is with to read edges of signals consistent, and exports its result.When write operation, the external storage controller 4 of MCU 1 is placed on the central authorities that write data with the edge of data strobe signal DQS, and it is outputed to MB-DDR SDRAM 6.In Fig. 1, at MB-DDR SDRAM 6 places, typically show be used for clock CK and/

input terminal

10 and 11 of CK, the input/output terminal 13 that is used for the input/output terminal 12 of data DQ and is used for data strobe signal DQS.Clock generator 5 produces internal clockings, as with corresponding clock cka of the clock of the synchronous operation that is used for MB-DDR SDRAM and ckb, and the operation reference clock CLK that is used for CPU 2 and external storage controller 4.For example, the frequency of clock b equals the twice of the frequency of clock a.

Via memory interface circuit 3 has data strobe signal DQS and reading of data DQ and the synchronous synchronizing circuit of internal clocking ckb that is used to make MB-DDR SDRAM 6 outputs, and is used for the MB-DDR SDRAM 6 direct connected input/output circuitries as external devices.

As input/output circuitry, for example mention usually be used for clock CK and/

output circuit

15 and 16 of CK, the input/output circuitry 18 that is used for the input/output circuitry 17 of data DQ and is used for data strobe signal

DQS.Output circuit

15 and 16 is according to respectively clock CK and/CK being outputed to the outside for the read operation of MB-DDR SDRAM 6 instruction (reading order) by output terminal of clock 19 and 20.Input/output circuitry 17 is connected to the data terminal 12 of MB-DDR SDRAM 6 by outside terminal 21.Input/output circuitry 18 is connected to the data strobe terminal 13 of MB-DDR SDRAM 6 by outside terminal 22.Make data strobe signal DQS and reading of data DQ and the synchronous circuit of internal clocking as being used to, provide and determined circuit 43, holding circuit 44, phase-shift circuit 27, sample circuit 28 and synchronizing circuit 45 time delay.

Determine acquisition or the time of arrival of circuit 43 measurement data gating signal DQS self time delay, so that synchronous from the signal DQS of MB-DDR SDRAM output and DQ and internal clocking.Set the time delay (DQin series) of determining circuit 43 and phase-shift circuit 27 from the input/output circuitry 18 of DQS terminal 22 to time delay and time delay (DQin series) in the mode of (clock skew (Skew)  0) about equally from the input/output circuitry 17 of DQ terminal 21 to sample circuit 28.Determine that circuit 43 utilizes internal clocking to come acquisition or the time of arrival (td1+td2+td3 time delay) of measuring-signal DQSin as a reference time delay.Determine that circuit 43 for example uses the rising edge of clock ckb and negative edge to determine when DQS becomes high level (logical zero to logical one) from low level time delay, measure the time of arrival (time delay) of DQSin thus, wherein said clock ckb is faster than the clock cka in the operating cycle that limits MB-DDR SDRAM 6, and its cycle is the twice in the cycle of clock cka.In order to avoid the edge of identification error at the variation edge of DQS consecutive hours, can be preferably be used for determining the measurement of time delay when discontinuous reading the bus cycles.

During bus cycles discontinuous, for example,, will determine that be set to holding circuit 44 as synchronically controlling information CNTsyc the time delay of the DQS that circuit 43 measures time delay during the memory refress or during storer writes the cycle.Use the synchronically controlling information CNTsyc that is set to holding circuit 44 in fetch cycle at its memory read subsequently.For example provide to be used to make and determine 43 pairs of instructions of carrying out measuring operation time delay of circuit time delay based on calibration sign on signal 30 from external storage controller 4.

Phase-shift circuit 27 is as the variable or able to programme phase-shift circuit that uses variable delay circuit.Because phase-shift circuit 27 utilizes the cycle of clock ckb to carry out 90 ° of phase shifts as benchmark, therefore need postpone to set (control time delay or adjustment) for variable delay circuit.Write cycle etc. at for example memory refress cycle, storer during the fetch cycle and carry out time delay at the very start and adjust memory read not occurring.For example, provide its operational order according to calibration sign on signal 30 from external storage controller 4.To be expressed as DQS-90 through the data strobe signal DQSin of 90 ° of phase shifts.Sample circuit 28 utilizations come reading of data DQ is sampled by rising edge and the negative edge that phase-shift circuit 27 has postponed 90 ° DQS.

Synchronizing circuit 45 has the different mulitpath of series connection progression that makes trigger, and each in the described trigger is carried out latch operation by positive clock and the negative clock of clock ckb.Synchronizing circuit 45 is selected a paths according to synchronically controlling information CNTsyc from described path.Thus, synchronizing circuit 45 is according to determine that in time delay circuit is 43 that measure, made the data DQ (DQsmp) that is sampled by sample circuit 28 synchronous with internal clocking ckb by sequential update and the synchronically controlling information CNTsyc that is maintained in the holding circuit 44 during bus cycles discontinuous.Data DQSsyc is by according to the output of holding circuit 44, by utilizing synchronizing circuit 45 with data DQsap and the synchronous resulting data of internal clocking (clock ckb), and described holding circuit 44 keeps 90 ° of phase-shift circuits 27 and determines the synchronically controlling information CNTsyc that circuit 43 calculates time delay.

In the present embodiment, the td1 and do not have td2 time delay at MB-DDR SDRAM 6 places of clock synchronization circuit time delay that in determining time delay (td1+td2+td3) of the DQS that circuit 43 measures time delay, comprises the output of above-mentioned MCU 1.As a result, the fluctuation width of the time delay that measures becomes bigger shown in Figure 17 (C), cause the restriction to the clock period thus.

In order to reduce the fluctuation width of above-mentioned time delay equivalently, be provided with virtual input/output circuitry 23, pulse control circuit 40, time delay in the present embodiment and determine circuit 41 and holding circuit 42.Virtual input/output circuitry 23 is called as the circuit that is equivalent to input circuit 15, and is so-called about input/

output circuitry

17 and 18 and the duplicate circuit of this input circuit.The lead-out terminal of the output circuit of input/output circuitry 23 and the input terminal of its input circuit are connected to outside terminal 24.Although be not particularly limited, but the simulated capacitance DC or the further electric capacity that adds that are equivalent to the input capacitance of MB-DDR SDRAM6 are connected to outside terminal 24, and the electric capacity of described interpolation has the electric capacity that is equivalent to the wiring capacitance between MCU 1 and the MB-DDR SDRAM 6.

Additional disclosure ground is connected to their corresponding

outside terminals

24,19,20 etc. such as the input circuit/output circuit of input/output circuitry 23,

output circuit

15 and 16 etc. by unshowned pad (PAD).In these pads each all is formed in the metallic region with preliminary dimension on the Semiconductor substrate.These pads have and the corresponding electric capacity of their size, and use lead frame to wait by bonding with gold thread to be connected these pads, to expose the outside terminal of the part of described lead frame and gold thread as semiconductor device.

Pulse control circuit 40 offers test pulse RPout the input end of the output circuit of input/output circuitry 23.The test pulse RPin that will transmit by the input circuit of input/output circuitry 23 is input to and determines circuit 41 time delay.Because input/output circuitry 23 is configured to aforesaid duplicate circuit, and simulated capacitance CD is connected with it, so determines td1+td3 time delay of the input and output circuit of circuit 41 measurement MCU 1 time delay.Holding circuit 42 obtains measurement (td1+td3) result wherein, and sends it to and determine circuit 43 time delay.Determine that circuit 43 measures the operation of td2 time delay basically time delay.

The oscillogram that is used to illustrate according to an example of the operation of via memory interface circuit 3 of the present invention shown in Figure 2.In Fig. 2, td1 represented from the clock CKBout of coupling in time and each the end the point of crossing of Ckout via each the time delay in the

CK terminal

10 and 11 of

output circuit

15 and 16 to MB-DDR SDRAM 6.The clock CK at

terminal

10 and 11 places and/in the point of crossing of CK each is defined as being used for reference the moment of data strobe signal DQS and data DQ.With MB-DDR SDRAM 6 be configured to export with respect to the clock CK at

terminal

10 and 11 places and/CK time delay is the data of td2, comprises the DLL circuit and not be used in the output stage that is used for data strobe signal DQS.Time delay, td3 represented to determine to time delay via input circuit 18 from DQS terminal 22 time delay of circuit 43 and phase-shift circuit 27.With these time delay td1 and td3 be arranged to virtual input/output circuitry place time delay td1 and td3 equate.

At td1 and td3 and the td2 of time delay shown in Fig. 2 (A) MCU1 hour and the example of the best/best of breed of MB-DDR SDRAM 6.Utilize this combination as a reference, variable timing is set determines that some t1 is to t5.In same width of cloth figure (A), detect DQSin and determining to change to high level between some t1 and the t2 from low level.On the other hand, Fig. 2 (B) illustrate MCU 1 place wherein time delay td1 and td3 for best, the example of and the best when being the poorest of td2 time delay at MB-DDRSDRAM 6 places/subtractive combination.In this example, MCU 1 place time delay td1 and td3 be in optimum condition, and determine that the variable timing at circuit 43 places determines that a some t1 remains former state to td5 time delay.Therefore, determine that circuit 43 detects DQSin and is associated at td2 time delay with MB-DDR SDRAM 6 places and fixes a point really to change to high level from low level between t3 and the t4 time delay.

The oscillogram that is used to illustrate according to another example of the operation of via memory interface circuit 3 of the present invention shown in Figure 3.In the mode that is similar to Fig. 2 (A) at td1 and td3 and the td2 of time delay shown in Fig. 3 (A) MCU 1 hour and the example of the best/best of breed of MB-DDR SDRAM 6.On the other hand, Fig. 3 (B) illustrate MCU 1 place wherein time delay td1 and td3 for the poorest, and the example of the poorest/best of breed of td2 time delay at MB-DDR SDRAM 6 places when being best.In this example, determine the td1 at circuit 41 definite MCU 1 places and the time delay of td3 time delay, and change the variable timing of determining circuit 43 places (moving) time delay and determine that some t1 is to t5, explicitly they are postponed one-period (3 points) so that determine the result with it, this cycle equals 1.5 times of cycle of internal clocking ckb.As a result, if the t1 that initially fixes a point really remains former state, then avoided obtaining the fault of the uncertain level of DQSin.By being similar to the mode of Fig. 3 (A), detecting DQSin and determining to change to high level from low level between some t1 and the t2.That is,, determine that the result who determines that circuit 43 carries out is reflected in time delay and determine that circuit 41 places fix time on (1.5 cycle) really, have carried out synchronous operation thus time delay though in the example shown in Fig. 3 (B), prevented the fault of definite DQSin.

The oscillogram that is used to illustrate according to another example of the operation of via memory interface circuit 3 of the present invention shown in Figure 4.In the mode that is similar to Fig. 2 (A) at td1 and td3 and the td2 of time delay shown in Fig. 4 (A) MCU 1 hour and the example of the best/best of breed of MB-DDR SDRAM 6.On the other hand, Fig. 4 (B) illustrate MCU 1 place wherein time delay td1 and td2 time delay at td3 and MB-DDR SDRAM 6 places to compare with the optimal cases of Fig. 4 (A) all be the example of the poorest combination.In this example, determine the td1 at circuit 41 definite MCU 1 places and the time delay of td3 time delay, and change the variable timing of determining circuit 43 places (moving) time delay and determine that some t1 is to t5, explicitly they are postponed one-period (2 points) so that determine the result with it, this cycle equals 1.0 times of cycle of internal clocking ckb.As a result, if the t1 that initially fixes a point really remains former state, then avoided obtaining the fault of the uncertain level of DQSin.Also detect the increase of DQSin, determining to change to high level from low level between some t3 and the t4 in response to td2 time delay.That is,, determine that the result who determines that circuit 43 carries out is reflected on the definite result (1.0 cycle) who determines circuit 41 places time delay, has carried out synchronous operation thus time delay though in the example shown in Fig. 4 (B), prevented the above-mentioned fault of definite DQSin.

The block scheme of another embodiment according to semiconductor device of the present invention shown in Figure 5.In the present embodiment, virtual input/output circuitry 23 is not provided with outside terminal 24.As a result, td1 ' time delay+td3 ' of test pulse RPin does not comprise the signal delay with the input capacitance corresponding virtual capacitor C D of outside terminal and external devices.Therefore, correcting circuit 46 is set.Correcting circuit 46 is carried out the operation that correction signal postpones.As an example as shown in Figure 6, table of corrections is used for determining time delay the Measuring Time of circuit 41, perhaps it is carried out arithmetic operation so that corrected value is added on it, forms time delay (td1+td3) thus doubtfully.So, allow holding circuit 46 to keep time delay.Present embodiment is similar with embodiment shown in Figure 1 in other configurations.According to this structure, can save outside terminal and simulated capacitance.

The operation of determining each time delay shown in Figure 7 and determine result's the degree of renewal operation of synchronically controlling information and the exemplary illustration figure of memory access operations according to it.The memory refress that MB-DDR SDRAM 6 need be provided with for each constant cycle in the mode that is similar to normal dynamic RAM, and during the cycle except that it, carry out normal storage access.During the read access in store access cycle, determine that circuit 43 carries out the time delay definite (the DQS due in is determined) of gating signal DQS time delay.Can be at memory refress and storage access does not take place during or carry out at write access and during not taking place the read cycle based on determining that the result is to the renewal (control information renewals) that remains on the value in the holding circuit 44 and use the internal latency measurement of determining circuit 41 time delay.

Yet, consider in memory refress interim and never carry out the memory read visit.In this case, can not upgrade the synchronically controlling information CNTsyc that remains in the holding circuit 44.Remain on old excessively synchronically controlling information CNTsyc in the holding circuit 44 for fear of use, when never carrying out the memory read visit, just in time before the memory refress cycle begins, produce the virtual read access cycle automatically in memory refress interim.Can avoid thus making synchronous CNYsyc old excessively.When MCU powers up, carry out internal latency and measure and virtual reading, and carry out memory refress to remove internal state.During this period of time, carry out internal latency, determining and the control information renewal to definite moment of DQS.

In Fig. 8, a width of cloth process flow diagram is shown, it is illustrated utilizing the timing adjustment operation control of determining

circuit

41 and 43 time delay shown in Figure 7.The window setting that DQS when the test pulse after the use power-on reset carries out determining the internal latency measurement that circuit 41 is done time delay and be used for storer in step 2 reading in step 1 regularly determines.In step 3, produce virtual read cycle, and carry out and determine definite operation that circuit 43 is carried out time delay.And then after it is carried out, in step 4, finish memory refress.Then, in step 5, remove the memory read access flag.In step 6, carry out internal latency and measure, and the window setting regularly determined of the DQS when in step 7, being used for storer and reading.

In step 8, the beginning store access cycle, and in step 9, finish determining to the memory refress request.If do not carry out refresh requests, then in step 10, finish determining to memory read access request.If do not carry out read request, then be used for regularly adjusting the routine of operating control and turn back to step 9.If find to have read request, then in step 11, carry out storer and read.At this moment, carry out the measurement of memory response speed.In step 12, storer is set reads sign, and with reference to above-mentioned, this routine turns back to step 9.

If carried out the memory refress request, then in step 17, finish store access cycle.In step 18, make storer and read sign decision, to determine that on being right after whether having finished storer during the store access cycle reads (even for once).If find that not finishing storer reads, and then produces virtual reading, and carry out the measurement of memory response speed in step 19.Storer reads and when being through with virtual reading, carry out memory refress (synchronization mechanism regularly is provided with) in step 13 when having carried out.In step 14, after synchronization mechanism regularly is provided with, remove storer and read sign.In step 15, carry out internal latency and measure.In step 16, be used for the window setting that DQS regularly determines when finishing storer and reading.After memory refress, this routine advances to the step 8 of beginning store access cycle.

In this structure, do not carry out clock CK and offer phase matching between the internal clocking of MB-DDR SDRAM 6.Use is measured time delay and the time delay when the I/O operation of himself from the data strobe signal DQS of MB-DDR SDRAM 6 outputs.Based on information, the data that obtain from MB-DDR SDRAM 6 are carried out correction of timing from its acquisition.

When needing or during bus cycles discontinuous, finished the measurement of each time delay of data strobe signal DQS, and during memory refress cycle etc., finished its message reflection on timing controlled mechanism.Therefore, and wherein be used for the time-controlled situation of data and compare, can avoid making become crucial the opportunity of delay time measurement and its measurement result of reflection about the information of time delay of the data strobe signal exported when the data read itself.When during the memory refress cycle, never producing the data read cycle that is defined as the initial information that is used for the timing measurement, just detect in case the memory refress cycle starts, and insert virtual read cycle.

Therefore, since the variable timing of the time delay when having considered that its own I/O is operated determine window (variable timing is determined a little) measure be used for in inside by the timing DQS of data in synchronization gating signal itself, therefore use high reliability information can make data strobe signal and internal clocking synchronous, the erroneous judgement that this high reliability information has avoided the uncertain level owing to DQS to bring.Owing to determine that by variable timing window judges the DQS signal, therefore can discern the timing of the operation that is used for MB-DDR SDRAM 6, and need not be concerned about such as problems such as reflections.Wish that in practice the signal DQS that regulates its timing measures from the data strobe signal DQS of MB-DDR SDRAM 6 outputs, has therefore introduced unnecessary error, and can not occur such as problems such as critical paths owing to use.Therefore, can make operation surplus maximum, and can easily make stable operation.In addition, owing to making the timing measurement become more accurate time delay when its I/O is operated owing to use, therefore do not need to provide unnecessary design margin, and can realize ddr interface faster for the external devices that as in the situation of general DDR SDRAM, does not have clock synchronization circuit.

The operation of determining each time delay shown in Figure 9 and determine result's the degree of renewal operation of synchronically controlling information and another exemplary illustration figure of memory access operations according to it.Present embodiment is the modification of embodiment shown in Figure 7.In the present embodiment, be each memory refress dredgeization (thinning), and do not carry out internal latency measurement (DQS that makes of delay time measurement regularly is provided with window timing and determines).That is, carry out internal latency and measure (delay time measurement made DQS the window timing decision regularly is set) only to carry out once ratio with respect to memory refress repeatedly.Therefore, in case virtual the reading when its memory refress that is right after taking place carrying out under with regard to the situation of carrying out internal latency and measuring not reading in storage access.

The process flow diagram that is used to illustrate the timing adjustment operation control of determining circuit 41 and 43 time delay that use is adopted in the present invention shown in Figure 10.Step 1 to 19 is similar with step shown in Figure 8.In addition, in step 7 ' in, after the step 6 that internal latency is measured, added and removed the step that internal latency is measured the number count device.Similarly, in step 16 ' in, after the step 15 of measuring internal latency, added and removed the step that internal latency is measured the number count device.After step 18 and 19, determine in step 20 whether the quantity that internal latency is measured has surpassed predetermined value.Surpass predetermined value if find it, then be used for regularly adjusting the step 13 that the routine of operating control advances to memory refress.Be no more than predetermined value if find it, then in step 21, carry out memory refress (synchronization mechanism regularly is provided with).Regularly be provided with as synchronization mechanism, in step 22, carry out storer and read the sign removing, in step 23, carry out number+1 that internal latency is measured, and the window setting that the DQS when being used for storer reading in step 24 regularly determines, and this routine advances to step 8, begins store access cycle therein.

The object lesson of the sample circuit 28 that adopts in the present invention shown in Figure 11.For example represent data DQ with 64 bits.Input to and be decided to be DQin[63:0].This input is latched among discrete flip-flop circuit FFr and the FFf to realize the sampling to each at rising edge DQS-r90 and its negative edge DQS-f90 of 90 ° of phase shift signalling DQS-90.DQS-f90 is the negative edge synchronizing pulse of phase shift signalling DQS-90, and DQS-r90 is the rising edge synchronizing pulse of phase shift signalling DQS-90.The output of sample circuit 28 is output as at rising edge data in synchronization DQsmp-r[63:0] and at negative edge data in synchronization DQsmp-f[63:0].

The object lesson of the synchronizing circuit 45 that adopts in the present invention shown in Figure 12.Synchronizing circuit 45 makes from the data DQsmp-r[63:0 of sample circuit 28 outputs according to the synchronically controlling information CNTsyc among the variable delay FIFO] and DQsmp-f[63:0] synchronous with internal clocking ckb.The rising edge that FFt1 is illustrated in the positive phase clock of ckb carries out the trigger of latch operation, the rising edge that FFt2 is illustrated in the positive phase clock of ckb carries out the trigger of latch operation, carries out the trigger of latch operation and FFb3 represents respectively the rising edge at the anti-phase or positive phase clock of ckb.SEL1, SEL2 and SEL3 are respectively selector switchs.Selector switch SEL2 and SEL3 can select path P AS1, PAS2 and PAS3 according to the synchronically controlling information CNTsyc from holding circuit 44 outputs.The synchronously described input of alternate selection of selector switch SEL1 and rising/decline switching controls.

The for example selection of switching input according to height and the low level of cka.When according to the time delays of determining that

circuit

41 and 43 is determined time delay, the arrival of data DQ with respect to internal clocking for the earliest the time, select path P AS1, and make the one-period of output delay ckb of selector switch SEL2 and SEL3 and synchronous thus with internal clocking ckb.When the arrival that makes data DQ a little later some the time, select path P AS2, and make 1/2 cycle of output delay ckb.When making its arrival slower, select path P AS3, and do not exporting under the situation by unnecessary delay.Make the output of selector switch SEL2 and SEL3 and ckb synchronous at FFt1, and with described output latch therein.Thus, with DQsyc as being transported to its corresponding back one-level with the ckb data in synchronization.

Relation between data DQ and data strobe signal DQS when MB-DDR SDRAM is carried out write access and read access shown in Figure 13.When write access, on phase place, postpone 90 ° with respect to data DQ and come output data strobe signal DQS.The MB-DDR SDRAM 6 that has received this signal and the edge of data strobe signal DQS be sampled data DQ synchronously.When read access, MB-DDR SDRAM 6 is output data DQ and data strobe signal DQS simultaneously.As mentioned above, interface circuit 3 receives these signals, and according to phase delay 90 ° data strobe signal DQS-90 come data DQ is sampled.

Determine an example of circuit 43 time delay shown in Figure 14.Determine that circuit 43 comprises time delay and trigger type series circuit 32, and determine from each time delay of the output of series circuit 32 and export the logical circuit 32 of 2 bit synchronous control information CNTsyc.Series circuit 32 has the level Four series circuit that is made of trigger FFa, FFb, FFc and FFd, and the level Four series circuit that is made of trigger FFe, FFf, FFg and FFh.Among trigger FFa and the FFb each is all carried out latch operation at the rising edge of the negative clock (ckb negative) of ckb.Trigger FFc carries out latch operation to each rising edge at positive phase clock (ckb) among the FFh.

The output of logical circuit 33 input FFc, FFd, FFf, FFg and FFh, and determine which makes the data DQSin that obtains become 1 with respect to ckb constantly at.Logical circuit 33 will determine that the result outputs to holding circuit 26 as 2 bit synchronous control information CNTsyc.Similarly, determine that circuit 41 also determines which makes the data RPin that obtains become 1 with respect to ckb constantly at time delay.According to clock ckb cycle and time delay td1+td3 and td2 between relation select the progression of these triggers.

The block scheme of another embodiment according to semiconductor device of the present invention shown in Figure 15.In the present embodiment, virtual input/output circuitry 23 is connected to the pad (PAD) 24 ' that is arranged on the Semiconductor substrate.Because pad 24 ' itself has stray capacitance Cp, in the figure, capacitor C p is connected to pad 24 ' doubtfully.This capacitor C p comprises the electric capacity that is formed on the electric capacity on the Semiconductor substrate.The stray capacitance of also considering pad 24 ' be formed on Semiconductor substrate on electric capacity be connected to outside electric capacity DC and compare and can only form with little electric capacity.In this case, can form time delay (td1+td3) with respect to td1 '+td3 ' time delay by proofreading and correct according to this corrected value described in the embodiment of Fig. 5.

The block scheme of another embodiment according to semiconductor device of the present invention shown in Figure 19.In the present embodiment, saved this virtual input/output circuitry 23 shown in Fig. 1,5 and 15.Correspondingly, also save pulse control circuit 40, time delay and determined circuit 41 and correcting circuit 46 and holding circuit 42.As its alternative, pull-up circuit is added to the input/output circuitry 18 that is used for data strobe signal DQS.That is, externally with cascaded structure resistor R 1 and P channel mosfet Q1 are set between terminal 22 and the source voltage.The grid of MOSFET Q1 provide by external memory controller 4 form on draw control signal DQSpu.Also show the output circuit 50 that is used for OPADD ADD, order COM etc. that in Fig. 1,5 and 15, has saved in the figure, with and outside terminal 51.

An oscillogram shown in Figure 20, it has illustrated the example of operation of the memory interface circuit 3 of Figure 19.And then training (training) cycle is provided after powering up.External storage controller 4 is in the last low level that is when drawing control signal DQSpu to enter cycle of training.Thus, make MOSFET Q1 enter conducting state, moving high level on the outside terminal 22.That is, to make signal DQS be high level from the uncertain clamping that is in high impedance HiZ by drawing on described.During cycle of training, carry out virtual reading.When being through with cycle of training and when reaching normal cycle, on draw control signal DQSpu to turn back to high level.Thus, when MCU did not carry out output function or MB-DDR SDRAM and do not carry out output function, externally terminal 22, and signal DQS becomes the uncertain level that is in high impedance HiZ during normal cycle.When finishing during the normal cycle data when MCU is written to MB-DDRSDRAM, make the output circuit of input/output circuitry 18 enter mode of operation, thereby output is used for the data strobe signal DQS of write operation.When the data read of carrying out conversely from MB-DDRSDRAM to MCU, the data strobe signal DQS that sends from MB-DDR SDRAM is imported into the input circuit of input/output circuitry 18.

Except after powering up, providing cycle of training immediately, carry out this cycle of training during virtual the reading of before the sort memory shown in Fig. 7 and 9 refreshes, inserting, perhaps MCU as the low-power consumption mode of sleep pattern or standby mode finish after commencing signal handle operating and carry out storage access before be provided this cycle of training.Perhaps, when the operating conditions (source voltage or temperature) at aforesaid MCU or MB-DDR SDRAM place when greatly this change or storer error often take place, can provide this cycle of training.Thus, can consider as required that memory access operations is provided with this cycle of training.

The oscillogram of an example of the training and operation of the memory interface circuit 3 that is used to illustrate Figure 19 shown in Figure 21.In Figure 19, td1 represent from the time engrave with each the end points the point of crossing that is similar to clock CKBout that above-mentioned mode mates and Ckout via time delay of each each in the

CK terminal

10 and 11 of MB-DDR SDRAM 6 in output circuit 15 and 16.The clock CK at

terminal

10 and 11 places and/in the point of crossing of CK each becomes each reference the moment that is used for data strobe signal DQS and data DQ.MB-DDR SDRAM 6 does not comprise the DLL circuit in the output stage that is used for data strobe signal DQS, and with its be configured to with respect to the clock CK at

terminal

10 and 11 places and/td2 time delay of CK exports.Time delay, td3 represented to determine to time delay via input circuit 18 from DQS terminal 22 time delay of circuit 43 and phase-shift circuit 27.

Shown in Figure 21 (A) at time delay td1 and td3 and the td2 MCU hour and the example of the best/best of breed of MB-DDR SDRAM.Shown in Figure 21 (B) wherein the MCU place time delay td1 and the poorest and MB-DDR SDRAM place of td3 time delay td2 the best the example of the poorest/best of breed.Owing to drawing on signal DQS during cycle of training as mentioned above in the present embodiment, and make its on level for high, so the above-mentioned uncertain level of signal DQS does not exist.Therefore, do not need to change definite point so that avoid this uncertain level.Thus, the quantity of definite point is not limited to as mentioned above.

In the example of Figure 21 (A), detect DQSin and determining to change to high level between some t2 and the t3 from low level.On the other hand, can detect in Figure 21 (B), postpone the td1 and td3 time delay at MCU place in the worst case, and DQSin is determining to change to high level from low level between some t6 and the t7.In addition, if take td1 and td3 and the td2 MCU when maximum and the poorest/subtractive combination of MB-DDR SDRAM time delay, then only under the worst condition of td2 time delay, postpone to determine point, for example, determine that point only is delayed as the situation of t7 and t8 or t8 and t9.Even postpone td1 and td3 in the worst case, because last pulling process is determining that some t1 and t2 also are identified as DQSin high level (H) even also make.The t1 place that can avoid thus fixing a point really in Figure 18 as mentioned above is defined as uncertain level.

In the present embodiment, adding for bidirectional data strobe signal can be simply and optionally conducting or the pull-up circuit that ends, wherein has the high impedance cycle between the terminal 22 of MCU and the terminal 13 corresponding with it among the MB-DDR SDRAM.So, only just make during the cycle of training such as initialization the time and draw function to enable on it.In addition, use to determine that point and its fixing simple clock synchronization high level/low level determine that circuit etc. found out the change point from the low level to the high level, feasible thus due in that can the specified data gating signal.

Even when the variable quantity of the length of delay of the I/O element that connects clock frequency height wherein and controller self becomes the DDR1-SDRAM that becomes big relatively or DDR2-SDRAM etc., even except that regularly changing the big storer such as above-mentioned mobile DDR SDRAM, for high impedance cycle wherein can not correctly determine high level/low level data strobe signal add conduction and cut-off optionally on draw function, and only just enable during the cycle of training such as initialization the time and draw function.Therefore can fully avoid wrong identification according to the high impedance cycle of data strobe signal.

Thus, when in storer DLL or similar circuit not being set, the embodiment of Figure 19 is suitable for the big variation of td2 time delay.Except above-mentioned, although even but when built-in DLL and the less relatively and relatively stable frequency of td2 time delay owing to clock ckb etc. increase make on the MCU side time delay td1+td3 above-mentioned fluctuation width when becoming big relatively, owing to added simple pull-up circuit and be provided with cycle of training, therefore also can address this is that.

The mobile DDR SDRAM that DLL wherein is not set as mentioned above can reduce the relatively large current drain of DLL circuit.Thus, it has caused being suitable for the mobile DDR SDRAM as the battery-driven storer in the situation of cellular telephone equipment etc.When a plurality of memory chips being installed on the packaging body when having the storer of large storage capacity with structure, the heat that causes owing to current drain produces and will become a big problem.Advantageously described a plurality of memory chips are installed on the packaging body it is assembled into stacked structure and construct image storer etc. by the little feature of current drain of noticing mobile DDR SDRAM with above-mentioned DLL.In this case, go wrong when quick access owing to the variation of time delay.Yet, can address this is that as the interface circuit of Memory Controller by using interface circuit according to the present invention.

Although on the basis of preferred embodiment, the foregoing invention that the inventor made is specified, the invention is not restricted to the foregoing description.In the scope that does not break away from its purport, can make various changes.For example, the concrete structure of determining pulse control circuit 40,

time delay circuit

41 and 43, synchronizing circuit 45, sample circuit 28 and 90 ° of phase-shift circuits 27 as being used to produce test pulse can adopt various embodiment.For example, synchronizing circuit 45 can be any synchronizing circuit that meets the following conditions: the timing that utilizes the PRout shown in each among Fig. 2 to 4 as a reference, found out determining definite result of

circuit

41 and 43 from time delay and then above-mentioned DQSin the rising point of the ckb after low level becomes high level obtain DQsmp thus.As for the concrete structure of 90 ° of phase-shift circuits 27, can be used as it is the circuit described in the patent documentation 1.

Can use pull-down circuit as alternative to pull-up circuit shown in Figure 19.At this moment, resistor R 1 can be made of polyresistor, diffused resistor or MOSFET.MOSFET Q1 wherein makes the MOSFET of its conduction resistance value as resistor R 1 by reducing its size etc., and makes it have resistance and these two kinds of functions of switch.

Except CPU shown in Fig. 1 and 5 and external memory controller etc., storer as ROM or RAM, cache memory also are set as required, such as the arithmetic element of multiplication/division computing circuit etc. etc. in microcontroller MCU.External devices can be the external devices that wherein synchronously data DQ is sent it back MCU with two edges of the DQS of the clock that sends from MCU and corresponding formation with it.

Claims

1, a kind of semiconductor device comprises:

Interface circuit;

Data processor; And

Clock generator,

Wherein this clock generator produces internal clocking and external clock,

Wherein this interface circuit comprises:

First output circuit, it offers external devices with this external clock;

First input circuit, the data strobe signal that its input forms corresponding to this external clock at this external devices place;

Second input circuit, its input is in the synchronous constantly data that form of the variation of this external devices place and this data strobe signal;

Virtual input/output circuitry wherein will be set to any one in described first output circuit and described first and second input circuits signal delay time respectively comparably;

Pulse control circuit, it offers described virtual input/output circuitry with test clock;

Determine circuit first time delay, it determines signal delay time in response to the described test clock that sends by described virtual input/output circuitry;

Determine circuit second time delay, it is in response to the arrival time delay of determining via the data strobe signal of described first input circuit input to determine the described internal clocking in the zone with respect to predetermined;

Sample circuit, it is according to by coming sampling via the data of described second input circuit input via the timing signal of 90 ° of acquisitions of phase shifts of the described data strobe signal of described first input circuit input; And

Synchronizing circuit, it is according to determining that definite result of circuit makes the data and the described internal clocking of being sampled synchronous described second time delay, and

Described definite zone of determining circuit wherein said second time delay changes in time according to the definite result who determines circuit described first time delay.

2, semiconductor device according to claim 1,

Wherein said interface circuit also comprises second output circuit and the 3rd output circuit, the lead-out terminal of wherein said second output circuit is connected to the input terminal of described first input circuit, and the lead-out terminal of described the 3rd output circuit is connected to the input terminal of described second input circuit

Wherein said second output circuit offers described external devices with data strobe signal, and

Wherein said the 3rd output circuit synchronously offers data described external devices constantly with the variation of the data strobe signal of exporting by described second output circuit.

3, semiconductor device according to claim 2, wherein constitute described virtual input/output circuitry output circuit lead-out terminal with and the input terminal of input circuit be connected to outside terminal.

4, semiconductor device according to claim 2 also comprises receiving the described correcting circuit of determining the output signal of circuit first time delay,

Described definite output of determining circuit wherein said first time delay is by described correcting circuit and corresponding to being complementary any one described signal delay time in described first output circuit and described first and second input circuits.

5, semiconductor device according to claim 3, wherein said external devices are the mobile DDR SDRAM with clock synchronization circuit.

6, semiconductor device according to claim 5 also comprises the memory controller that is provided with and described mobile DDR SDRAM is carried out access control corresponding to described interface circuit.

7, semiconductor device according to claim 6, wherein when there was not the read cycle in the predetermined refresh interim at described mobile DDR SDRAM, described memory controller produced and is used to carry out the described virtual read cycle of determining definite operation of circuit second time delay.

8, semiconductor device according to claim 7, wherein said memory controller produce in response to power-on reset and are used to carry out the described virtual read cycle of determining definite operation of circuit second time delay.

9, semiconductor device according to claim 8 wherein carries out definite operation of determining circuit described first time delay in the refresh cycle of described mobile DDR SDRAM.

10, semiconductor device according to claim 9 wherein carries out definite operation of determining circuit described first time delay every a plurality of refresh cycles.

11, a kind of semiconductor device comprises:

Interface circuit;

Data processor; And

Clock generator,

Wherein this clock generator produces internal clocking and external clock,

Wherein this interface circuit comprises:

First output circuit, it offers external devices with this external clock;

The 3rd input/output circuitry, it is connected to first capacitor cell;

Pulse control circuit, it can output to pulse signal described the 3rd input/output circuitry;

Determine circuit first time delay, it determines signal delay time in response to the described pulse signal that sends by described the 3rd input/output circuitry;

Determine circuit second time delay, it is in response to the arrival time delay of determining via the described data strobe signal of described first input circuit input to determine the described internal clocking in the zone with respect to predetermined;

12, semiconductor device according to claim 11,

Wherein said the 3rd output circuit synchronously offers data described external devices constantly with the variation of the described data strobe signal of exporting by described second output circuit.

13, semiconductor device according to claim 12,

Wherein said the 3rd input/output circuitry has output circuit and input circuit, and

The input terminal of the lead-out terminal of wherein said output circuit and described first capacitor cell and described input circuit is connected in parallel.

14, semiconductor device according to claim 13, wherein said first capacitor cell are to be connected with the described lead-out terminal of described output circuit and to be formed on PAD terminal on the Semiconductor substrate.

15, semiconductor device according to claim 12 also comprises receiving the described correcting circuit of determining the output signal of circuit first time delay,

16, semiconductor device according to claim 13, wherein said external devices are the mobile DDR SDRAM with clock synchronization circuit.

17, semiconductor device according to claim 16 also comprises the memory controller that is provided with and described mobile DDR SDRAM is carried out access control corresponding to described interface circuit.

18, semiconductor device according to claim 17, wherein when there was not the read cycle in the predetermined refresh interim at described mobile DDR SDRAM, described memory controller produced and is used to carry out the described virtual read cycle of determining definite operation of circuit second time delay.

19, semiconductor device according to claim 18, wherein said memory controller produce in response to power-on reset and are used to carry out the described virtual read cycle of determining definite operation of circuit second time delay.

20, semiconductor device according to claim 19 wherein carries out definite operation of determining circuit described first time delay in the refresh cycle of described mobile DDR SDRAM.

21, semiconductor device according to claim 20 wherein carries out definite operation of determining circuit described first time delay every a plurality of refresh cycles.

22, a kind of semiconductor device comprises:

Interface circuit;

Data processor; And

Clock generator,

Wherein this clock generator produces internal clocking and external clock,

Wherein this interface circuit comprises:

First output circuit, it offers external devices by first outside terminal with this external clock;

Second output circuit, it will be provided to described external devices by the control signal that described data processor forms by second outside terminal;

The 3rd output circuit, it will be provided to described external devices corresponding to first data strobe signal of described external clock by the 3rd outside terminal;

The 4th output circuit, its by all round portion's terminal will with the variation of described first data strobe signal constantly data in synchronization be provided to described external devices;

First input circuit, it imports at this external devices place second data strobe signal corresponding to this external clock by described the 3rd outside terminal;

Second input circuit, its by described all round the input of portion's terminal in the variation moment of this external devices place and this second data strobe signal data in synchronization;

Determine circuit time delay, it is in response to the arrival time delay of determining by described second data strobe signal of described first input circuit input with respect to internal clocking;

Sample circuit, it is according to by coming sampling via the data of described second input circuit input via the timing signal of 90 ° of acquisitions of phase shifts of described second data strobe signal of described first input circuit input; And

Synchronizing circuit, it makes the data and the described internal clocking of being sampled synchronous according to the definite result who determines circuit this time delay,

In wherein said the 3rd output circuit and described the 4th output circuit each all comprises tristate output circuit, it carries out output function when the output control signal is a kind of level, and when this output control signal is another kind of level, make it be in output high impedance state, and

Wherein said the 3rd output circuit is provided with a circuit, it is made as described the 3rd output outside terminal corresponding to high level or low level fixed level according to prearranged signals when making this circuit be in output high impedance state owing to this output control signal, and in this time period, carry out determine described time delay circuit definite operation.

23, semiconductor device according to claim 22, wherein said external devices are the DDR SDRAM with clock synchronization circuit.

24, semiconductor device according to claim 23 also comprises the memory controller that is provided with and the described DDRSDRAM that does not have clock synchronization circuit is carried out access control corresponding to described interface circuit.

25, semiconductor device according to claim 24, wherein said memory controller are carried out and are used for producing described prearranged signals and the virtual read cycle of definite operation of carrying out determining circuit described time delay in response to power-on reset.

26, semiconductor device according to claim 25, wherein described memory controller produces described prearranged signals when indicating the refresh cycle of the DDR SDRAM that is not provided with described clock synchronization circuit, carries out definite operation of determining circuit described time delay thus.

27, semiconductor device according to claim 26 wherein carries out determining described time delay definite operation of circuit every a plurality of refresh cycles.