JP2014017807A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction occurring in a synchronous circuit in a case where a differential clock signal and a single-end transmission signal which are transmitted in a synchronous manner are received and used for the synchronous circuit.SOLUTION: A semiconductor device comprises: a differential input receiver 2 to which differential CLK signals are input; a differential input receiver 4 to which a single-end CS signal which is a signal transmitted in synchronization with the CLK signal and has a voltage magnitude different from that of the CLK signal, and a threshold value voltage Vth to the CS signal are input; and a shift register 5. The shift register 5 defines a CS signal output from the receiver 4 as a chip select signal, and sequentially inputs DATA signals output from the receiver in synchronization with the CLK signals output from the receiver 2.

Description

  The present invention relates to a semiconductor device for inputting a differential clock signal and a single-ended transmission signal.

  For example, when data is transmitted from a microcomputer to a peripheral IC by serial communication, the microcomputer transmits a clock signal and a data signal synchronized with the clock signal. In recent years, there has been a demand for higher communication speeds, and in order to perform high-speed stable communication without communication errors even in noisy environments, use differential clock signals and differential data signals. Is effective (see, for example, Patent Document 1). The peripheral IC receives the clock signal and the data signal by the differential receiver, and supplies the clock signal and the data signal output from each differential receiver to the clock terminal and the data terminal of the shift register which is a synchronous circuit, respectively. .

  In order to further increase the communication speed using a differential signal, it is effective to reduce the amplitude of the clock signal and the data signal. Further, since the logic level of the clock signal and the data signal changes every clock half cycle or every clock cycle, and the drive current flows to the driver each time, reducing the signal amplitude is effective in reducing power consumption. Therefore, for example, even in a system having a voltage level of 3.3 V, the voltage amplitude of the differential clock signal and data signal used for communication is made smaller.

  By the way, in order to control the receiving circuit and the like of the peripheral IC, the microcomputer may transmit a signal used for controlling the synchronizing circuit, for example, a chip select signal of the shift register, in addition to the clock signal and the data signal. Such transmission signals require less speed than clock signals and data signals, and single-ended signals are used instead of differential signals in order to avoid an increase in the number of communication lines. The microcomputer synchronizes the transmission signal with the clock and transmits the voltage level inside the microcomputer (for example, 3.3 V) as it is. The peripheral IC receives this transmission signal using a Schmitt trigger communication buffer.

JP 2012-43410 A

When serial communication is actually executed using the above configuration, an event occurs in which a reception error that may be caused by a timing difference between the clock signal and the chip select signal occurs.
The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a malfunction that occurs in a synchronous circuit when a synchronous clock signal and a single-ended transmission signal that are transmitted synchronously are used in the synchronous circuit. An object of the present invention is to provide a semiconductor device for preventing the above.

  The semiconductor device according to claim 1 is a differential input type first receiver to which a differential clock signal is input, and a signal transmitted in synchronization with the clock signal, the clock signal having a voltage amplitude A second receiver of a differential input type to which a single-ended transmission signal having a different value and a threshold voltage for the transmission signal are input; and a clock signal output from the first receiver; 2 includes a synchronization circuit in which a transmission signal output from the receiver is used as a function signal in the synchronization operation.

  Since the first receiver and the second receiver are both differential input type receivers, the delay characteristics between the input and output are substantially equal. Therefore, when the clock signal is received by the first receiver and the transmission signal is received by the second receiver, the timing shift between the clock signal and the transmission signal output from the first receiver and the second receiver can be reduced. In general, the delay characteristics of the receiving circuit fluctuate according to temperature and voltage. In particular, the threshold value of the Schmitt trigger communication buffer is easily affected by temperature. According to this means, the variation of the delay amount between the first receiver and the second receiver, that is, the tolerance variation becomes substantially equal. Therefore, even if the signal formats and voltage amplitudes of the clock signal and the transmission signal are different, the timing shift between the clock signal and the transmission signal applied to the synchronization circuit can be reduced, and malfunction can be prevented.

  According to a second aspect of the present invention, there is provided a voltage output circuit that holds a set level of the threshold voltage and outputs a threshold voltage having the set level. According to this means, since the threshold voltage input to the second receiver can be changed, the delay amount of the transmission signal output from the second receiver can be adjusted according to the threshold voltage.

  According to the means described in claim 3, when the clock signal and the transmission signal are inputted to the first receiver and the second receiver, respectively, in a synchronized state, they are outputted from the first receiver. A detection circuit for detecting a shift between a clock signal and a transmission signal output from the second receiver; and a level of the threshold voltage is adjusted so as to reduce the detected shift, and the adjusted set level is And a correction circuit held in the voltage output circuit. According to this means, it is possible to accurately reduce the timing shift between the clock signal output from the first receiver and the transmission signal output from the second receiver based on the actually detected shift.

  According to the means described in claim 8, the first delay circuit that delays the clock signal output from the first receiver, and the second that delays the transmission signal output from the second receiver according to a delay command. A delay circuit; and a delay command circuit that holds a delay command for commanding a delay amount of the second delay circuit and outputs the delay command to the second delay circuit.

  According to this means, the delay amount of the second delay circuit can be changed according to the delay command, so that the delay amount of the transmission signal applied to the synchronization circuit can be adjusted. By making the delay amount of the second delay circuit larger than the delay amount of the first delay circuit, the transmission signal can be adjusted in the direction of delay with respect to the clock signal. Conversely, by making the delay amount of the second delay circuit smaller than the delay amount of the first delay circuit, the transmission signal can be adjusted in the direction of advance with respect to the clock signal.

  According to the means described in claim 9, when the clock signal and the transmission signal are input to the first receiver and the second receiver in a synchronized state, respectively, they are output from the first delay circuit. A detection circuit for detecting a deviation between a clock signal to be transmitted and a transmission signal output from the second delay circuit, and adjusting a delay amount of the second delay circuit so as to reduce the detected deviation. And a correction circuit that causes the delay command circuit to hold a delay command for commanding the delay amount. According to this means, it is possible to accurately reduce the timing shift between the clock signal and the transmission signal applied to the synchronization circuit based on the actually detected shift.

The block diagram of the communication circuit which shows the 1st Embodiment of this invention Waveform diagram of CLK signal and CS signal input to receiver and CS signal output from receiver Timing chart showing relationship between CLK signal, CS signal and DATA signal (A) When there is no deviation between the CLK signal and the CS signal, (b) Timing chart when the CS signal is delayed with respect to the CLK signal FIG. 1 equivalent diagram showing a second embodiment of the present invention Configuration diagram of detection circuit Waveform diagram for explaining the operation of the detection circuit Waveform diagram when CS signal rises and falls Waveform diagram when CS signal rise and fall are delayed Waveform diagram when CS signal rises and falls late Waveform diagram when CS signal rise is delayed and fall is advanced Waveform diagram when CS signal rises and falls with no advance or delay Waveform diagram for explaining the operation of the correction circuit FIG. 1 equivalent view showing a third embodiment of the present invention 3 equivalent figure FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention Figure 13 equivalent

In each embodiment, substantially the same parts are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. 1 to 4. For example, a vehicle engine ECU (Electronic Control Unit) includes a peripheral IC such as an ASIC in addition to a microcomputer. The microcomputer and the peripheral IC include a communication circuit for performing serial communication with each other.

  The microcomputer transmits a differential clock signal (CLK +, CLK−) through the communication lines CL1 and CL2, and transmits a differential data signal (DATA +, DATA−) synchronized with the clock signal through the communication lines CL3 and CL4. The single-ended chip select signal (CS) synchronized with the clock signal is transmitted through the communication line CL5. The chip select signal corresponds to a transmission signal in the present invention. In the following description, a clock signal, a data signal, and a chip select signal are referred to as a CLK signal, a DATA signal, and a CS signal, respectively.

  The CS signal has a voltage level of L: 0V / H: 3.3V as in the internal circuit of the microcomputer or ASIC. In contrast, the CLK +/− and DATA +/− signals have a voltage level of 1.2V ± 0.15V (1.05V / 1.35V) for the purpose of increasing communication speed and reducing power consumption. Yes.

  As shown in FIG. 1, a communication circuit 1 (corresponding to a semiconductor device) includes differential input receivers 2, 3, and 4 (first, third, and second, respectively) that receive a CLK signal, a DATA signal, and a CS signal. And a shift register 5 in which received DATA signals are sequentially stored bit by bit. The CS signal is input to the non-inverting input terminal of the receiver 4, and the threshold voltage Vth is input to the inverting input terminal. The receivers 2, 3, and 4 are configured in the same circuit and in the same size, and are arranged close to each other on the chip.

  The shift register 5 is a synchronization circuit that operates in synchronization with the CLK signal output from the receiver 2, and has n stages of D flip-flops F / F1, F / F2,..., F / Fn according to the received data length. Are connected in series. The CLK signal output from the receiver 2 is input to the CK terminals of F / F1 to F / Fn, and the CS signal output from the receiver 4 is input to the RB (reset) terminal. That is, the CS signal is a signal that functions as a reset release signal in the shift register 5.

  Next, the operation of the present embodiment will be described with reference to FIGS. In the present embodiment, the timing difference between the CLK signal and the CS signal having a voltage amplitude different from the signal format on the communication line is described. Since the CLK signal and the DATA signal have the same signal format and voltage amplitude on the communication line, the timing difference between them is sufficiently small. For simplification, n bit data from D1 (LSB) to Dn (MSB) are transmitted and received. As is well known, a start bit, a parity bit, a stop bit, etc. are actually transmitted and received.

  The receiver 2 of the communication circuit 1 outputs an H level CLK signal when the voltage level of the input CLK + signal is higher than the voltage level of the CLK− signal, and the voltage level of the CLK + signal is higher than the voltage level of the CLK− signal. When it is low, the L level CLK signal is output. The same applies to the receiver 3 to which the DATA + signal and the DATA− signal are input. On the other hand, as shown in FIG. 2, the receiver 4 outputs an H-level CS signal when the voltage level of the input CS signal is higher than the threshold voltage Vth, and the voltage level of the input CS signal is When it is lower than the threshold voltage Vth, an L level CS signal is output. By appropriately setting the level of the threshold voltage Vth, the deviation between the CLK signal output from the receiver 2 and the CS signal output from the receiver 4 can be brought close to zero (see FIG. 2).

  The microcomputer starts transmission of data D1 (LSB) at the timing of the down edge of the CLK signal and sets the CS signal to the H level. Further, the transmission of the data Dn (MSB) is terminated at the timing of the down edge of the CLK signal, and the CS signal is returned to the L level. FIG. 4 shown as a comparative example is a timing chart of a conventional example that receives a CS signal using a Schmitt trigger communication buffer.

  FIG. 4A shows an ideal case where there is no deviation between the CLK signal output from the receiver and the CS signal output from the communication buffer, and the wiring delay in the layout described later is equal. F / F1 to F / Fn are released from reset when the CS signal becomes H level, and take in data at the rising edge of the CLK signal. In F / F1 to F / Fn, a setup time Ts and a hold time Th are defined for the DATA signal and CS signal for the up edge of the CLK signal. In this ideal case, the CS signal is determined before the setup time Ts.

  FIG. 4B shows a timing shift that actually occurs in the conventional example. When a CLK signal and a CS signal having different signal formats and voltage levels are received using a receiver and a communication buffer, respectively, a relative delay of Td1 occurs in the CS signal. Further, due to the layout of the ASIC, a wiring delay corresponding to a maximum of Td2 occurs in the CS signal according to the distance between the output terminal of the communication buffer and each of the RB terminals F / F1 to F / Fn. In order to assume the worst case, the wiring delay of the CLK signal from the output terminal of the receiver to each of the CK terminals F / F1 to F / Fn is set to zero. In such a case, there is a possibility that the setup time Ts cannot be secured for the CS signal, and this is considered to be the cause of the communication error that has occurred conventionally.

  FIG. 3 shows a timing chart of the present embodiment. Again, in order to assume the worst case, the wiring delay of the CLK signal after the output terminal of the receiver 2 is zero. In order from the top, an ideal CS signal output from the receiver 4 (no deviation from the CLK signal), an actual CS signal output from the receiver 4, a CS signal input to the RB terminal of the F / F1, F / F2 CS signal input to RB terminal, CS signal input to RB terminal of F / Fn, CLK signal input to each CK terminal of F / F1 to F / Fn, and input to D terminal of F / F1 Represents a DATA signal.

  Since the CS signal is received by the receiver 4 having the same differential input format as the CLK signal and an appropriate threshold voltage Vth is set as shown in FIG. 2, the CLK signal output from the receiver 2 and the CS signal output from the receiver 4 The timing shift decreases to Td3 (<Td1). As a result, even if the wiring delay Td2 described above exists, the CS signal is determined to be at the H level before the setup time Ts by the margin time Tm1 with respect to the up edge of the CLK signal. In addition, the CS signal input to F / F1 to F / Fn is fixed at the L level before the setup time Ts with respect to the up edge of the next CLK signal holding the last data Dn (MSB).

  The communication circuit 1 of the present embodiment described above receives a single-ended CS signal by a receiver 4 having a differential input format in the same manner as the receiver 2 that receives a differential CLK signal. Since the receivers 2 and 4 are configured to be the same size in the same circuit and are arranged close to each other, the delay characteristics between the input and output are almost equal, and the variation in delay amount due to temperature or the like, that is, the tolerance variation is also almost equal. Will be equal.

  Accordingly, the CS signal is received using the Schmitt trigger communication buffer by appropriately setting the threshold voltage Vth used in the receiver 4 in accordance with the difference in voltage amplitude between the CLK signal and the CS signal on the communication line. Compared to the conventional configuration, the timing difference between the CLK signal and the CS signal respectively output from the receivers 2 and 4 can be reduced. As a result, even when there is a wiring delay between the receiver 4 and the shift register 5, the CS signal setup time Ts with respect to the CLK signal can be secured, and the occurrence of a communication error can be prevented.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. The communication circuit 11 includes a circuit that adjusts the first threshold voltage VthH and the second threshold voltage VthL input to the inverting input terminal of the receiver 4. The voltage output circuit 12 includes a storage circuit that holds the setting levels of the threshold voltages VthH and VthL, and a D / A converter that outputs the threshold voltages VthH and VthL by D / A converting the held setting levels. And. The voltage output circuit 12 outputs the threshold voltage VthH when the CS signal rises from the L level to the H level, and outputs the threshold voltage VthL when the CS signal falls from the H level to the L level.

  The detection circuit 13 detects a shift between the CLK signal output from the receiver 2 and the CS signal output from the receiver 4. As shown in FIG. 6, the detection circuit 13 includes inverters 51, 52, AND gates 53, 55, 56, 59-61, 65-68, a NAND gate 54, D flip-flops 57, 58, 62-64, and an average processing circuit. (Not shown). The detection circuit 13 receives the CLK signal and the CS signal, and leads the phase difference signal (rising), the leading phase difference signal (falling), the lagging phase difference signal (rising), the lagging phase difference signal (falling), A delay determination signal (rising edge) and an advance / delay determination signal (falling edge) are output.

  The correction circuit 14 adjusts the levels of the threshold voltages VthH and VthL so that the detected deviation is reduced, and stores the adjusted set level in the storage circuit of the voltage output circuit 12. In the adjustment operation by the detection circuit 13 and the correction circuit 14, the microcomputer and the peripheral IC shift to the test mode while the mode signal is in the test mode, that is, immediately after the power is turned on or according to an instruction from the microcomputer. It is executed during a period of repeated transmission in a synchronized state.

  FIG. 7 is an explanatory diagram of the operation of the detection circuit 13. (A) shows a case where the CS signal is delayed with respect to the CLK signal, and (b) shows a case where the CS signal is advanced with respect to the CLK signal. In order to clearly show the shift, the shift between the two signals is slightly exaggerated. The detection circuit 13 becomes 3.3V (first voltage) during a shift period in which the AND signal (/ CLK · CS) of the inverted signal of the CLK signal and the CS signal becomes H level, and 0V (first voltage) during the period when it becomes L level. 2), a delayed phase difference signal (rising edge) is generated and the average voltage is output. For the averaging process, an integration circuit (duty voltage conversion) or the like may be used.

  Similarly, the detection circuit 13 generates a delayed phase difference signal (falling) by the AND signal (/ CLK · / CS) of the inverted signal of the CLK signal and the inverted signal of the CS signal, and the CLK signal and the CS signal The lead phase difference signal (rising edge) is generated by the AND signal (CLK · CS), and the lead phase difference signal (falling) is generated by the AND signal (CLK · / CS) of the inverted signal of the CLK signal and the CS signal. These average voltages are output. Each phase difference signal is masked to 0 V during a period not related to the difference between the CLK signal and the CS signal. The average voltage of the phase difference signal, which is a duty signal, has a value corresponding to the amount of phase shift between the CLK signal and the CS signal.

  8 to 12 show the advance / delay determination signal and the phase difference signal when the CS signal is advanced / delayed with respect to the CLK signal. The H level is 3.3 V, the L level is 0 V, and the cycle T of the CLK signal is 100 ns. FIG. 8 shows a case where the rise and fall of the CS signal are both advanced by 15 ns. FIG. 9 shows a case where the rise and fall of the CS signal are both delayed by 15 ns. FIG. 10 shows a case where the CS signal rises by 15 ns and the fall is delayed by 15 ns. FIG. 11 shows a case where the rising edge of the CS signal is delayed by 15 ns and the falling edge is advanced by 15 ns. FIG. 12 shows a case where there is no progress or delay in the rise and fall of the CS signal.

  When the CS signal rises with respect to the CLK signal, the detection circuit 13 generates a lead phase difference signal (rise) that changes from 0 V to 3.3 V for the advance time (15 ns) when the CS signal rises. . At this time, the advance / delay determination signal (rising edge) is set to 3.3V. Even when the CS signal falls with respect to the CLK signal, the detection circuit 13 proceeds from 0V to 3.3V for the advance time (15 ns) when the CS signal falls. Is generated. At this time, the advance / delay determination signal (falling) is set to 3.3V.

  When the rising edge of the CS signal is delayed with respect to the CLK signal, the detecting circuit 13 delays the phase difference signal from 0 V to 3.3 V only when the CS signal rises (T / 2−delay time) (35 ns). (Rise) is generated. At this time, the advance / delay determination signal (rising edge) is set to 0V. When the fall of the CS signal is delayed with respect to the CLK signal, the detection circuit 13 delays from 0V to 3.3V only when the CS signal falls (T / 2−delay time) (35 ns). A phase difference signal (falling) is generated. At this time, the advance / delay determination signal (falling) is set to 0V.

  When there is no advance or delay in the rising edge of the CS signal with respect to the CLK signal, the detection circuit 13 has a constant advance phase difference signal (rising edge) of 0 V and a delay from 0 V to 3.3 V by T / 2 (50 ns). A phase difference signal (rising edge) is generated. The same applies to the fall of the CS signal. The detection circuit 13 outputs average values of the generated advance phase difference signal (rising / falling) and delayed phase difference signal (rising / falling).

  When the CS signal rises, the correction circuit 14 advances the phase advance / delay and phase difference (deviation) based on the delayed phase difference signal (rise), the advance phase difference signal (rise), and the advance / delay determination signal (rise). The amount of the threshold voltage VthH is adjusted so that the deviation converges to zero. That is, the level of the threshold voltage VthH is adjusted so that the average value of the leading phase difference signal (rising edge) becomes zero and the average value of the delayed phase difference signal (rising edge) becomes maximum. The maximum value here is a voltage determined by an interval (number of clocks) at which the CS signal periodically rises and an H level voltage.

  Similarly, when the CS signal falls, the correction circuit 14 advances the phase based on the delayed phase difference signal (falling), the advanced phase difference signal (falling), and the advanced / lag determining signal (falling). / The delay and the phase difference (shift amount) are grasped, and the level of the threshold voltage VthL is adjusted so that the shift converges to zero. That is, the level of the threshold voltage VthL is adjusted so that the average value of the leading phase difference signal (falling) becomes zero and the average value of the delayed phase difference signal (falling) becomes maximum. The maximum value here is as described above.

  FIG. 13 shows changes in the CS signal before and after the level adjustment of the threshold voltages VthH and VthL. Since the CS signal is delayed in the example of the rising edge of the CS signal shown in FIG. 13A, the correction circuit 14 adjusts so as to reduce the delay of the CS signal by lowering the level of the threshold voltage VthH. In the example of the falling edge of the CS signal shown in FIG. 13B, since the CS signal is advanced, the correction circuit 14 adjusts so as to increase the delay of the CS signal by lowering the level of the threshold voltage VthL. By repeating the above adjustment for the synchronized CLK signal and CS signal one or more times, it is possible to reduce timing deviation between the CLK signal and CS signal output from the receivers 2 and 4, respectively.

  According to the present embodiment, the voltage output circuit 12 can set the threshold voltages VthH and VthL separately for the rising and falling edges of the CS signal, so that the setting level is adjusted to shift the CLK signal and the CS signal. Can be adjusted accurately. Since the detection circuit 13 and the correction circuit 14 detect the deviation between the CLK signal and the CS signal in the test mode and adjust the threshold voltages VthH and VthL so that the deviation becomes zero, even when the ECU is operating. The deviation can be calibrated by executing the test mode. In addition, operations and effects similar to those of the first embodiment can be obtained.

(Third embodiment)
Next, a third embodiment will be described with reference to FIGS. 14 and 15. The communication circuit 21 includes D flip-flops F / F22 and F / F23 for synchronizing the DATA signal and CS signal output from the receivers 3 and 4 with the CLK signal output from the receiver 2, respectively. F / F 22 and F / F 23 capture the DATA signal and CS signal at the rising edge of the CLK signal, respectively. Along with the synchronization, F / F1 to F / Fn of the shift register 5 are changed from capturing the up edge of the CLK signal to capturing the down edge.

  FIG. 15 shows a timing chart of the present embodiment. In order to assume the worst case as in FIG. 3, the wiring delay of the CLK signal after the output terminal of the receiver 2 is set to zero. In order from the top, the ideal CS signal output from the receiver 4 (no deviation from the CLK signal), the actual CS signal output from the receiver 4, the CS signal output from the F / F 23, and the RB terminal of the F / F1 CS signal input, CS signal input to RB terminal of F / F2, CS signal input to RB terminal of F / Fn, CLK signal input to each CK terminal of F / F1 to F / Fn, The DATA signal output from the receiver 3 and the DATA signal output from the F / F 22 (input to the D terminal of the F / F 1) are shown.

  By providing the F / F 23, the deviation between the CS signal and the CLK signal generated by the receivers 2 and 4 is temporarily eliminated. Due to the adjustment operation described in the second embodiment, the difference between the CLK signal output from the receiver 2 and the CS signal output from the receiver 4 is reduced to Td3. For this reason, with respect to F / F 23, the CS signal is fixed at the H level before the setup time Ts for the up edge of the CLK signal.

  Between the Q terminal of the F / F 23 and each of the RB terminals F / F1 to F / Fn, a wiring delay of a maximum of Td2 occurs in the CS signal. However, as a result of synchronization, the CS signal is fixed at the H level for F / F1 to F / Fn by a margin time Tm2 (> Tm1) before the setup time Ts for the down edge of the CLK signal. The CS signal input to F / F1 to F / Fn returns to the L level before the setup time Ts for the down edge of the next CLK signal holding the last data Dn (MSB).

  The communication circuit 21 of the present embodiment includes F / F 22 and F / F 23 for synchronizing the DATA signal and the CS signal with the CLK signal. By placing the F / F 23 close to the receiver 4 on the chip, the CS signal level is determined before the setup time Ts for any of the F / F 23 and F / F 1 to F / Fn. Can do. As a result, the margin with respect to the setup time Ts is improved compared to the first and second embodiments, and communication errors can be prevented more reliably.

(Fourth embodiment)
Next, a fourth embodiment will be described with reference to FIG. A communication circuit 31 of a peripheral IC such as an ASIC has a configuration in which the detection circuit 13 and the correction circuit 14 are removed from the communication circuit 21 described in the third embodiment. The shipping inspection device 32 is composed of, for example, an IC tester, and includes a communication circuit 33, a detection circuit 13, and a correction circuit 14.

  In the inspection process before shipment, the peripheral IC is connected to the shipment inspection device 32. The communication circuit 33 transmits a CLK signal and a CS signal synchronized with the CLK signal to the communication circuit 31. The detection circuit 13 of the shipping inspection device 32 detects a deviation between the CLK signal output from the receiver 2 and the CS signal output from the receiver 4. The correction circuit 14 adjusts the levels of the threshold voltages VthH and VthL so that the detected deviation is reduced. The shipping inspection device 32 outputs the adjusted setting level to the peripheral IC and stores it in the storage circuit of the voltage output circuit 12.

  This embodiment can provide the same operations and effects as those of the third embodiment. Further, since the communication circuit 31 of the peripheral IC does not need to include the detection circuit 13 and the correction circuit 14, the chip area can be reduced by the amount of these circuits.

(Fifth embodiment)
Next, a fifth embodiment will be described with reference to FIGS. 17 and 18. The communication circuit 41 of the present embodiment includes delay circuits 42, 43, and 44 that delay the output signals of the receivers 2, 3, and 4, instead of using the constant threshold voltages VthH and VthL. The delay circuits 42 and 44 correspond to a first delay circuit and a second delay circuit.

  The delay circuits 42 and 43 for delaying the CLK signal and the DATA signal are each composed of a fixed number of buffer circuits connected in series. The delay circuit 44 that delays the CS signal is configured to be able to change the number of serial connections of the buffer circuits to one or more in accordance with a delay command that commands a delay amount.

  The delay command circuit 45 holds the numbers NH and NL of serial connection of the buffer circuits in the delay circuit 44 in the memory circuit, and outputs an NH delay command when the CS signal rises from the L level to the H level. When NL falls from the H level to the L level, an NL delay command is output. The numbers NH and NL connected in series correspond to the first delay amount and the second delay amount, respectively. The reason why the delay circuits 42 and 43 are provided not only for the receiver 4 but also for the receivers 2 and 3 is to allow the CS signal to be adjusted in both the forward and delayed directions with respect to the CLK signal and the DATA signal.

  As described in the second embodiment, the detection circuit 13 detects the difference between the CLK signal output from the delay circuit 42 and the CS signal output from the delay circuit 44 when the transmission signal rises and falls, respectively. Is detected. The correction circuit 46 grasps the phase advance / delay and the phase difference (shift amount) when the CS signal rises, and adjusts the number of series connections NH so that the shift converges to zero. That is, the series connection number NH is adjusted so that the average value of the leading phase difference signal (rising) becomes zero and the lagging phase difference signal (rising) becomes the maximum.

  Similarly, the correction circuit 46 grasps the phase advance / delay and the phase difference (shift amount) when the CS signal falls, and adjusts the number of serial connections NL so that the shift converges to zero. That is, the series connection number NL is adjusted so that the average value of the lead phase difference signal (falling) becomes zero and the delay phase difference signal (falling) becomes the maximum. The correction circuit 46 stores the adjusted series connection numbers NH and NL in the storage circuit of the delay command circuit 45.

  The adjustment operation by the detection circuit 13 and the correction circuit 46 is executed while the mode signal is in the test mode. The correction circuit 46 increases / decreases the serial connection number NH one by one in the test mode, obtains a lower limit value at which a communication error starts and an upper limit value at which a communication error starts, and obtains the lower limit value and the upper limit value. May be determined as the number NH connected in series. The number NL of series connections can be determined similarly.

  FIG. 18 shows changes in the CS signal before and after the adjustment of the number of series connections NH and NL. Since the CS signal is delayed in the example of the rising edge of the CS signal shown in FIG. 18A, the correction circuit 46 adjusts so as to reduce the delay of the CS signal by reducing the number NH connected in series. In the example of the falling edge of the CS signal shown in FIG. 18B, since the CS signal is advanced, the correction circuit 46 adjusts so that the delay of the CS signal is increased by increasing the number of serial connections NL. By repeating the above adjustment one or more times, it is possible to adjust so that the deviation between the CLK signal input to F / F1 to F / Fn and the CS signal approaches zero. According to this embodiment, the same effect as that of the third embodiment can be obtained.

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

  The synchronization circuit operates in synchronization with the CLK signal output from the receiver 2 and shifts if the transmission signal (CS signal in the above embodiment) output from the receiver 4 is used as a function signal in the synchronization operation. The register 5 is not limited. The transmission signal is not limited to the CS signal. The semiconductor device according to the present invention can be applied to various circuits other than the communication circuit.

  The first embodiment may be modified as follows. That is, F / F22 and F / F23 may be added and synchronized, and F / F1 to F / Fn of the shift register 5 may be changed to capture the down edge of the CLK signal. A voltage output circuit 12 may be added to hold the set level of the threshold voltage Vth in the memory circuit. Further, the set level of the threshold voltage Vth held may be configured to be rewritable.

  In the second, third, fourth, and fifth embodiments, as in the first embodiment, the threshold voltage when the CS signal rises from the L level to the H level, and the CS signal from the H level to the L level. The threshold voltage may be set to a common value Vth when falling to the level.

  The fifth embodiment may be modified as follows. That is, F / F22 and F / F23 may be deleted, and F / F1 to F / Fn of the shift register 5 may be changed to capture the up edge of the CLK signal. Further, the detection circuit 13 and the correction circuit 46 may be omitted. In this case, similarly to the fourth embodiment, a shipping circuit including a detection circuit 13, a correction circuit 46, and a communication circuit 33 is connected in an inspection process before shipment, and a delay circuit is provided so as to reduce the detected deviation. The numbers NH and NL of the buffer circuits connected in series in 44 may be adjusted. The shipment inspection apparatus outputs the adjusted series connection numbers NH and NL to the peripheral IC and stores them in the storage circuit of the delay command circuit 45. Furthermore, the number NH connected in series and the number NL connected in series may be made a common value without being distinguished.

  In the configuration in which the F / F 22 and the F / F 23 are provided in the above embodiments and modifications, F / F1 to F / Fn of the shift register 5 may be changed to capture the up edge of the CLK signal. In this case, the fetch timing of F / F22 and F / F23 and the fetch timing of F / F1 to F / Fn differ by one clock cycle.

  Also in the second to fourth embodiments, the correction circuit 14 gradually increases or decreases the threshold voltage VthH in the test mode, and a lower limit value at which a communication error starts and an upper limit value at which a communication error starts. The median value between the lower limit value and the upper limit value may be determined as the threshold voltage VthH. The threshold voltage VthL can be determined similarly.

  In each of the above embodiments and modifications, even if the threshold voltages Vth, VthH, VthL or the number of series connections NH, NL are adjusted, the difference between the CLK signal and the CS signal input to F / F1 to F / Fn However, if it is not possible to reduce the setup time Ts to a range that can secure the setup time Ts, an error flag may be transmitted to the microcomputer.

  In the drawing, 1, 11, 21, 31, 41 are communication circuits (semiconductor devices), 2 is a receiver (first receiver), 3 is a receiver (third receiver), 4 is a receiver (second receiver), and 5 is a shift. Register (synchronization circuit), 12 is a voltage output circuit, 13 is a detection circuit, 14 and 46 are correction circuits, 23 is a D flip-flop (synchronization circuit), 42 is a delay circuit (first delay circuit), 44 is a delay circuit (Second delay circuit) 45 is a delay command circuit.

Claims (14)

A first receiver (2) in a differential input format to which a differential clock signal is input;
A differential input type second receiver to which a single-ended transmission signal having a voltage amplitude different from that of the clock signal and a threshold voltage for the transmission signal are input in synchronization with the clock signal. (4) and
And a synchronization circuit (5) that operates in synchronization with a clock signal output from the first receiver, and a transmission signal output from the second receiver is used as a function signal in the synchronization operation. Semiconductor device.   The semiconductor device according to claim 1, further comprising a voltage output circuit (12) for holding a set level of the threshold voltage and outputting a threshold voltage having the set level. When the clock signal and the transmission signal are input to the first receiver and the second receiver in a synchronized state, respectively, the clock signal output from the first receiver and the second receiver are output. A detection circuit (13) for detecting a deviation from the transmission signal;
A correction circuit (14) for adjusting a level of the threshold voltage so as to reduce the detected deviation and holding the adjusted set level in the voltage output circuit. 2. The semiconductor device according to 2. The voltage output circuit (12) maintains a set level of a first threshold voltage and a second threshold voltage, outputs a first threshold voltage when the transmission signal rises, and the transmission signal Output the second threshold voltage when falling,
The detection circuit (13) detects a shift between a clock signal output from the first receiver and a transmission signal output from the second receiver, respectively, when the transmission signal rises and falls.
The correction circuit (14) adjusts the level of the first threshold voltage when the transmission signal rises, and adjusts the level of the second threshold voltage when the transmission signal falls. The semiconductor device according to claim 3. The detection circuit (13) generates a first voltage during a period in which there is a deviation between the clock signal output from the first receiver and the transmission signal output from the second receiver. The second voltage is generated during a period excluding the generated period, and an average value of the generated voltages is output.
5. The semiconductor device according to claim 3, wherein the correction circuit adjusts the level of the threshold voltage based on an average value output from the detection circuit. When the period of the clock signal is T,
When the rise / fall of the transmission signal output from the second receiver is advanced with respect to the clock signal output from the first receiver, the detection circuit (13) A leading phase difference signal that changes from the second voltage to the first voltage for the leading time when falling, and the rising / falling of the transmission signal output from the second receiver relative to the clock signal output from the first receiver When the fall is delayed, a delayed phase difference signal is generated from the second voltage to the first voltage only when the transmission signal rises / falls (T / 2−delay time). Configured to output each average value of the advanced phase difference signal and the delayed phase difference signal,
The correction circuit (14) adjusts the level of the threshold voltage so that an average value of the leading phase difference signal becomes zero and an average value of the delayed phase difference signal becomes maximum. The semiconductor device according to claim 3 or 4.   The synchronization circuit according to claim 1, further comprising: a synchronization circuit that synchronizes a transmission signal output from the second receiver with a clock signal output from the first receiver. Semiconductor device. A first delay circuit (42) for delaying a clock signal output from the first receiver;
A second delay circuit (44) for delaying a transmission signal output from the second receiver according to a delay command;
2. The delay command circuit according to claim 1, further comprising: a delay command circuit that holds a delay command for commanding a delay amount of the second delay circuit and outputs the delay command to the second delay circuit. Semiconductor device. A clock signal output from the first delay circuit and an output from the second delay circuit when the clock signal and the transmission signal are input to the first receiver and the second receiver in a synchronized state, respectively. A detection circuit (13) for detecting a deviation from the transmitted signal;
A correction circuit (46) for adjusting a delay amount of the second delay circuit so as to reduce the detected deviation, and holding the delay command for instructing the adjusted delay amount in the delay command circuit; The semiconductor device according to claim 8. The delay command circuit (45) holds a delay command for commanding a first delay amount and a delay command for commanding a second delay amount, and outputs a delay command related to the first delay amount when the transmission signal rises. And outputting a delay command related to the second delay amount when the transmission signal falls,
The detection circuit (13) detects a deviation between a clock signal output from the first delay circuit and a transmission signal output from the second delay circuit, respectively, when the transmission signal rises and falls. ,
The correction circuit (46) adjusts the first delay amount when the transmission signal rises, and adjusts the second delay amount when the transmission signal falls. Semiconductor device. The detection circuit (13) generates a first voltage during a period in which a shift occurs between the clock signal output from the first delay circuit and the transmission signal output from the second delay circuit, The second voltage is generated in a period excluding the period in which the deviation occurs, and an average value of the generated voltage is output,
11. The semiconductor device according to claim 9, wherein the correction circuit adjusts a delay amount of the second delay circuit based on an average value output from the detection circuit. When the period of the clock signal is T,
When the rising / falling edge of the transmission signal output from the second delay circuit is advanced with respect to the clock signal output from the first delay circuit, the detection circuit (13) Transmission that is output from the second delay circuit in response to a clock signal that is output from the first delay circuit by generating an advance phase difference signal that changes from the second voltage to the first voltage for the advance time when rising or falling. When the signal rise / fall is delayed, a delayed phase difference signal is generated from the second voltage to the first voltage only when the transmission signal rises / falls (T / 2−delay time). The average value of the generated advance phase difference signal and delayed phase difference signal is output,
The correction circuit (46) adjusts the delay amount of the second delay circuit so that the average value of the lead phase difference signal becomes zero and the average value of the delay phase difference signal becomes maximum. The semiconductor device according to claim 9 or 10.   13. The synchronization circuit according to claim 8, further comprising: a synchronization circuit that synchronizes a transmission signal output from the second delay circuit with a clock signal output from the first delay circuit. A semiconductor device according to 1. A differential input type third receiver (3) to which a differential data signal transmitted in synchronization with the clock signal is input;
The synchronization circuit (5) uses a transmission signal output from the second receiver as a chip select signal, and outputs a data signal output from the third receiver in synchronization with a clock signal output from the first receiver. 14. The semiconductor device according to claim 1, wherein the semiconductor device is a shift register that inputs sequentially.

Images