TWI657672B - Delivery unit - Google Patents

Abstract

A transmission unit includes a first buffer, a second buffer, and a logic circuit. A receiving unit buffers and amplifies the potential change of a contact and outputs it as a digital input signal. The first buffer decides to buffer and amplify a digital output signal from a digital circuit according to the logic value of a gate output signal to output to the contact. The second buffer buffers and amplifies the digital output signal and outputs it to the contact. The logic circuit determines whether the logic values of the digital output signal and the digital input signal are different to determine the logic value of the generated gate output signal, so as to realize a low-power transmission that conforms to the mobile industry processor interface and has a simpler design unit.

Description

Delivery unit

The invention relates to a transmission unit, in particular to a low power consumption transmission unit of Mobile Industry Processor Interface (MIPI).

Referring to FIG. 1, a conventional transmission unit 91 is suitable for a receiving unit 92, a digital circuit 94, and a contact 93, and includes a first buffer 911 and a second buffer 912. The transmitting unit 91 and the receiving unit 92 are electrically connected to the digital circuit 94 and the contact 93, and conform to a mobile industry processor interface (MIPI). Therefore, the transmission unit 91 must take into account both low power consumption and high output impedance. On this premise, the transmission unit 91 must be able to provide a sufficiently fast slew rate and rising / falling time.

The second buffer 912 of the transmission unit 91 is electrically connected to the digital circuit 94 to receive a digital output signal DATA_TX, and is also electrically connected to the contact 93 to buffer and amplify the digital outgoing signal and output it to the contact 93. The first buffer 911 and the second buffer 912 of the transmission unit 91 are connected in parallel, and also receive a The enable signal BW_EN of the bit circuit 94 determines whether the digital output signal DATA_TX is buffered and amplified and output to the contact 93. For example, when the logic value of the enable signal BW_EN is equal to logic 1, the first buffer 911 outputs the digital output signal DATA_TX to the contact 93. In addition, compared with the first buffer 911 and the second buffer 912, the driving force of the first buffer 911 is stronger but the output impedance is lower (Strong Buffer), and the driving force of the second buffer 912 is weaker But the output impedance is higher (Weak Buffer).

The receiving unit 92 receives the change in potential on the contact 93 and outputs a digital input signal DATA_RX to the digital circuit 94. The receiving unit is, for example, a buffer to buffer the change in potential on the contact 93 Amplified to become the digital input signal DATA_RX.

The digital circuit 94 outputs the digital output signal DATA_TX to the contact 93 through the transmission unit 91 to be transmitted to another circuit. When the digital circuit 94 is to receive the digital input data, the digital circuit 94 does not output the digital output signal DATA_TX to avoid affecting the potential change on the contact 93. At this time, the potential change on the contact 93 It is output to the contact 93 through another circuit, and then output as the digital input signal DATA_RX through the receiving unit 92.

Referring again to FIG. 2, FIG. 2 is a timing chart, and FIG. 2 is used to explain the relationship between multiple signals when the transmission unit 91 outputs the digital output signal DATA_TX to the contact 93, where the horizontal axis represents time and the vertical axis The axis represents the change in potential, such as logic 1 and Logic 0, the contact signal PAD indicates that the potential on the contact 93 changes. When the digital circuit 94 wants to output data, the digital output signal DATA_TX is generated, and when the current two data are different, that is, one is logic 0 and the other is logic 1, the digital circuit 94 will enable The logic value of the signal BW_EN changes to 1, to control the first buffer 911 to output the digital output signal DATA_TX, and help the potential transition on the contact 93, such as from logic 0 to logic 1 or from logic 1 to Logic 0. On the contrary, when the data of the previous and next two are the same, that is, when both are logic 0 or logic 1, the digital circuit 94 changes the logic value of the enable signal BW_EN to 0 to control the first buffer 911 not to output The digital output signal DATA_TX increases the output impedance of the transmission unit 91.

Although the conventional transmission unit 91 can take into account both the impedance and the driving force, it must rely on the digital circuit 94 to generate the enable signal BW_EN, which makes the digital circuit 94 more complicated in implementation, and There are often several sets of the number of the contacts 93 that the digital circuit 94 inputs and outputs to the outside, which also causes difficulty in layout and integration of the circuit. Therefore, providing a simpler transmission unit becomes an important issue.

Therefore, the object of the present invention is to provide a transmission unit with a simpler design.

Therefore, the transmission unit of the present invention is suitable for a digital circuit, a receiving unit, and a contact. The receiving unit is electrically connected to the contact and the digital circuit to connect the The potential change of the point is buffered and amplified and output as a digital input signal to the digital circuit. The transmission unit includes a first buffer, a second buffer, and a logic circuit.

The first buffer includes an input terminal electrically connected to the digital circuit to receive a digital output signal, an output terminal electrically connected to the contact, and an enable terminal receiving a gate output signal. When the logic value of the gate output signal is equal to a first logic value, the first buffer buffer-amplifies the digital output signal from the input terminal to the output terminal. When the logic value of the gate output signal is equal to a second logic value, the first buffer does not buffer and amplify the digital output signal from the input terminal to the output terminal.

The second buffer includes an input terminal electrically connected to the digital circuit to receive the digital output signal, and an output terminal electrically connected to the contact, and buffers and amplifies the digital output signal from the input terminal to the output terminal.

The logic circuit includes a first input terminal electrically connected to the digital circuit to receive the digital output signal, a second input terminal electrically connected to the receiving unit to receive the digital input signal, and a gate output to output the gate output signal end. When the logic circuit determines that the logic values of the digital output signal and the digital input signal are different, the gate output signal with a logic value equal to the first logic value is generated. When the logic circuit judges that the digital output signal and the digital input signal have the same logic value, the gate output signal having a logic value equal to the second logic value is generated.

In some embodiments, the logic circuit is an exclusive OR (XOR) gate.

In some embodiments, the driving force of the first buffer is greater than the second buffer.

In some embodiments, the first logic value is logic 1, and the second logic value is logic 0.

The effect of the present invention lies in: the logic circuit determines the change of the logic value between the digital output signal and the digital input signal, so that when the digital output signal passes through the second buffer, the contact, and the receiving unit When it becomes the digital input signal after delay, it can detect the change of the logical value of the digital output signal in the two adjacent data, and change the logical value of the gate output signal to control the output of the first buffer, and then realize A low-power transmission unit with a simpler design.

1‧‧‧Transmission unit

11‧‧‧First buffer

12‧‧‧Second buffer

13‧‧‧Logic circuit

2‧‧‧Receiving unit

3‧‧‧Contact

9‧‧‧Digital circuit

91‧‧‧Transmission unit

911‧‧‧First buffer

912‧‧‧Second buffer

92‧‧‧Receiving unit

93‧‧‧Contact

94‧‧‧ digital circuit

PAD‧‧‧contact signal

XOR‧‧‧Gate output signal

DATA_TX‧‧‧Digital output signal

DATA_RX‧‧‧Digital input signal

BW_EN‧‧‧Enable signal

Other features and functions of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: FIG. 1 is a block diagram illustrating a conventional transmission unit; FIG. 2 is a timing diagram to assist the description of FIG. 1 FIG. 3 is a block diagram illustrating an embodiment of the transmission unit of the present invention; and FIG. 4 is a timing diagram to assist FIG. 3 in explaining that the embodiment has more signals during transmission. The relationship between the signals.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same number.

Referring to FIG. 3, an embodiment of the transmission unit 1 of the present invention is applicable to a digital circuit 9, a receiving unit 2, and a contact 3, and includes a first buffer 11, a second buffer 12, and a Logic circuit 13.

The digital circuit 9, the transmitting unit 1, the receiving unit 2, and the contact 3 are part of a chip or integrated circuit (IC), and the chip may also include other contacts 3 or other circuits, But not limited to this. The contact 3 is a pad of a chip package (PAD), which is used for electrical connection with the input and output pins of the chip to transmit and receive signals with other electronic devices outside the chip. Both the transmission unit 1 and the reception unit 2 conform to a Mobile Industry Processor Interface (MIPI), that is to say, the transmission unit 1 is a low power transmitter (Low Power Transmitter; LP_TX), and Provide fast enough slew rate and rising / falling time to take into account both low power consumption and high output impedance.

The receiving unit 2 is electrically connected to the contact 3 and the digital circuit 9 to buffer and amplify the potential change of the contact 3 to output a digital input signal DATA_RX to the digital circuit 9.

The first buffer 11 includes an input terminal electrically connected to the digital circuit 9 to receive a digital output signal DATA_TX, an output terminal electrically connected to the contact 3, and an enable terminal receiving a gate output signal XOR. When the logic value of the gate output signal XOR is equal to a first logic value, the first buffer 11 buffer-amplifies the digital output signal DATA_TX at the input terminal to the output terminal. When the logic value of the gate output signal XOR is equal to a second logic value, the first buffer 11 does not buffer and amplify the digital output signal DATA_TX from the input terminal to the output terminal.

The second buffer 12 includes an input terminal electrically connected to the digital circuit 9 to receive the digital output signal DATA_TX, and an output terminal electrically connected to the contact 3, and amplifies the digital output signal DATA_TX of the input terminal to The output.

The logic circuit 13 includes a first input terminal electrically connected to the digital circuit 9 to receive the digital output signal DATA_TX, a second input terminal electrically connected to the receiving unit 2 to receive the digital input signal DATA_RX, and an output of the gate The gate output terminal of the output signal XOR. When the logic circuit 13 determines that the logic values of the digital output signal DATA_TX and the digital input signal DATA_RX are different, the gate output signal XOR with a logic value equal to the first logic value is generated. When the logic circuit 13 determines that the digital output signal DATA_TX and the digital input signal DATA_RX have the same logic value, the gate output signal XOR having a logic value equal to the second logic value is generated.

In this embodiment, the logic circuit 13 is an exclusive OR (Exclusive OR; XOR) gate, and the driving force of the first buffer 11 is greater than that of the second buffer 12, The first logic value is logic 1, and the second logic value is logic 0, but not limited to this.

3 and 4, FIG. 4 is a timing diagram, and FIG. 3 is an auxiliary diagram illustrating the relationship between multiple signals when the transmission unit 1 outputs the digital output signal DATA_TX to the contact 3, where the horizontal axis represents time , The vertical axis represents the change in potential, such as logic 1 and logic 0, and the contact signal PAD represents the change in potential at this contact 3.

When the digital circuit 9 is to output data, the digital output signal DATA_TX is generated, and the digital output signal DATA_TX becomes the digital input through the second buffer 12, the contact 3, and the time delay of the receiving unit 2 Signal DATA_RX. When the data output by the digital circuit 9 is two different before and after, that is, one is logic 0 and the other is logic 1, the gate output signal XOR generated by the logic circuit (mutually exclusive or gate) 13 is equal to logic 1, and then control the first buffer 11 to output the digital output signal DATA_TX to the contact 3, and can help the potential transition on the contact 3, such as from logic 0 to logic 1 or from logic 1 to Logic 0. Conversely, when the data output by the digital circuit 9 are the same before and after, that is, both are logic 0 or logic 1, the gate output signal XOR generated by the logic circuit (mutually exclusive or gate) 13 is equal to logic 0 In order to control the first buffer 11 not to output the digital output signal DATA_TX to the contact 3, the output impedance of the transmission unit 1 can be increased.

In summary, the logic circuit 13 determines the logic value change between the digital output signal DATA_TX and the digital input signal DATA_RX, so that when the digital output signal DATA_TX passes through the second buffer 12, the contact 3, The When the time of the receiving unit 2 becomes the digital input signal DATA_RX, it can detect the change of the logical value of the digital output signal DATA_TX in the adjacent two data, and change the logical value of the gate output signal XOR to control the The output of the first buffer 11 can not only realize a low-power transmission unit 1 with a simpler design, but also reduce the area and cost of the entire integrated circuit, so it can indeed achieve the purpose of cost invention.

However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.

Claims (4)

A transmission unit is suitable for a digital circuit, a receiving unit, and a contact. The receiving unit is electrically connected to the contact and the digital circuit to buffer and amplify the potential change of the contact and output it as a digital input signal to In the digital circuit, the transmission unit includes: a first buffer including an input terminal electrically connected to the digital circuit to receive a digital output signal, an output terminal electrically connected to the contact, and an output terminal receiving a gate output signal On the enable terminal, when the logic value of the gate output signal is equal to a first logic value, the first buffer amplifies the digital output signal of the input terminal to the output terminal, when the logic value of the gate output signal is equal to one At the second logic value, the first buffer does not buffer and amplify the digital output signal at the input end to the output end; a second buffer includes an input end electrically connected to the digital circuit to receive the digital output signal, And an output terminal electrically connected to the contact, and buffering and amplifying the digital output signal of the input terminal to the output terminal; and a logic circuit including an electrical connection to the digital circuit A first input terminal receiving the digital output signal, a second input terminal electrically connected to the receiving unit to receive the digital input signal, and a gate output terminal outputting the gate output signal, when the logic circuit judges the digital output When the logical values of the signal and the digital input signal are different, the gate output signal with a logical value equal to the first logical value is generated, and when the logical circuit determines that the logical values of the digital output signal and the digital input signal are the same, the logical value is generated The gate output signal equal to the second logic value. The transmission unit according to claim 1, wherein the logic circuit is an exclusive OR (XOR) gate. The transfer unit according to claim 2, wherein the driving force of the first buffer is greater than the second buffer. The transmission unit according to claim 3, wherein the first logical value is a logical 1 and the second logical value is a logical 0.