JP5513862B2 - Microcomputer failure analysis system - Google Patents

Description

  The present invention relates to a failure analysis system for a microcomputer.

  Semiconductor devices are shipped through strict quality control and strict inspection for each manufacturing process, but there are rare cases where defects that have been hidden after passing the inspection and appearing on the market become apparent. This is called a market claim product, and manufacturers are struggling to deal with the problem because the market is required to clarify the cause and prevent recurrence.

  The market complaint product is returned to the manufacturer for failure analysis. Failure analysis is defined by JIS (Japanese Industrial Standards) as “a systematic research study to examine the mechanism / incidence of an item's potential or actual failure and the effect of the failure and determine the corrective action”. And its area is extensive. The present invention contributes to the part belonging to the initial nondestructive analysis.

  Information obtained by non-destructive analysis is used as a clue to identify the location of the defect and investigate the cause in the subsequent physical analysis, and finally, the manufacturer reflects the measures to prevent recurrence in the design, process, manufacturing process, and inspection process. It will be possible to provide a more reliable product by fulfilling the responsibility for these requirements.

  A failure analysis using an LSI (Large Scale Integrated Circuit) tester is performed on the market complaint item returned to the manufacturer. In the initial failure analysis, it is indispensable to reproduce the defect on the LSI tester, but there are many problems that cannot be reproduced unless a combination of many conditions and a complicated communication protocol are given, and it is extremely difficult to reproduce the defect using the LSI tester. There is a case.

  For example, an LSI tester gives a test vector from an external pin of a semiconductor device, and determines whether it is good or bad by comparing the behavior that appears on the external pin through an internal circuit with an expected value. The test vectors that can be given to the semiconductor device by the LSI tester are limited, and if the test vector runs out before the operation failure that occurs inside the semiconductor device appears at the external terminal observed by the LSI tester, the failure cannot be reproduced. .

  Conventionally, a failure analysis using an actual machine has been attempted for a failure that cannot be reproduced by an LSI tester as described above. The actual machine here refers to a final product itself in which a market claim product is incorporated, or a printed circuit board constituting the product, and is provided from a customer who purchased a semiconductor device.

  The actual machine is an environment itself that includes a factor that causes the failure of the incorporated semiconductor device, and by analyzing input / output between the actual machine and the semiconductor device, the conditions under which the failure of the semiconductor device can be clarified. It is also possible to change the various conditions to pursue the cause of the failure. However, knowledge, experience and insight are required and skill is required to analogize which part of the circuit of the semiconductor device has a defect from the behavior of these actual machines and obtain clues for subsequent physical analysis.

  Although analysis using a real machine has been performed conventionally, there is no example of using the real machine as a part of the analysis device. The following Patent Documents 1 to 4 describe a method for selecting a defective product by comparing the behavior with a non-defective product.

  In order to inspect and sort semiconductor devices, various methods and configurations have been devised for an apparatus that sifts out defective products by comparing behavior with non-defective products.

  Further, in Patent Document 5, terminal signal information of a microcomputer to be analyzed is operated using a target system (corresponding to a customer's actual machine in the present invention), temporarily stored in a workstation, and thereafter in the workstation. A failure analysis system and failure analysis method for a logic LSI that reproduces terminal signal information given to a microcomputer and gives it to a normal microcomputer or emulator as an input signal is disclosed.

JP-A-2-95280 JP 2002-365342 A Japanese Patent No. 3569154 JP-A-4-12490 JP 2004-101203 A

  In the failure analysis using the conventional LSI tester, there is a problem in the reproducibility of the failure. In addition, there is a problem that the analysis using the actual machine and the measuring instrument depends on the skill of the operator and requires time for the analysis. Furthermore, the technique described in the above-mentioned prior patent document is intended to determine whether the semiconductor device is good or bad, and it is impossible to obtain information until it is specified under what conditions a failure inherent in the semiconductor device occurs. Remains.

  Further, the invention described in Patent Document 5 requires a mechanism for “reproducing terminal signal information applied to a microcomputer” (for example, a terminal digital IO (input output: input / output) board in FIG. 12), and the system configuration is complicated. In addition, a mechanism for storing a time axis and an analog value (for example, recorded analog trace data and an analog IO board in FIG. 36) is required for an analog input signal, and the system configuration is complicated and the cost is increased. There was a problem.

  An object of the present invention is to enable reliable reproduction of a failure / failure in a semiconductor device having a malfunction in a failure analysis of a microcomputer, and which part of a circuit built in the semiconductor device has a problem. It is an object of the present invention to provide a microcomputer failure analysis system capable of analyzing the above as a system that is inexpensive and can be quickly constructed.

  A microcomputer failure analysis system according to the present invention includes a substrate on which a microcomputer is mounted, and a signal output means for supplying an input signal to the microcomputer and a circuit means for performing a predetermined operation based on an output signal from the microcomputer; Connected to the signal extracting means for extracting the input signal and the output signal to the outside of the substrate from the foot pattern on the substrate from which the mounted microcomputer is removed, and the signal extracting means for extracting the input signal and the output signal In order to operate the microcomputer and a malfunctioning microcomputer, a non-defective microcomputer, or an in-circuit emulator of the microcomputer, a predetermined number of clocks are supplied according to instructions from a host computer. A clock control means for supplying black computer, characterized by comprising a signal storage means for storing the level of said input signal and said output signal in synchronization with the clock.

  The microcomputer failure analysis system of the present invention further connects the failed product and the signal extraction means for extracting the input signal and the output signal, and the clock control means supplies the predetermined number of clocks. The signal storage means stores the input signal and the output signal, and the host computer dumps and stores the stored contents of the signal storage means in the host computer. With the input signal and the signal extraction means for extracting the output signal connected, the clock control means supplies the predetermined number of clocks, and the signal storage means stores the input signal and the output signal. The host computer dumps the stored contents of the signal storage means and stores them in the host computer. To.

  In the microcomputer failure analysis system of the present invention, the host computer further operates the failed product by comparing the level of the output signal of the failed product and the non-defective product stored in the host computer for each clock. The number of clocks that become abnormal is detected, and the in-circuit emulator is connected to the signal extraction means for extracting the input signal and the output signal. The clock is supplied up to the number of clocks causing the abnormal operation, and the program location corresponding to the occurrence of the abnormal operation is detected by the debugging function of the in-circuit emulator.

The microcomputer failure analysis system according to the present invention includes a substrate on which a microcomputer is mounted, and which includes signal output means for supplying an input signal to the microcomputer and circuit means for performing a predetermined operation based on the output signal from the microcomputer. And a signal extraction means for extracting the input signal and the output signal to the outside of the substrate from the foot pattern on the substrate from which the mounted microcomputer is removed, and the signal extraction means for extracting the input signal and the output signal. In order to operate the microcomputer, and a predetermined number of clocks in order to operate the microcomputer, the defective microcomputer or the non-defective microcomputer or the in-circuit emulator of the microcomputer connected to the microcomputer A clock control unit supplies the serial microcomputer,
Signal storage means for storing levels of the input signal and the output signal in synchronization with the clock; and current measurement means for measuring a current value of the microcomputer in synchronization with the clock. To do.

  The microcomputer failure analysis system of the present invention further connects the failed product and the signal extraction means for extracting the input signal and the output signal, and the clock control means supplies the predetermined number of clocks. The signal storage means stores the input signal and the output signal, and the host computer dumps the storage contents of the signal storage means and a current value synchronized with the clock and accumulates them in the host computer, Next, in a state where the non-defective product is connected to the signal extraction unit that extracts the input signal and the output signal, the clock control unit supplies the predetermined number of clocks, and the signal storage unit The host computer stores the signal and the output signal, and the host computer synchronizes the stored contents of the signal storage means and the clock. Dump the values, characterized in that accumulate within the host computer.

  In the microcomputer failure analysis system of the present invention, the host computer further operates the failed product by comparing the level of the output signal of the failed product and the non-defective product stored in the host computer for each clock. The number of clocks that become abnormal is detected, and the in-circuit emulator is connected to the signal extracting means for extracting the input signal and the output signal. The clock is supplied up to the number of clocks causing the operation abnormality or the number of clocks where the faulty product causes the current abnormality, and the program location corresponding to the occurrence of the operation abnormality or current abnormality is detected by the debug function of the in-circuit emulator. It is characterized by that.

The microcomputer failure analysis system according to the present invention includes a substrate on which a microcomputer is mounted, and which includes signal output means for supplying an input signal to the microcomputer and circuit means for performing a predetermined operation based on the output signal from the microcomputer. And a signal extraction means for extracting the input signal and the output signal to the outside of the substrate from the foot pattern on the substrate from which the mounted microcomputer is removed, and the signal extraction means for extracting the input signal and the output signal. In order to operate the microcomputer, and a predetermined number of clocks in order to operate the microcomputer, the defective microcomputer or the non-defective microcomputer or the in-circuit emulator of the microcomputer connected to the microcomputer A clock control unit supplies the serial microcomputer,
Current measuring means for measuring a current value of the microcomputer in synchronization with the clock.

  The microcomputer failure analysis system of the present invention further connects the failed product and the signal extraction means for extracting the input signal and the output signal, and the clock control means supplies the predetermined number of clocks, The host computer dumps and accumulates a current value synchronized with the clock in the host computer, and then connects the non-defective product and the signal extraction means for extracting the input signal and the output signal, and A predetermined number of clocks are supplied, and the host computer dumps and stores a current value synchronized with the clock in the host computer.

  In the microcomputer failure analysis system of the present invention, the host computer further compares the current values of the failed product and the non-defective product stored in the host computer for each clock, so that the failed product has a current abnormality. The clock control means detects the number and connects the in-circuit emulator and the signal extraction means for extracting the input signal and the output signal. The clock is supplied up to the number of clocks, and the program location corresponding to the occurrence of the current abnormality is detected by the debugging function of the in-circuit emulator.

  According to the present invention, since the occurrence of a malfunction of a faulty product can be identified by comparing with a good product of a microcomputer, it is not necessary to prepare an expected value, and the efficiency of failure analysis can be improved.

  In addition, according to the present invention, since an operation abnormality or current abnormality due to a malfunction of the microcomputer can be compared and detected on the host PC, the timing at which the operation abnormality or current abnormality occurs is known by counting the operation clock, and the analysis target The time range can be narrowed down.

  Furthermore, according to the present invention, when an ICE (In Circuit Emulator) is used, internal information such as a program counter and a register in the microcomputer can be read by the debug function of the ICE when an abnormal operation is detected. Therefore, it is possible to easily estimate the execution instruction that causes the abnormality.

  As described above, according to the present invention, failure analysis of a microcomputer can be performed at low cost and failure location can be estimated without using a large-scale facility such as an LSI tester.

1 is a configuration diagram of a microcomputer failure analysis system according to a first embodiment of the present invention. FIG. 2 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the first embodiment of the present invention. FIG. 3 is a flowchart of the failure analysis operation by the microcomputer failure analysis system according to the first embodiment of the present invention. FIG. 4 is a configuration diagram of the microcomputer failure analysis system according to the second embodiment of the present invention. FIG. 5 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the second embodiment of the present invention. FIG. 6 is a flowchart of a failure analysis operation by the microcomputer failure analysis system according to the second embodiment of the present invention. FIG. 7 is a configuration diagram of the microcomputer failure analysis system according to the third embodiment of the present invention. FIG. 8 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the third embodiment of the present invention. FIG. 9 is a flowchart of the failure analysis operation by the microcomputer failure analysis system according to the third embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 is an overall configuration diagram of a microcomputer failure analysis system according to a first embodiment of the present invention. In FIG. 1, 1 is a board of a customer's actual machine, 2 is a signal extracting means, 3 is a base board, 4 is a utility board, and 5 is a host PC (Personal Computer).

  An actual machine socket 11 is provided on the board 1 of the actual customer machine, and a distributor 21 and a connector 22 are connected to the signal extracting means 2. The base board 3 is equipped with a sample mounting socket 31 and a current measurement terminal 33 for a device under test (DUT) on which a defective product, a non-defective product, and an ICE (In Circuit Emulator) connector are mounted. Are equipped with an FPGA (Field Programmable Gate Array) 41 and a log storage memory 42. The ICE USB (Universal Serial Bus) terminal 32 of the base board 3 and the FPGA USB terminal 43 of the utility board 4 are connected to the USB terminal 51 of the host PC 5.

  The FPGA 41 of the utility board 4 controls input signals to the X1, XT1, and Reset terminals of the DUT, observes the terminal status of each terminal, buffers output from each terminal (data recording to the log storage memory 42), and the like. In addition to performing control, interface (I / F) control with the host PC 5 and counting / control of the number of clocks are performed.

  Further, the host PC 5 performs interface (I / F) control with the FPGA 41, graphing of the acquired log (log), and ICE control (using a debugger).

  FIG. 2 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the first embodiment of the present invention. In FIG. 2, when the microcomputer mounted on the board 1 of the actual customer machine fails, the faulty product 71 is removed from the socket 11 of the board 1 of the actual customer machine. The socket 11 of the board 1 of the customer's actual machine and the sample mounting socket 31 of the base board 3 are connected by the signal extracting means 2, and the terminal state of the board 1 of the customer's actual machine is as follows: It is possible to transmit to the FPGA 41 on the utility board via.

  In the investigation of the failed product in the first stage, the failed product 71 removed from the socket 11 of the board 1 of the customer's actual machine is set in the sample mounting socket 31 of the base board 3 and the FPGA 41 of the utility board 4 is instructed by the host PC 5. However, a control signal is transmitted to the faulty product 71 for a predetermined number of clocks N, and the terminal status of each terminal output from the faulty product 71 is observed by the FPGA 41 and recorded in the log storage memory 42. The terminal state data for each number of clocks of the failed product 71 recorded in the log storage memory 42 is stored in the host PC 5 via the USB terminals 43 and 51.

  In the next second stage investigation of non-defective products, the defective product 71 is removed from the sample mounting socket 31 of the base board 3, and the non-defective product 72 is set in the sample mounting socket 31 of the base board 3. As in the first stage, the FPGA 41 of the utility board 4 transmits a control signal for a predetermined number of clocks N to the non-defective product 72 according to an instruction from the host PC 5, and each terminal output from the non-defective product 72 is transmitted by the FPGA 41. The terminal state is observed and recorded in the log storage memory 42. The terminal state data for each clock number of the non-defective product 72 recorded in the log storage memory 42 is accumulated in the host PC 5 via the USB terminals 43 and 51.

  Then, in the third-stage check of the defective product / non-defective product, the terminal state data at each clock number of the failed product 71 and the non-defective product 72 stored in the host PC 5 is compared. For example, if the data of the terminal states of the defective product 71 and the non-defective product 72 are different at the number of clocks M, it can be estimated that an error has occurred in the failed product 71 at the step corresponding to the clock number M.

  Next, in the fourth stage ICE survey, the non-defective product 72 is removed from the sample mounting socket 31 of the base board 3, and the socket of the ICE 73 is set in the sample mounting socket 31 of the base board 3. In this state, the failure occurrence clock number M is supplied to the ICE 73. The ICE 73 has a debugging function, can read a program counter value corresponding to the number of clocks M, and can analyze the execution instruction from the program counter value to estimate the cause of the failure.

  FIG. 3 is a flowchart of the failure analysis operation by the microcomputer failure analysis system according to the first embodiment of the present invention. In the flowchart of FIG. 3, first, when the investigation of the faulty product 71 is started in step S301, the faulty product 71 is set on the base board 3 in step S302. In step S303, N clocks are supplied to the faulty product 71. In step S304, the input / output signal levels of the faulty product 71 are stored in the host PC 5.

  Next, when the inspection of the non-defective product 72 is started in step S305, the non-defective product 72 is set on the base board 3 in step S306. In step S307, N clocks are supplied to the non-defective product 72. In step S308, the input / output signal levels of the non-defective product 72 are stored in the host PC 5.

  Thereafter, in step S309, the host PC compares the input / output signal levels of the defective product 71 and the non-defective product 72. In step S310, when a difference occurs in the input / output signal levels of the defective product 71 and the non-defective product 72 at the M-th clock (S310: Yes), the process proceeds to the investigation by ICE in step S311. If there is no difference between the input / output signal levels of the faulty product 71 and the non-defective product 72 (S310: No), the faulty product 71 is checked in step S312 and the non-defective product 72 is checked in step 313.

  When the investigation by ICE is started in step S311, the ICE 73 is set on the base board 3 in step S314. In step S315, the M clock corresponding to the failure is supplied to the ICE 73. In step S316, the program counter value of the Mth clock is read by ICE, and in step S317, the execution instruction is analyzed from the program counter value to estimate the cause of failure.

  FIG. 4 is a configuration diagram of the microcomputer failure analysis system according to the second embodiment of the present invention. In FIG. 4, 1 is a board of a customer's actual machine, 2 is a signal extracting means, 3 is a base board, 4 is a utility board, 5 is a host PC (Personal Computer), and 6 is a current measuring device.

  An actual machine socket 11 is provided on the board 1 of the actual customer machine, and a distributor 21 and a connector 22 are connected to the signal extracting means 2. The base board 3 is equipped with a sample mounting socket 31 and a current measurement terminal 33 for a device under test (DUT) on which a defective product, a non-defective product, and an ICE (In Circuit Emulator) connector are mounted. Are equipped with an FPGA (Field Programmable Gate Array) 41 and a log storage memory 42. The current measuring device 6 is connected to the current measuring terminal 33 of the base board 3. The ICE USB (Universal Serial Bus) terminal 32 of the base board 3 and the FPGA USB terminal 43 of the utility board 4 are connected to the USB terminal 51 of the host PC 5, and the current measuring device 6 is a current measuring USB terminal of the host PC 5. 52.

  The FPGA 41 of the utility board 4 controls input signals to the X1, XT1, and Reset terminals of the DUT, observes the terminal status of each terminal, buffers output from each terminal (data recording to the log storage memory 42), and the like. In addition to performing control, interface (I / F) control with the host PC 5 and counting / control of the number of clocks are performed.

  Further, the host PC 5 performs interface (I / F) control with the FPGA 41, graphs of the acquired log (log) or acquired current value, and ICE control (using a debugger).

  FIG. 5 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the second embodiment of the present invention. Similarly to the first embodiment, the faulty product 71, the non-defective product 72, and the ICE 73 are mounted on the sample mounting socket 31 of the base board 3, and the fault analysis of the microcomputer is executed.

  The difference from the first embodiment is that a log (log) storage memory 42 is mounted on the utility board 4 to store log data of input / output signal levels, and a failure is estimated by the difference of input / output signal levels. Not only that, the current measuring device 6 is connected to the current measuring terminal 33 of the base board 3, and the current value at each clock is also stored in the host PC 5, and the failure is determined by the data of both the input / output signal level and the current value. The failure analysis of the product 71 is performed.

  FIG. 6 is a flowchart of a failure analysis operation by the microcomputer failure analysis system according to the second embodiment of the present invention. In the flowchart of FIG. 6, first, when the investigation of the failed product 71 is started in step S601, the failed product 71 is set on the base board 3 in step S602. In step S603, N clocks are supplied to the faulty product 71. In step S604, the input / output signal level of the faulty product 71 and the current value for each clock are stored in the host PC 5.

  Next, when the inspection of the non-defective product 72 is started in step S605, the non-defective product 72 is set on the base board 3 in step S606. In step S607, N clocks are supplied to the non-defective product 72. In step S608, the input / output signal level of the non-defective product 72 and the current value for each clock are stored in the host PC 5.

  After that, in step S609, the host PC compares the input / output signal levels of the failed product 71 and the non-defective product 72 with current values. In step S610, when a difference occurs in the input / output signal level between the defective product 71 and the non-defective product 72 at the M-th clock (S610: Yes), or the current value of the failed product 71 is larger than that of the non-defective product 72 (S610: Yes). ), The process proceeds to the investigation by ICE in step S611. If there is no difference in the input / output signal level between the faulty product 71 and the non-defective product 72 (S610: No) or no difference in the current value (S610: No), the investigation of the faulty product 71 in step S612, step In 613, the non-defective product 72 is investigated.

  When the investigation by ICE is started in step S611, the ICE 73 is set on the base board 3 in step S614. In step S615, the M clock corresponding to the failure is supplied to the ICE 73. In step S616, the MCE clock program counter value is read by ICE, and in step S617, an execution instruction is analyzed from the program counter value to estimate the cause of the failure.

  FIG. 7 is a configuration diagram of the microcomputer failure analysis system according to the third embodiment of the present invention. In FIG. 7, reference numeral 1 denotes a customer's actual machine board, 2 denotes a signal extracting means, 3 denotes a base board, 4 denotes a utility board, 5 denotes a host PC (Personal Computer), and 6 denotes a current measuring device.

  An actual machine socket 11 is provided on the board 1 of the actual customer machine, and a distributor 21 and a connector 22 are connected to the signal extracting means 2. The base board 3 is equipped with a sample mounting socket 31 and a current measurement terminal 33 for a device under test (DUT) on which a defective product, a non-defective product, and an ICE (In Circuit Emulator) connector are mounted. Is equipped with an FPGA (Field Programmable Gate Array) 41. The current measuring device 6 is connected to the current measuring terminal 33 of the base board 3. The ICE USB (Universal Serial Bus) terminal 32 of the base board 3 and the FPGA USB terminal 43 of the utility board 4 are connected to the USB terminal 51 of the host PC 5, and the current measuring device 6 is a current measuring USB of the host PC 5. The terminal 52 is connected.

  The FPGA 41 of the utility board 4 controls input signals to the X1, XT1, and Reset terminals of the DUT, controls the terminal state of each terminal, and controls the interface (I / F) with the host PC 5 and the number of clocks. Count and control.

  Further, the host PC 5 performs interface (I / F) control with the FPGA 41, graphing of the acquired current value, and ICE control (using a debugger).

  FIG. 8 is a diagram showing each stage of the operation of the microcomputer failure analysis system according to the third embodiment of the present invention. Similarly to the first embodiment, the faulty product 71, the non-defective product 72, and the ICE 73 are mounted on the sample mounting socket 31 of the base board 3, and the fault analysis of the microcomputer is executed.

  The difference from the first and second embodiments is that, in the third embodiment, the utility board 4 is not equipped with the log storage memory 42, and the current measuring device 6 is connected to the current measuring terminal 33 of the base board 3. The current value at the clock is accumulated in the host PC 5 and the failure analysis of the failed product 71 is performed based on the current value data.

  FIG. 9 is a flowchart of the failure analysis operation by the microcomputer failure analysis system according to the third embodiment of the present invention. In the flowchart of FIG. 9, first, when the investigation of the defective product 71 is started in step S901, the defective product 71 is set on the base board 3 in step S902. In step S903, N clocks are supplied to the faulty product 71. In step S904, the current value for each clock of the faulty product 71 is stored in the host PC 5.

  Next, when the inspection of the non-defective product 72 is started in step S905, the non-defective product 72 is set on the base board 3 in step S906. In step S907, N clocks are supplied to the non-defective product 72. In step S908, the current value for each clock of the good product 72 is stored in the host PC 5.

  Thereafter, in step S909, the current values of the defective product 71 and the non-defective product 72 are compared on the host PC. In step S910, when the current value of the faulty product 71 becomes larger than that of the non-defective product 72 at the M-th clock (S910: Yes), the process proceeds to the investigation by ICE in step S911. If there is no difference between the current values of the faulty product 71 and the non-defective product 72 (S910: No), the faulty product 71 is checked in step S912, and the non-defective product 72 is checked in step 913.

  When the investigation by ICE is started in step S911, the ICE 73 is set on the base board 3 in step S914. In step S915, the M clock corresponding to the failure is supplied to the ICE 73. In step S916, the MCE program counter value is read by ICE, and in step S917, an execution instruction is analyzed from the program counter value to estimate the cause of failure.

1 Board of customer's machine 2 Signal extraction means 3 Base board 4 Utility board 5 Host PC
6 Current measurement device 11 Actual socket 21 Distributor 22 Connector 31 Sample mounting socket 32 ICE USB terminal 33 Current measurement terminal 41 FPGA
42 Log storage memory 43 USB terminal for FPGA 51 USB terminal 52 USB terminal for current measurement 71 Faulty product 72 Non-defective product 73 ICE

Claims (9)

A board on which a microcomputer is mounted, and a signal output means for supplying an input signal to the microcomputer and a circuit means for performing a predetermined operation based on an output signal from the microcomputer;
A signal extraction means for extracting the input signal and the output signal from the foot pattern on the substrate from which the mounted microcomputer is removed;
A faulty product of the microcomputer or a non-defective product of the microcomputer or an in-circuit emulator of the microcomputer connected to the signal extraction means for extracting the input signal and the output signal;
Clock control means for supplying a predetermined number of clocks to the microcomputer according to instructions from a host computer in order to operate the microcomputer;
A microcomputer failure analysis system comprising: signal storage means for storing levels of the input signal and the output signal in synchronization with the clock. The microcomputer failure analysis system according to claim 1,
The faulty product is connected to the signal extraction means for extracting the input signal and the output signal, the clock control means supplies the predetermined number of clocks, and the signal storage means includes the input signal and the input signal. The output signal is stored, and the host computer dumps and stores the storage contents of the signal storage means in the host computer,
Next, in a state where the non-defective product is connected to the signal extraction unit that extracts the input signal and the output signal, the clock control unit supplies the predetermined number of clocks, and the signal storage unit A microcomputer failure analysis system for storing a signal and the output signal, wherein the host computer dumps and stores the storage contents of the signal storage means in the host computer. The microcomputer failure analysis system according to claim 2,
The host computer detects the number of clocks at which the faulty product becomes abnormal by comparing the level of the output signal of the faulty product and the non-defective product stored in the host computer for each clock,
The in-circuit emulator is connected to the signal extraction means for extracting the input signal and the output signal, and according to an instruction from the host computer, the clock control means supplies a clock up to the number of clocks at which the failed product becomes abnormal in operation. A microcomputer failure analysis system, wherein the program location corresponding to the occurrence of the abnormal operation is detected by a debugging function of the in-circuit emulator. A board on which a microcomputer is mounted, and a signal output means for supplying an input signal to the microcomputer and a circuit means for performing a predetermined operation based on an output signal from the microcomputer;
A signal extraction means for extracting the input signal and the output signal from the foot pattern on the substrate from which the mounted microcomputer is removed;
A faulty product of the microcomputer or a non-defective product of the microcomputer or an in-circuit emulator of the microcomputer connected to the signal extraction means for extracting the input signal and the output signal;
Clock control means for supplying a predetermined number of clocks to the microcomputer according to instructions from a host computer in order to operate the microcomputer;
Signal storage means for storing levels of the input signal and the output signal in synchronization with the clock; and current measurement means for measuring a current value of the microcomputer in synchronization with the clock. A microcomputer failure analysis system. The microcomputer failure analysis system according to claim 4,
The faulty product is connected to the signal extraction means for extracting the input signal and the output signal, the clock control means supplies the predetermined number of clocks, and the signal storage means includes the input signal and the input signal. The output signal is stored, and the host computer dumps and stores the current value synchronized with the stored contents of the signal storage means and the clock in the host computer,
Next, in a state where the non-defective product is connected to the signal extraction unit that extracts the input signal and the output signal, the clock control unit supplies the predetermined number of clocks, and the signal storage unit A microcomputer failure analysis system for storing a signal and the output signal, wherein the host computer dumps and accumulates the storage contents of the signal storage means and the current value synchronized with the clock in the host computer . In the microcomputer failure analysis system according to claim 5,
The host computer compares the output signal level or current value of the failed product and the non-defective product stored in the host computer for each clock to determine the number of clocks at which the failed product becomes abnormal in operation or current. Detect
The clock control means connects the in-circuit emulator with the signal extraction means for extracting the input signal and the output signal, and the clock control means, according to an instruction from the host computer, determines the number of clocks at which the failed product is abnormal or the failed product. A microcomputer failure characterized by supplying clocks up to the number of clocks that cause current abnormality of and detecting a program location corresponding to the occurrence of the operation abnormality or current abnormality by the debug function of the in-circuit emulator Analysis system. A board on which a microcomputer is mounted, and a signal output means for supplying an input signal to the microcomputer and a circuit means for performing a predetermined operation based on an output signal from the microcomputer;
A signal extraction means for extracting the input signal and the output signal from the foot pattern on the substrate from which the mounted microcomputer is removed;
A faulty product of the microcomputer or a non-defective product of the microcomputer or an in-circuit emulator of the microcomputer connected to the signal extraction means for extracting the input signal and the output signal;
Clock control means for supplying a predetermined number of clocks to the microcomputer according to instructions from a host computer in order to operate the microcomputer;
A microcomputer failure analysis system comprising: current measuring means for measuring a current value of the microcomputer in synchronization with the clock. The microcomputer failure analysis system according to claim 7,
The faulty product is connected to the signal extraction means for extracting the input signal and the output signal, the clock control means supplies the predetermined number of clocks, and the host computer supplies a current value synchronized with the clock. Dump and accumulate,
Next, the non-defective product and the signal extracting means for extracting the input signal and the output signal are connected to supply the predetermined number of clocks, and the host computer supplies a current value synchronized with the clock in the host computer. A microcomputer failure analysis system characterized by being dumped and stored. The microcomputer failure analysis system according to claim 8,
The host computer detects the number of clocks at which the faulty product has an abnormal current by comparing the current values of the faulty product and the non-defective product stored in the host computer for each clock.
The in-circuit emulator is connected to the signal extraction means for extracting the input signal and the output signal, and according to an instruction from the host computer, the clock control means supplies a clock up to the number of clocks that causes a current abnormality of the failed product. A microcomputer failure analysis system, wherein the program location corresponding to the occurrence of the current abnormality is detected by a debugging function of the in-circuit emulator.

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