JP2003289342A - Data control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data control circuit in which a throughput of a whole system is improved and increase in power consumption is suppressed. <P>SOLUTION: Serial data RXDAT under inputting this time are time sequentially compared with serial data RXDAT inputted the last time bit by bit for each mutually corresponding bit by a data comparator 50 and in accordance with the compared result, a flag presenting whether the serial data RXDAT inputted this time are the same data as the serial data RXDAT inputted the last time or not is stored in a flag storage part comprising a receiving buffer 20 corresponding to the serial data RXDAT inputted this time. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data control circuit to which serial data is input and stored in a reception buffer. 2. Description of the Related Art In recent years, as represented by the spread of portable terminals, a low-cost and low-power-consumption wireless communication system has been demanded by the society, and at the same time, with the increase in communication speed, There is an increasing demand for high throughput as a system. Usually, when transmitting the same data from the main station to multiple substations simultaneously,
The broadcast packet is transmitted a plurality of times in order to improve the probability that data is transmitted to the receiving side. The receiving side is provided with a data control circuit for inputting data (serial data) from the transmitting side and storing the data in a receiving buffer. This data control circuit transmits the data a plurality of times if the transfer state is not bad. Receive. Further, the software on the receiving side, which has been notified of the arrival of the received data from the data control circuit, accesses the hardware on the receiving side in order to receive the received data. For example, when 400 bytes of received data is accessed (read access) using a data bus having a data width of 16 bits (2 bytes), a simple calculation is performed.
Reading is performed 0 times / 2 bytes = 200 times. [0003] As described above, when reading out 400 bytes of received data on a data bus having a data width of 16 bits, the receiving side needs to perform 200 times of reading. If this is repeated multiple times, (2
(00 times × multiple times) read access occurs. However, in the case of the same data, there is a high possibility that data other than the first data is discarded.
Most of the read accesses (0 times x multiple times) (first 1
Are often wasted, and there is a problem in that the throughput of the entire system decreases and power consumption increases. In view of the above circumstances, an object of the present invention is to provide a data control circuit in which the throughput of the entire system is increased and the increase in power consumption is suppressed. A data control circuit according to the present invention for achieving the above object is a data control circuit for receiving serial data and storing the received serial data in a reception buffer. A data comparator that compares the input serial data one bit at a time for each bit corresponding to each other, and, according to the comparison result by the data comparator, sets the serial data input this time to the same data as the serial data input last time. And a flag storage unit for storing a flag indicating whether or not the data is serial data inputted this time. In a wireless communication system capable of having a plurality of communication partners at the same time, when transmission of the same data is repeated a plurality of times, if the same data is received a plurality of times on the receiving side, the same as the normal data. It is received and a receiving process is performed. Normally, the same data is rarely repeated. However, when transmitting the same data to a plurality of other parties at the same time, such as broadcast data, the same data is transmitted a plurality of times in order to prevent loss of communication data. Sometimes.
When this is received, the process for reading the same data is repeated many times on the receiving side, which may reduce the throughput of the data processing. The data control circuit according to the present invention stores a flag indicating whether or not the serial data input this time is the same as the serial data input last time, in association with the serial data input this time. Therefore, useless reading can be prevented in advance by referring to the flag. Therefore, the processing speed of the received data in the entire system is improved, the throughput is increased, and the increase in power consumption is suppressed. An embodiment of the present invention will be described below. FIG. 1 is a block diagram of a data control circuit according to one embodiment of the present invention. The data control circuit 1 shown in FIG.
Para conversion register unit 10, reception buffer 20, same data reception flag switch 30, data selection unit 40
, A data comparator 50, and a control circuit 60. Serial-parallel conversion register section 10, data comparator 5
0, and the control circuit 60 has serial data RXDA
T is input. The data comparator 50 receives the system clock SYSCLK, and the control circuit 60 receives the reception clock RXCLK. First, the serial-parallel conversion register unit 10 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the serial-parallel conversion register unit shown in FIG. The serial-parallel conversion register unit 10 shown in FIG.
, Receives serial data RXDAT of n + 1 bits per packet, converts the input serial data RXDAT of n + 1 bits into parallel data RXDAT [0],..., RXDAT [n−1], RXD of n + 1 bits
This is a circuit for converting to DAT [n]. The serial-parallel conversion register section 10 includes:
AND gates 11_0,..., 11_n-1, 11_n
, 12_n−1, 12_n
, 13_n−1, 1
3_n. AND gate 11_0,
, 11_n-1, 11_n are connected to one input terminal, respectively.
The load signal LOAD from the control circuit 60 is input.
Also, AND gates 11_0,..., 11_n−1, 11
_N have the count values 0,..., N−
Received data count signal RXDCOUNT having 1, n
T is input. Here, the reception data count signal RX
DCOUNT is a signal which is output from the control circuit 60 and indicates the bit number of the received data (serial data RXDAT) at present, and the count value 0,.
1, n correspond to bits (the first bit is assumed to be LSB) 0,..., N−1, n that constitute the serial data RXDAT. The serial-parallel conversion register unit 10 sets the serial data RXDAT in a flip-flop corresponding to a bit constituting the serial data RXDAT at the same time as the start of reception of the input serial data RXDAT. First, the serial data RXDAT
In order to set the first bit (LSB) of the received data, control circuit 60 outputs received data count signal RXDCOUNT having count value 0. Then
The load signal LOAD is set (logic 1). Then, data RXDAT [0] corresponding to the first bit constituting the serial data RXDAT is output to the selector 12_
0, and is stored in the flip-flop 13_0.
Similarly, data RXD corresponding to n-1 bits
AT [n-1] is stored in flip-flop 13_n-1 via selector 12_n-1, and data RXDAT [n] corresponding to n bits is stored in flip-flop 13_n via selector 12_n. Reception is completed. , 13_n-
Data RXDAT [0] stored in 1,13_n,
, [N-1], [n] are input to the reception buffer 20 and the data selection unit 40. Next, the reception buffer 20 and the same data reception flag switch 30 will be described with reference to FIG. FIG. 3 is a diagram showing the configuration of the reception buffer and the same data reception flag switch shown in FIG. The reception buffer 20 shown in FIG. 3 has three stages of reception buffer units 21 each having an n + 1 bit configuration.
_0, 21_1, 21_2
1 and the reception buffer sections 21_0, 21_1, 21
_2, the same data reception flag units 22_0, 22_1, 22_ each having a 1-bit configuration and provided corresponding to
2 is provided. The flag storage unit 22 stores the serial data RXDA input this time according to the comparison result by the data comparator 50 described later.
The same data reception flag indicating whether or not T is the same data as the serial data RXDAT previously input is
It is stored in association with the serial data RXDAT input this time. The same data reception flag switch 30
Receives the externally-received reception data switching signal SEL, and sets the same data reception flag corresponding to the data stored in any of the three-stage reception buffers 21_0, 21_1, 21_2 constituting the reception data storage 21. Select and output to the data bus. Here, when outputting the same data reception flag to the data bus, the same data reception flag is read from the outside via the data bus as 1-bit data constituting the interrupt status (interrupt status reading method). ). By doing so, the CPU
Only requires the normal operation of reading the interrupt status in response to the occurrence of an interrupt due to the arrival of the received data. Therefore, no new hardware access is added, and the useless read operation of the same data is avoided. The processing efficiency of the CPU is increased. FIG. 4 is a diagram showing the data select unit shown in FIG. The data selector 40 shown in FIG. 4 has input terminals 0,..., N−1, n to which data RXDAT [0],. The data selection unit 40 has a switching terminal to which a received data count signal RXDCOUNT having count values 0,..., N−1, n (described as received data count signals RXDCOUNT0 to n) is input. The data select unit 40 receives the serial data RXDA currently being input.
In order to compare T with the previously input serial data RXDAT one bit at a time for each corresponding bit, the data RXDAT [0],... n
-1] and [n], the reception data count signal RX
By sequentially selecting DCOUNT0 to DCOUNTn, bits corresponding to the serial data RXDAT currently being input are extracted. As a result, the previous data OLDRXDAT representing the bit corresponding to the serial data RXDAT currently being input is output. FIG. 5 is a diagram showing a configuration of the data comparator shown in FIG. The data comparator 50 shown in FIG. 5 includes the serial data RXDAT currently input and the serial data RXDAT (data OLDRXDA) input last time.
T) is a comparator that compares one bit in time series with each other for each bit corresponding to each other. This data comparator 50 includes an exclusive OR gate 51, an AND gate 52, an OR gate 53, and a flip-flop 54. Provided. The exclusive OR gate 51 sequentially receives the data OLDRXDAT corresponding to the previously input serial data RXDAT and the serial data RXDAT currently being input, and outputs the output to one input of the AND gate 52. . Also,
The other input of the AND gate 52 has a load signal LOA
D is input, and its output is input to one input of the OR gate 53. The output of the OR gate 53 is input to the data input terminal of the flip-flop 54. Further, the flip-flop 54 has a system clock SY
SCLK and a reception start signal RXSTART are input. The reception start signal RXSTART is a signal output from the control circuit 60 and set to logic 0 when reception is started. Hereinafter, the operation of the data comparator 50 will be described with reference to FIG. FIG. 6 is a timing chart of the data comparator shown in FIG. The exclusive OR gate 51 outputs a logical 0 when the levels of the input data OLDRXDAT and RXDAT are the same (the same bit), and outputs a logical 1 when the levels are different. The load signal LOAD input to the AND gate 52 becomes logic 1 at the timing when the reception data RXDAT is sampled by the flip-flop of the serial-parallel conversion register unit 10. Further, the reception start signal RXSTART input to the flip-flop 54 changes from logic 1 to logic 0 when the reception is started, and immediately changes to logic 1 so that the output terminals Q and Q_ of the flip-flop 54 are changed. Output a logic 0 and a logic 1, respectively. Here, the data OLDR input to the exclusive OR gate 51 is
If the levels of XDAT and RXDAT are different (bits do not match), a logical 1 is input to the input terminal 0 of the AND gate 52, and the logical 1 is the logical value of the received data RXD
AT is taken into the flip-flop 54 at the rising edge of the system clock SYSCLK at the same timing as when the AT is taken into the flip-flop. This is the load signal L
It is controlled by OAD. Therefore, logic 1 and logic 0 are output from the output terminals Q and Q_ of the flip-flop 54. On the other hand, if both bits of the data OLDRXDAT and RXDAT match, a logic 0 is input to the input terminal 0 of the AND gate 52, and this logic 0 is taken into the flip-flop 54 at the rising edge of the system clock SYSCLK. And the flip-flop 54
Logic 0 and Logic 1 are output from the output terminals Q and Q_ of.
As described above, if both bits of the data OLDRXDAT and RXDAT input to the exclusive OR gate 51 match, the logic 0 and the logic 1 are output from the output terminals Q and Q_ of the flip-flop 54. If there is no match even once, flip-flop 5
The four output terminals Q and Q_ become logic 1 and logic 0, respectively. Therefore, the data match signal DA at the time when all the bits of the serial data RXDAT are input and converted into parallel.
T_EQ means the result of all-bit comparison between the current packet and the previous packet. That is, the data match signal DA
If T_EQ is logical 1, the two packets match, and if logical 0, the packets do not match. This logic 1 data match signal DAT_EQ
Is stored in the flag storage unit 22 constituting the reception buffer 20 as the same data reception flag in association with the serial data RXDAT input this time when the reception completion signal is input to the reception buffer 20 described above. Is done. As described above, the data control circuit 1 of the present embodiment is provided with the data comparator 50 at the point where the serial reception data RXDAT is first taken in, and compares the serial reception data RXDAT received last time with each bit. To determine whether they match or not, and when all bits match, generates a data match signal DAT_EQ (identical data reception flag) of logic 1. Also, the reception buffer 20
And a flag storage unit 22 for storing the same data reception flag.
When the reception data is written to the reception buffer 20 when the reception of one packet is completed, the flag storage unit 2
2 stores the same data reception flag of logical 1 if they match and logical 0 if they do not match. By doing so, when reading the received data, the software first checks the same data reception flag, and determines whether or not to subsequently read the data. Access can be omitted. For example, if 400 bytes of received data is 16
When reading using the data bus of byte data width,
Conventionally, interrupt status readout was required multiple times and received data readout was required (200 times x multiple times).
If the above-described interrupt status reading method is adopted, the calculation is such that the reading of the interrupt status is performed a plurality of times and the reading of the received data is performed only once. Therefore, in the data control circuit 1 according to the present embodiment, it is possible to reduce the frequency of hardware access when reading data received a plurality of times, and to improve the throughput for receiving the same data continuously. , And prevention of an increase in power consumption. Further, the data control circuit 1 of the present embodiment
This is a so-called successive approximation type circuit configuration in which the serial data RXDAT being input this time and the serial data RXDAT input last time are compared one bit at a time in a bit sequence corresponding to each other, so that the circuit configuration is simplified. Is done. As described above, according to the present invention,
It is possible to provide a data control circuit in which the throughput of the entire system is increased and an increase in power consumption is suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a data control circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a serial-parallel conversion register unit shown in FIG. 1; FIG. 3 is a diagram showing a configuration of a reception buffer and an identical data reception flag switch shown in FIG. 1; FIG. 4 is a diagram showing a data select unit shown in FIG. 1; FIG. 5 is a diagram showing a configuration of a data comparator shown in FIG. FIG. 6 is a timing chart of the data comparator shown in FIG. [Description of Signs] 1 Data control circuit 10 Serial-parallel conversion register unit 20 Receive buffer 30 Same data reception flag switch 40 Data select unit 50 Data comparator 60 Control circuits 11_0,..., 11_n-1, 11_n, 52 AND gate 12_0, ..., 12_n-1, 12_n selectors 13_0, ..., 13_n-1, 13_n, 54 flip-flops 21 received data storage units 21_0, 21_1, 21_2 reception buffer units 22 flag storage units 22_0, 22_1, 22_2 identical data reception flag units 51 Exclusive OR gate 53 OR gate

Claims (1)

Claims: 1. A data control circuit that receives serial data and stores the received serial data in a reception buffer, wherein the serial data being input this time and the serial data input last time are one bit for each bit corresponding to each other. And a flag indicating whether or not the serial data input this time is the same as the serial data input last time, according to the comparison result by the data comparator. A data control circuit, comprising: a flag storage unit that stores the data in association with serial data.