JP2003282560A - Ferroelectric layer and manufacturing method, and ferroelectric capacitor and piezoelectric device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a ferroelectric layer for improving surface morphology where the surface morphology is improved, a ferroelectric memory device and a piezoelectric device where the ferroelectric layer is applied. <P>SOLUTION: The manufacturing method of the ferroelectric layer comprises steps of (a) forming a ferroelectric film 20, and (b) forming an embedded insulating film 30 on the ferroelectric film 20. The step (b) includes a step of stacking a raw material liquid layer 32 on the ferroelectric film 20 by turning raw material liquid for the embedded insulating film into mist. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric layer, a method of manufacturing the same, a ferroelectric capacitor and a piezoelectric element.

[0002]

BACKGROUND ART At present, as a ferroelectric film applied to a semiconductor device (for example, a ferroelectric memory (FeRAM)), a ferroelectric film having a layered perovskite structure (for example, B
iLaTiO-based, BiTiO-based, SrBiTaO-based) have been proposed. The ferroelectric film having the layered perovskite structure is generally formed by forming a raw material layer of the ferroelectric film and then performing heat treatment to grow crystals.

By the way, when a ferroelectric film having, for example, a layered perovskite structure is formed by this forming method, the ferroelectric film has a crystal growth rate in the c-axis direction due to the crystal structure. Slower than the directional crystal growth rate. That is, crystals are easily grown in the a and b axis directions. Therefore, according to the above forming method, the ferroelectric film having the layered perovskite structure has a rough surface morphology.
That is, a recess is formed on the upper surface of the ferroelectric film. Even when the ferroelectric film is made of PZT, although not as much as the ferroelectric having the layered perovskite structure,
Recesses occur.

As a method for filling the concave portion, a technique has been proposed in which a sol solution or a solution for MOD (Metal Organic Decomposition) method is applied by a spin coating method and baked (JP-A-6-32613).

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a ferroelectric layer, which can improve surface morphology.

Another object of the present invention is to provide a ferroelectric layer having improved surface morphology.

Another object of the present invention is to provide a ferroelectric capacitor and a piezoelectric element to which the ferroelectric layer of the present invention is applied.

[0008]

[Means for Solving the Problems] 1. Method for Manufacturing Ferroelectric Layer In the method for manufacturing a ferroelectric layer of the present invention, (a) a step of forming a ferroelectric film, (b) a step of forming an embedded insulating film on the ferroelectric film. And the step (b) includes a step of forming a raw material liquid for the buried insulating film into a mist and depositing it on the ferroelectric film.

According to the method of manufacturing the ferroelectric layer of the present invention,
The raw material liquid for the buried insulating film is deposited in a mistaken form. For this reason, the raw material liquid easily enters the concave portion on the upper surface of the ferroelectric film. Therefore, according to the ferroelectric layer of the present invention, it is possible to reliably fill the raw material liquid into the recess.

By forming a buried insulating film on the ferroelectric film, the surface morphology of the ferroelectric layer can be improved.

The step (b) may include a step of heat-treating the raw material liquid to form a buried insulating film.

In the step (b), the raw material liquid is
It can be deposited by the LSMCD method. LSMC
According to the method D, the raw material liquid can be filled in the recess more reliably.

The raw material liquid is a sol-gel liquid or M
It can be an OD solution.

The embedded insulating film may be made of a ferroelectric material. Thereby, the ferroelectricity of the ferroelectric layer can be more surely exhibited.

The particle size of the mist of the raw material liquid is 10
It can be set to nm to 1 μm. When the particle size is in this range, it is possible to reliably fill the raw material liquid in the concave portion of the ferroelectric layer.

The embedded insulating film may be provided only in the concave portion on the upper surface of the ferroelectric film.

2. Ferroelectric Layer The ferroelectric layer of the present invention includes a ferroelectric film and an embedded insulating film provided only in the concave portion on the upper surface of the ferroelectric film.

3. Ferroelectric capacitor The ferroelectric capacitor of the present invention includes a first electrode, a ferroelectric layer of the present invention, and a second electrode, and the ferroelectric layer is
It is provided at least between the first electrode and the second electrode.

4. Piezoelectric element The piezoelectric element of the present invention includes the ferroelectric layer of the present invention.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION 1. 1. Method of Manufacturing Ferroelectric Layer 1.1 Process FIGS. 1 to 3 are cross-sectional views schematically showing the steps of forming the ferroelectric layer.

First, the ferroelectric film 20 is formed on the substrate 10. Examples of the material of the ferroelectric film 20 include layered perovskite (for example, SBT, BLT), PZT.
Furthermore, those obtained by adding a metal such as niobium, nickel, or magnesium to these materials can be applied. The ferroelectric film 20 may be formed by, for example, a spin coating method using a sol-gel material or a MOD material, a dipping method, a sputtering method, an LSMCD method, an MOC.
The VD method and the laser ablation method can be mentioned.

The ferroelectric film 20 generally has a recess 22 formed on the upper surface thereof as shown in FIG. The recess 22 is particularly prominent when the ferroelectric film 20 is made of a layered perovskite ferroelectric.

Next, as shown in FIG. 3, a buried insulating film 30 is formed on the ferroelectric film 20. In particular,
The embedded insulating film 30 is formed as follows.

As shown in FIG. 2, a raw material liquid for the buried insulating film 30 is misted on the ferroelectric film 20 to deposit a raw material liquid layer 32. The method for depositing the raw material liquid is not particularly limited as long as it can be introduced into the raw material liquid in the form of a mist, and examples thereof include the LSMCD method. Examples of the raw material liquid include a sol-gel liquid and a MOD liquid. The sol-gel liquid may be a liquid containing a carboxylate. As a MOD liquid,
A liquid containing a polynuclear metal complex in which the constituent elements of the buried insulating film to be obtained are continuously connected directly or indirectly to each other can be mentioned.

The thickness of the raw material liquid layer 32 is, for example, 1 to 20.
can be nm. The particle size of the mist of the raw material liquid may be 10 nm to 1 μm.

Specific examples of the sol-gel liquid and the MOD liquid are determined by the material of the buried insulating film 30 to be obtained. The material of the buried insulating film 30 is not particularly limited as long as it has an insulating property, and for example, SBT, BL
Examples thereof include T and PZT. The material of the embedded insulating film 30 is preferably a ferroelectric material. Further, the material of the embedded insulating film 30 and the material of the ferroelectric film 20 can be the same.

Then, as shown in FIG. 3, the raw material liquid layer 32 is formed.
The embedded insulating film 32 can be formed by heat-treating.

As the heat treatment method, for example, RTA is used.
(Rapid Thermal Annealing) and FA (furnace) may be used for annealing in an oxygen atmosphere. More specifically, RTA is used to anneal for a short time to purify the microcrystalline nuclei. Then, the buried insulating film 30 can be formed by promoting crystallization using FA. In this way, the ferroelectric layer 100 can be formed.

As shown in FIG. 4, the buried insulating film 30 may be formed only in the recess 22. In this case, the buried insulating film 3 is formed by depositing the raw material liquid layer only on the concave portion 22 of the ferroelectric film 20 as shown in FIG.
0 can be formed only in the recess 22.

1.2 Operational Effects The operational effects of the method for manufacturing a ferroelectric layer according to this embodiment will be described below.

(1) According to the present embodiment, the embedded insulating film 30 is formed on the ferroelectric film 20. Therefore, the surface morphology of the ferroelectric layer can be improved. Further, as described later in Examples, by forming the buried insulating film 30, it is possible to prevent dielectric breakdown when the ferroelectric layer 100 is applied to a ferroelectric capacitor.

(2) According to the technique disclosed in JP-A-6-32613 (see background art), a sol solution or MO is used.
It is difficult to fill the minute recesses of the ferroelectric film with the solution for the D method due to the problem of surface tension. For this reason, a cavity is generated in the recess. In addition, the coating by the spin coating method has a problem that the uniformity of the film thickness on the wafer surface is not good and the reproducibility of the film thickness between wafers or between lots is poor.

However, according to the present embodiment, the raw material liquid for the buried insulating film 30 is deposited in the form of mist. Therefore, it is possible to reliably fill the concave portion 22 with the raw material liquid by reducing the size of the mist. Moreover, since the thickness of the raw material liquid layer can be controlled by the deposition time, controllability is improved. Further, the uniformity of the thickness within the wafer surface is improved, and the reproducibility of the film thickness between wafers or between lots is improved.

2. Application Example The ferroelectric layer according to the present invention can be applied to, for example, the following ferroelectric memory device.

2.1 First Ferroelectric Memory Device FIG. 6 is a cross-sectional view schematically showing the first ferroelectric memory device.

The first ferroelectric memory device 200 includes a ferroelectric capacitor 210 and a selection transistor 220. The ferroelectric capacitor 210 is configured by sequentially stacking a lower electrode 212, a ferroelectric layer 214, and an upper electrode 216.

2.2 Second Ferroelectric Memory Device FIG. 7 is a plan view schematically showing the second ferroelectric memory device. FIG. 8 is a sectional view schematically showing a section of the second ferroelectric memory device.

The second ferroelectric memory device 300 is formed by arranging ferroelectric memory cells, which are composed of ferroelectric capacitors, in a matrix. Specifically, the second ferroelectric memory device 300 has a first signal electrode 312, a ferroelectric layer 314, and a second signal electrode 316. The first signal electrode (word line) 312 for row selection and the second signal electrode (bit line) 316 for column selection are arranged so as to be orthogonal to each other. That is, the first signal electrodes 312 are arranged at a predetermined pitch along the row direction, and the second signal electrodes 316 are arranged at a predetermined pitch along the column direction orthogonal to the row direction. As shown in FIG. 8, the ferroelectric layer 314 is provided with the ferroelectric layer 314 between the first signal electrode 312 and the second signal electrode 316.

The application example of the ferroelectric layer according to the present invention is not limited to the above ferroelectric memory device, but can be applied to a piezoelectric element.

[0040]

EXAMPLES Next, the present invention will be described in more detail with reference to examples. Incidentally, the present invention, unless it exceeds the gist,
The present invention is not limited to the examples below.

1. Method for Forming Ferroelectric Layer Hereinafter, a method for forming the ferroelectric layer will be described. In addition,
FIG. 9 shows a flow chart of the process for the ferroelectric layer.

First, an SBT film was formed. SBT film is
It was formed as follows.

The SBT raw material liquid was applied onto the substrate by the spin coating method to form an SBT precursor layer. In addition, S
The thickness of the BT precursor layer was 60 nm. Next, SBT
The precursor layer was baked to form microcrystal nuclei. This baking was performed at 260 ° C. for 4 minutes. Next, the SBT precursor layer was pre-baked. This calcination was performed for 40 seconds under the condition of temperature of 700 ° C. under oxygen atmosphere. S
A total of 2 cycles were carried out, with one cycle from the coating of the BT raw material liquid to the preliminary firing.

Then, the SBT precursor layer was fired. This main calcination was carried out in an oxygen atmosphere at a temperature of 700 ° C. for 1 hour. In this way, the SBT film was formed.

Next, a buried SBT film was formed on the SBT film. The embedded SBT film was formed as follows.

The SBT raw material liquid was made into mist, and the SBT raw material liquid layer was deposited on the SBT film. Specifically, SB
A raw material liquid layer of T was deposited by the LSMCD method. Then S
The raw material liquid layer of BT was baked. This bake is 260 ° C
I went there for 4 minutes. Next, the raw material liquid of SBT was pre-baked.
The calcination was performed in an oxygen atmosphere at a temperature of 700 ° C. for 40 seconds. Next, the SBT raw material liquid was subjected to main firing. This main calcination was performed for 1 hour in an oxygen atmosphere at a temperature of 700 ° C. As described above, the embedded SBT film was formed and the ferroelectric layer according to the example was formed.

Incidentally, a total of three types of ferroelectric layers according to the example were obtained. That is, the ferroelectric layer according to the first to third examples was obtained by changing the deposition amount of the raw material liquid of the embedded SBT film. The ferroelectric layer according to the first example was formed by supplying the SBT raw material liquid in an amount theoretically necessary for depositing the SBT raw material liquid layer having a thickness of 5 nm on the SBT film. Further, the ferroelectric layers according to the second and third examples are respectively
SB with a thickness of 10 nm or 20 nm on the SBT precursor layer
It was formed by supplying the SBT raw material liquid in an amount theoretically necessary to deposit the T raw material liquid layer. The amount of this SBT raw material liquid was controlled by time.

A ferroelectric layer made of only the SBT film without the embedded SBT film was used as a comparative example.

2. Surface Morphology Figures 10 to 13 show SEM (Scanning el
ectron microscope) Show photos. FIG. 10 is an SEM photograph of the ferroelectric layer according to the first example. FIG. 11 is an SEM photograph of the ferroelectric layer according to the second example. 12
4A is an SEM photograph of a ferroelectric layer according to a third example.
FIG. 13 is an SEM photograph of the ferroelectric layer according to the comparative example.

As shown in FIGS. 10 to 13, the embedded S
According to the first to third examples in which the BT film is formed, the degree of unevenness is significantly reduced and the surface morphology is improved as compared with the comparative example in which the embedded SBT film is not formed.

In addition, as shown in FIG.
It can be seen that the maximum height tends to decrease as the thickness of the T film increases. Therefore, also from this point, it is understood that the surface morphology is improved by forming the embedded SBT film. Here, the "maximum height" means that in FIG.
As shown in FIG. 5, among the adjacent convex portions S10 and concave portions S20 on the surface of the ferroelectric layer, the distance L10 between the apex of the convex portion S10 and the bottom of the concave portion S20 is the maximum distance. The “embedded SBT film thickness” on the horizontal axis is the amount of the supply of the SBT raw material liquid converted into the film thickness.

Further, as shown in FIG. 16, the embedded SB
It can be seen that the average roughness Ra decreases as the thickness of the T film increases. The average roughness Ra was derived by the following formula.

[0053]

[Equation 1]

3. Dielectric Breakdown FIG. 17 is a graph showing the relationship between the applied voltage and the leakage current when the ferroelectric layers according to the first to third examples and the ferroelectric layer according to the comparative example are applied to the ferroelectric capacitor. Is. The applied voltage mentioned here indicates a potential difference between the upper electrode 112 and the lower electrode 116 sandwiching the ferroelectric layer 114 as shown in FIG. 18, and the leakage current is between the upper electrode 112 and the lower electrode 116. The leak current between them is shown. In FIG. 17, the point where the leak current sharply rises is the voltage that causes dielectric breakdown. The measurement temperature was 85 ° C.

As shown in FIG. 17, the voltages that cause dielectric breakdown in the first to third embodiments are higher on the positive voltage side than in the comparative example, and lower on the negative voltage side than in the comparative example. Therefore, according to the first to third examples, it is understood that the dielectric breakdown is less likely to occur as compared with the comparative example.

4. Hysteresis Characteristics FIG. 19 is a graph showing hysteresis characteristics when the ferroelectric layers according to the first to third examples are applied to the ferroelectric capacitors. 2Pr indicates the difference between the Pr value when the potential difference is 0V when the data 0 is written and the Pr value when the potential difference is 0V when the data 1 is written. The higher 2Pr,
It shows that the squareness of the hysteresis loop is excellent.
The horizontal axis represents the write voltage.

In the first embodiment, the write voltage is 1V.
2 Pr is 10 μC / cm²Exceeding the second embodiment
When the write voltage is 2 V or higher, 2 Pr is 10 μC /
cm ²And the write voltage is 3 in the third embodiment.
2Pr is 10 μC / cm above V²Is over. did
Therefore, according to the ferroelectric layer according to each example, an appropriate writing is performed.
By setting the imprint voltage, the specified hysteresis
The characteristics can be surely obtained. In addition, as shown in FIG.
As the embedded insulating film becomes thinner,
The 2Pr value is improving.

It should be noted that the present invention is not limited to the above-described embodiment, but various modifications can be made within the scope of the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically showing a step of forming a ferroelectric layer.

FIG. 2 is a cross-sectional view schematically showing a step of forming a ferroelectric layer.

FIG. 3 is a cross-sectional view schematically showing a step of forming a ferroelectric layer.

FIG. 4 is a cross-sectional view schematically showing a ferroelectric layer according to a modified example.

FIG. 5 is a sectional view schematically showing a step of forming a ferroelectric layer according to a modification.

FIG. 6 is a sectional view schematically showing a first ferroelectric memory device.

FIG. 7 is a plan view schematically showing a second ferroelectric memory device.

FIG. 8 is a cross-sectional view schematically showing a cross section of a second ferroelectric memory device.

FIG. 9 shows a process flow chart for a ferroelectric layer.

FIG. 10 is an SEM photograph of the ferroelectric layer according to the first example.

FIG. 11 is an SEM photograph of a ferroelectric layer according to a second example.

FIG. 12 is an SEM photograph of a ferroelectric layer according to a third example.

FIG. 13 is an SEM photograph of a ferroelectric layer according to a comparative example.

FIG. 14 is a graph showing the relationship between the hole-filling SBT film thickness and the maximum height of recesses in the ferroelectric layer.

FIG. 15 is a diagram for explaining the maximum height of the concave portion of the ferroelectric layer.

FIG. 16 is a graph showing the relationship between the hole-filling SBT film thickness and the average roughness.

FIG. 17 is a graph showing the relationship between applied voltage and leak current.

FIG. 18 is a graph showing a relationship between an applied voltage and a leak current when the ferroelectric layers according to the first to third examples and the ferroelectric layer according to the comparative example are applied to a ferroelectric capacitor. .

FIG. 19 is a graph showing the relationship between the write voltage and 2Pr.

[Explanation of symbols]

10 Base 20 Ferroelectric film 22 recess 30 Embedded insulating film 32 Raw material liquid layer 100 ferroelectric layer 200 First Ferroelectric Memory Device 210 Ferroelectric capacitor 212 Lower electrode 214 Ferroelectric layer 216 Upper electrode 220 selection transistor 300 Second ferroelectric memory device 312 First signal electrode 314 Ferroelectric layer 316 Second signal electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) // H01L 27/105 C04B 35/00 J H01L 27/10 444C F term (reference) 4G030 AA09 AA13 AA16 AA21 AA43 BA09 BA10 CA08 GA09 GA10 GA35 5F058 BA20 BD01 BD05 BF27 BF80 BH03 BJ02 5F083 FR01 FR02 JA15 JA17 MA06 MA19 PR23 PR33 PR34

Claims (10)

[Claims] 1. (a) a step of forming a ferroelectric film,
(B) including a step of forming a buried insulating film on the ferroelectric film, wherein the step (b) mist forms a raw material liquid for the buried insulating film on the ferroelectric film. A method of manufacturing a ferroelectric layer, comprising the step of: 2. The method of manufacturing a ferroelectric layer according to claim 1, wherein the step (b) includes a step of heat-treating the raw material liquid to form a buried insulating film. 3. The method for manufacturing a ferroelectric layer according to claim 1, wherein in the step (b), the raw material liquid is deposited by the LSMCD method. 4. The method for manufacturing a ferroelectric layer according to claim 1, wherein the raw material liquid is a sol-gel liquid or a MOD liquid. 5. The method for manufacturing a ferroelectric layer according to claim 1, wherein the embedded insulating film is made of a ferroelectric material. 6. The method for manufacturing a ferroelectric layer according to claim 1, wherein the particle size of the mist of the raw material liquid is 1 μm or less. 7. The method of manufacturing a ferroelectric layer according to claim 1, wherein the embedded insulating film is provided only in a recess on the upper surface of the ferroelectric film. 8. A ferroelectric layer including a ferroelectric film and an embedded insulating film provided only in a recess on the upper surface of the ferroelectric film. 9. A first electrode, a ferroelectric layer according to claim 8, and a second electrode, wherein the ferroelectric layer is at least the first electrode and the second electrode.
A ferroelectric capacitor provided between the electrodes. 10. A ferroelectric layer according to claim 8, comprising
Piezoelectric element.