JP4825373B2 - Ferroelectric thin film manufacturing method and ferroelectric memory manufacturing method using the same - Google Patents

Ferroelectric thin film manufacturing method and ferroelectric memory manufacturing method using the same Download PDF

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JP4825373B2
JP4825373B2 JP2001246070A JP2001246070A JP4825373B2 JP 4825373 B2 JP4825373 B2 JP 4825373B2 JP 2001246070 A JP2001246070 A JP 2001246070A JP 2001246070 A JP2001246070 A JP 2001246070A JP 4825373 B2 JP4825373 B2 JP 4825373B2
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敬和 藤森
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Description

【０００１】
【発明の属する技術分野】
本発明は強誘電体薄膜の形成方法および強誘電体メモリの製造方法に係り、特に強誘電体薄膜の結晶性の向上に関する。
【０００２】
【従来の技術】
現在研究されている強誘電体メモリは大きく２つに分けられる。1つは、強誘電体キャパシタの反転電荷量を検出する方式で、強誘電体キャパシタと選択トランジスタとで構成される。
【０００３】
もう１つは、強誘電体の自発分極による半導体の抵抗変化を検出する方式のメモリである。この方式の代表的なものが、ＭＦＳＦＥＴである。これはゲート絶縁膜に強誘電体を用いたＭＩＳ構造である。
【０００４】
いずれの構造の場合も、強誘電体の膜質がメモリ特性に大きな影響を及ぼすものであることがわかっている。
【０００５】
そこで強誘電体薄膜の結晶性を向上するためにいろいろな方法が提案されている。そのひとつにＴｉシード法と呼ばれるＰＺＴ薄膜の結晶化方法が提案されている。
【０００６】
この方法は図７に示すように、プラチナＰｔなどからなる下部電極８表面にスパッタリング法などにより膜厚２０ｎｍ程度のチタン超薄膜からなるシード層９Ｌを形成し、この上層にゾルゲル法によりＰＺＴ膜９Ｐを形成する。ここでは出発原料として、Pb(CH3COO)2・3H2O,Zr(t-OC4H9)4,Ti(i-OC3H7)4の混合溶液を用い、この混合溶液をスピンコートした後、１５０度で乾燥させ、ドライエアー雰囲気において４００度で３０分の仮焼成を行った。これを５回繰り返した後、Ｏ2の雰囲気中で、７００℃１分程度の結晶化アニール工程を経て超薄膜９Ｌからの結晶成長を生ぜしめる。
【０００７】
【発明が解決しようとする課題】
この方法では結晶化がはじまる場所が不定なので結晶粒径が制御できず、不均一な大きさの柱状結晶が形成されるため、特性にばらつきが大きく、特に微細化、高集積化に際しては充分な特性を得ることができないという問題があった。
【０００８】
また、ＰＺＴ膜にはならず、酸化チタン（ＴｉＯ2）層あるいはチタン酸鉛（ＰｂＴｉＯ3）層となる箇所もあり、良好な特性を得ることができないという問題があった。
【０００９】
また結晶化アニールに際し温度を７００℃程度の高温にしなければならなかったため、下地配線などの下地層に悪影響を与えるという問題もあった。
【００１０】
本発明は前記実情に鑑みてなされたもので、均一で結晶性の良好な強誘電体薄膜を提供することを目的とする。
【００１１】
【課題を解決するための手段】
そこで本発明では、強誘電体薄膜の形成に先立ち、下地を構成する基板表面に、Ｔｉ超微粒粉を含む溶液を塗布し、乾燥・焼成して、Ｔｉ超微粒粉を含むシード層を形成し、このシード層の上層に、強誘電体薄膜を形成し、このシード層を核として結晶化を行うようにしたことを特徴とする。
【００１２】
かかる構成によれば、超微粒粉の存在により、この超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好な強誘電体薄膜を得ることが可能となる。
また、本発明は、上記強誘電体薄膜の形成方法において、前記シード層を形成する工程は、前記Ｔｉ超微粒粉を界面活性剤及びαテルビオールと混合してなる混合液を塗布する工程を含むことを特徴とする。
また、本発明は、上記強誘電体薄膜の形成方法において、前記Ｔｉ超微粒粉の粒径は０．５ｎｍから２００ｎｍであることを特徴とする。
この超微粒粉は粒径０．５ｎｍから２００ｎｍ程度とするのが望ましく、さらに望ましくは粒径１ｎｍから５０ｎｍ程度とする。
また、本発明は、上記強誘電体薄膜の形成方法において、前記Ｔｉ超微粒粉の粒径は５ｎｍであり、前記界面活性剤の濃度は０．１ｗｔ％〜１０ｗｔ％であることを特徴とする。
【００１３】
ところで、超微粒粉が核になるには、ある程度の原子の数が必要であり、原子1個では核にならず、また０．１ｎｍ程度の原子よりは充分に大きいサイズであることが望ましい。一方、核が大きすぎると、核の中心はＴｉのままで残ってしまう。したがってＴｉを残さないためには高いアニール温度が必要である。また、２００ｎｍを越えると平坦で均一な強誘電体薄膜の形成が不可能となる。また核が大きくなると、溶媒中に分散しにくくなるという不都合がある。
さらにまたこの濃度は、０．００００１ｗｔ％（０．１ｗｔｐｐｍ）から１ｗｔ％程度とするのが望ましい。
【００１４】
また望ましくは、下地を構成する基板表面に、シードとなるチタン超微粒粉を含むシード層を形成する工程と、前記シード層の上層に、ＰＺＴ薄膜を形成する工程とを含むことを特徴とする。
【００１５】
かかる構成によれば、直径５ｎｍ程度のチタン超微粒粉の存在により、このチタン超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好なＰＺＴ強誘電体薄膜を得ることが可能となる。
【００１６】
望ましくは、前記シード層を形成する工程は、チタン超微粒粉を含む溶液を塗布する工程と、乾燥・焼成する工程とを含むことを特徴とする。
【００１７】
かかる構成によれば、容易かつ均一にチタン超微粒粉を配置することが可能となる。
【００１８】
望ましくは、前記ＰＺＴ薄膜を形成する工程はスパッタリング工程を含むことを特徴とする。
【００１９】
望ましくは、さらに結晶化のためのアニール工程を含むことを特徴とする。
【００２０】
かかる構成によれば、４５０℃程度と従来よりも低温下での結晶成長が可能となるため、後続の電極形成あるいは絶縁膜の形成工程などにおける加熱工程で結晶化を行うことも可能であるが、結晶化のためのアニール工程を導入することにより、容易に結晶性の良好な強誘電体薄膜を形成することが可能となる。
【００２１】
また、以下は、本発明の参考例である。 また、本発明の方法によれば、前記シード層を形成する工程は、下地を構成する基板表面に、強誘電体薄膜の構成元素の少なくとも１種を含む超微粒粉を含む強誘電体薄膜塗布液を塗布する工程と、焼成工程とを含むことを特徴とする。
【００２２】
かかる構成によれば、超微粒粉を含む薄膜を形成しているため、この超微粒粉から良好に結晶化が進み、均一で信頼性の高い薄膜形成が可能となる。
【００２３】
望ましくは、下地を構成する基板表面に、シードとなるチタン超微粒粉を含むＰＺＴ塗布液を塗布する工程と、焼成工程とを含むことを特徴とする。
【００２４】
かかる構成によれば、強誘電体薄膜全体に均一に分散された、粒径５ｎｍ程度のチタン超微粒粉からなる、シードから結晶成長が始まる。従って、このチタン超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好なＰＺＴ強誘電体薄膜を得ることが可能となる。
【００２５】
望ましくは、さらに結晶化のためのアニール工程を含むことを特徴とする。
【００２６】
かかる構成によれば、４５０℃程度と従来よりも低温下での結晶成長が可能となるため、後続の電極形成あるいは絶縁膜の形成工程などにおける加熱工程で結晶化を行うことも可能であるが、結晶化のためのアニール工程を導入することにより、容易に結晶性の良好な強誘電体薄膜を形成することが可能となる。
【００２７】
さらにまた、本発明では、ＭＦＭＩＳ構造のＦＥＴからなる強誘電体メモリの製造方法において、強誘電体薄膜の形成に先立ち、フローティングゲート表面に、Ｔｉ超微粒粉および前記強誘電体薄膜の構成元素を含む溶液を塗布し、乾燥・焼成して、前記Ｔｉ超微粒粉を含むシード層を形成しておくようにし、この超微粒粉を核として結晶成長を行うようにしたことを特徴とする。
また、本発明は、上記強誘電体メモリの製造方法において、前記シード層を形成する工程は、前記Ｔｉ超微粒粉を界面活性剤及びαテルピオネールと混合してなる混合液を塗布する工程を含むことを特徴とする。
【００２８】
かかる構成によれば、直径５ｎｍ程度の超微粒粉の存在により、この超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好な強誘電体薄膜を得ることが可能となり、信頼性の高い強誘電体メモリの形成が可能となる。
【００２９】
また、以下は、本発明の参考例である。
本発明の参考例では、ＭＦＭＩＳ構造のＦＥＴからなる強誘電体メモリの製造方法において、前記強誘電体膜の形成工程が、下地を構成する基板表面に、強誘電体薄膜の構成元素の少なくとも１種を含む超微粒粉を含む強誘電体薄膜塗布液を塗布し、強誘電体薄膜を形成し、これを結晶化するようにしている。
【００３０】
かかる構成によれば、強誘電体薄膜全体に均一に分散されたシードから結晶成長が始まるため、均一な強誘電体薄膜を得ることができ、微細化に際しても信頼性の高い強誘電体メモリを形成することが可能となる。
【００３１】
本発明の参考例によれば、スイッチングトランジスタと強誘電体キャパシタとからなる強誘電体メモリの製造方法であって、前記強誘電体キャパシタの強誘電体薄膜を、第１の電極表面に、強誘電体薄膜の構成元素の少なくとも１種を含む超微粒粉を含む強誘電体薄膜塗布液を塗布し、これを結晶化することによって強誘電体薄膜を形成することを特徴とする。
【００３２】
かかる構成によれば、強誘電体薄膜全体に均一に分散されたシードから結晶成長が始まるため、均一な強誘電体薄膜を得ることができ、微細化に際しても信頼性の高い強誘電体メモリを形成することが可能となる。
【００３３】
本発明の参考例によれば、スイッチングトランジスタと強誘電体キャパシタとからなる強誘電体メモリの製造方法であって、前記強誘電体キャパシタの強誘電体薄膜を、第１の電極表面に、強誘電体薄膜の構成元素の少なくとも１種を含む超微粒粉を含む強シード層を形成し、このシード層の上層に、強誘電体薄膜を形成し、これを結晶化することによって粒径のそろった結晶からなる強誘電体薄膜を形成することを特徴とする。
【００３４】
かかる構成によれば、直径５ｎｍ程度の超微粒粉の存在により、この超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好な強誘電体薄膜を得ることが可能となり、信頼性の高い強誘電体メモリの形成が可能となる。
【００３５】
【発明の実施の形態】
本発明に係る強誘電体メモリおよびその製造方法の一実施形態について図面を参照しつつ詳細に説明する。
実施形態１
次に、本発明の第１の実施形態として、ＰＺＴを誘電体膜として用いた強誘電体キャパシタを用いた強誘電体メモリについて説明する。図１に、この強誘電体メモリの完成図、図２（ａ）乃至（ｅ）にその製造工程図を示す。この強誘電体メモリは、シリコン基板１内に形成されたスイッチングトランジスタとしてのＭＯＳＦＥＴのソース・ドレイン領域２、３の一方とプラグ７を介して下部電極８ａ、８ｂが接続するように、基板表面を覆う絶縁膜６上に強誘電体キャパシタを形成してなる強誘電体メモリ（ＦＲＡＭ）に関するもので、この強誘電体キャパシタの強誘電体薄膜９の結晶性を均一にしたことを特徴とするものである。ここで５はゲート絶縁膜４を介して基板表面に形成されたゲート電極である。強誘電体薄膜９は下部電極表面にチタン超微粒粉を含むシード層を形成しておき、このチタン超微粒粉から結晶成長を生ぜしめるようにして形成された、結晶粒径の均一な結晶からなることを特徴とする。
【００３６】
すなわち図１に示すように、高濃度にドープされた多結晶シリコン層からなるプラグ７とイリジウム８ａおよび酸化イリジウム８ｂとの２層膜からなる下部電極８と、下部電極８上に、チタン超微粒粉からなるシード層Ｓを核とする結晶成長により、結晶性の均一な強誘電体薄膜９（図３参照）と、さらにその上層に酸化イリジウムとイリジウムとの２層膜からなる上部電極１０とを形成したことを特徴とする。
【００３７】
次に、この強誘電体メモリの製造工程について説明する。
まず、ＬＯＣＯＳ法で形成された素子分離絶縁膜１Ｓで形成された素子領域内にＭＯＳＦＥＴ（図示せず）の形成されたシリコン基板１の表面を熱酸化し、膜厚６００ｎｍ程度の酸化シリコン層からなる絶縁膜６を形成した後、この絶縁膜６にコンタクトホールＨを形成する。そして、図２（ａ）に示すように、このコンタクトホール内に高濃度にドープされた多結晶シリコン層を埋め込み、プラグ７を形成した後、基板表面全体にスパッタリング法により膜厚２００ｎｍ程度のイリジウム層８ａを形成し、さらにこの表面を酸化し酸化イリジウム層８ｂとする。
【００３８】
続いてこれをフォトリソグラフィにパターニングし、下部電極８を形成する。
【００３９】
こののち、図２（ｂ）に示すように、粒径５ｎｍ程度のＴｉ超微粒粉を０．１ｗｔ％乃至１０ｗｔ％の界面活性剤およびαテルピオネールと混合して混合液を塗布する。このようにして表面にＴｉ超微粒粉Ｓを有するシード層が形成される。
【００４０】
この後、ゾルゲル法によって、強誘電体膜９を形成するためのＰＺＴ膜９Ｐを形成する。出発原料として、Pb(CH3COO)2・3H2O,Zr(t-OC4H9)4,Ti(i-OC3H7)4の混合溶液を用いた。この混合溶液をスピンコートした後、１５０℃で乾燥させ、ドライエアー雰囲気において４００℃で３０分の仮焼成を行った。これを５回繰り返した。
【００４１】
この後、図２（ｄ）に示すように、Ｏ2の雰囲気中で、４５０℃１分の熱処理を施した。
このようにして、図２（ｅ）に示すように、２５０nmの強誘電体膜１０を形成した。なお、ここでは、PbZrxTi1-xO3において、ｘを０．５２として（以下ＰＺＴ（５２／４８）と表す）、ＰＺＴ膜を形成している。
【００４２】
さらに、強誘電体膜９の上に、スパッタリングにより酸化イリジウムとイリジウムとの積層膜を形成する。この酸化イリジウム層とイリジウム層との積層膜を、上部電極１０とする。ここでは、イリジウム層と酸化イリジウム層とをあわせて２００nmの厚さとなるように形成した。このようにして、強誘電体キャパシタを得る。
【００４３】
かかる構成によれば、超微粒粉の存在により、図３に説明図を示すようにこの超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好な強誘電体薄膜を得ることが可能となる。
【００４４】
なおこの超微粒粉は粒径０．５ｎｍから２００ｎｍ程度とするのが望ましく、さらに望ましくは粒径１ｎｍから５０ｎｍ程度とする。
ところで、超微粒粉が核になるには、ある程度の原子の数が必要であり、原子1個では核にならず、また０．１ｎｍ程度の原子よりは充分に大きいサイズであることが望ましい。一方、核が大きすぎると、核の中心はＴｉのままで残ってしまう。したがってＴｉを残さないためには高いアニール温度が必要である。また、２００ｎｍを越えると平坦で均一な強誘電体薄膜の形成が不可能となる。また核が大きくなると、溶媒中に分散しにくくなるという不都合がある。
【００４５】
さらにまたこの濃度は、０．００００１ｗｔ％（０．１ｗｔｐｐｍ）から１ｗｔ％程度とするのが望ましい。このシード層の形成はＴｉ超微粒粉の周囲を界面活性剤で被覆し、これに、αテルピオネール等の有機溶剤を混合したものを用いたが、有機溶剤としてはこのほかキシレン、トルエン、２メトキシエタノール、ブタノール等を用いることも可能である。
【００４６】
また望ましくは、シード層を形成するに際し、チタン超微粒粉を含む溶液を塗布し、こののち、乾燥・焼成するようにしている。
【００４７】
かかる構成によれば、容易かつ均一にチタン超微粒粉を配置することが可能となる。
【００４８】
また、前記ＰＺＴ薄膜を形成する工程はゾルゲル法の他スパッタリング法によってよい。
【００４９】
また望ましくは、さらに結晶化のためのアニール工程を含むことを特徴とする。
【００５０】
かかる構成によれば、４５０℃程度と従来よりも低温下での結晶成長が可能となるため、後続の電極形成あるいは絶縁膜の形成工程などにおける加熱工程で結晶化を行うことも可能であるが、結晶化のためのアニール工程を導入することにより、容易に結晶性の良好な強誘電体薄膜を形成することが可能となる。
【００５１】
本発明の第１の実施形態として、ＰＺＴを強誘電体薄膜を用いた強誘電体メモリについて説明したが、このほかＳＴＮを誘電体膜として用いた強誘電体メモリなど他の材料を用いた場合にも適用可能であることはいうまでもない。
【００５２】
参考例
次に、参考例としてのＭＦＭＩＳ構造の強誘電体メモリの製造工程について説明する。図４は本発明の方法で形成された強誘電体メモリを示す図、図５（ａ）乃至（ｅ）は製造工程図である。
【００５３】
この例では、ＭＦＭＩＳ構造の強誘電体メモリの強誘電体薄膜１６の形成をＴｉ超微粒粉を含むゾルゲル液を塗布し、焼成した後、結晶化アニールを行うことにより、均一で結晶性の高い強誘電体薄膜１６を形成したことを特徴とするものである。
【００５４】
すなわち、シリコン基板１表面に形成されたソースおよびドレイン領域２，３と、これらの間にゲート絶縁膜４を介して形成されたフローティングゲート１５と、フローティングゲート１５上に形成された強誘電体薄膜１６とこの強誘電体薄膜１６上に形成されたコントロールゲート１７とから構成されている。
【００５５】
製造に際しては、まず、図５（ａ）に示すようにｎ型シリコン基板１の表面を熱酸化し、膜厚２０ｎｍ程度の酸化シリコン層４を形成した後、この酸化シリコン層４上にイリジウムをターゲットとして用いてスパッタリング法により、フローティングゲート１５となるイリジウム層を形成する。次に、Ｏ2の雰囲気中で８００度（摂氏、以下同じ）１分の熱処理を行い、イリジウム層の表面に酸化イリジウム層を形成する。
【００５６】
次に、このフローティングゲート１５の上に、図５（ｂ）に示すようにゾルゲル法によって、強誘電体膜１６としてＰＺＴ膜を形成する。出発原料として、粒径５ｎｍのチタン超微粒子を０．５ｗｔ％と界面活性剤１ｗｔ％と、Pb(CH3COO)2・3H2O,Zr(t-OC4H9)4,Ti(i-OC3H7)4の混合溶液を用いた。この混合溶液をスピンコートした後、１５０度で乾燥させ、ドライエアー雰囲気において４００度で３０分の仮焼成を行った。これを５回繰り返した後、図５（ｃ）に示すようにＯ2の雰囲気中で、５００度１分の熱処理を施した。このようにして、２５０nmの強誘電体膜１６を形成した。なお、ここでは、PbZrxTi1-xO3において、ｘを０．５２として（以下ＰＺＴ（５２／４８）と表す）、ＰＺＴ膜を形成している。
【００５７】
ここでは強誘電体薄膜全体に均一に分散されたシードから結晶成長が始まるため、均一な強誘電体薄膜を得ることができ、微細化に際しても信頼性の高い強誘電体薄膜を形成することが可能となる。
【００５８】
さらに、強誘電体膜１６の上に、スパッタリングによりイリジウム層および酸化イリジウム層を形成しコントロールゲート１７を形成する。ここでは、イリジウム層と酸化イリジウム層とをあわせて２００nmの厚さとなるように形成した。
【００５９】
そしてこの上層にレジストパターンＲを形成し、図５（ｄ）に示すようにこれをマスクとして各層をパターニングし、ソースドレインとなる領域の表面を露呈せしめる。
【００６０】
こののち、このゲート電極パターンをマスクとして、ホウ素（Ｂ）イオンを注入することにより、図５（ｅ）に示すようにｐ型拡散層からなるソース・ドレイン領域２，３を形成する。
【００６１】
さらに、層間絶縁膜、配線パターンを形成し、強誘電体メモリが完成する。
【００６２】
かかる構成によれば、フローティングゲートとコントロールゲートとの間に形成される強誘電体膜が、均一で結晶性の良好な膜となっているため、微細化に際しても、特性のバラツキがなく信頼性の高いものとなっている。
【００６３】
なお、強誘電体膜としてＰＺＴを用いたが、ＳＴＮ，ＳＢＴなどの強誘電体あるいはＢＳＴなどの高誘電率誘電体膜などにも適用可能である。また、超微粒粉としても強誘電体膜の構成元素を含むものであればよい。
【００６４】
【発明の効果】
以上説明してきたように、強誘電体薄膜の形成に先立ち、下地を構成する基板表面に、前記強誘電体薄膜の構成元素を含む超微粒粉を含むシード層を形成し、このシード層の上層に、強誘電体薄膜を形成し、このシード層を核として結晶化を行うようにしているため、超微粒粉の存在により、この超微粒粉を核として良好に結晶化が進むため、均一で結晶性の良好な強誘電体薄膜を得ることが可能となる。
【００６５】
また、本発明の方法では、下地を構成する基板表面に、強誘電体薄膜の構成元素の少なくとも１種を含む超微粒粉を含む強誘電体薄膜塗布液を塗布し、超微粒粉を含む薄膜を形成しているため、薄膜全体に分散する超微粒粉から良好に結晶化が進み、均一で信頼性の高い薄膜形成が可能となる。
【図面の簡単な説明】
【図１】本発明の第1の実施形態の方法で形成した絶縁膜を用いたＦＲＡＭを示す図
【図２】図１のＦＲＡＭの製造工程を示す図
【図３】本発明の第1の実施形態の方法を説明する原理説明図
【図４】本発明の第２の実施形態の方法で形成したＦＲＡＭを示す説明図
【図５】図４のＦＲＡＭの製造工程を示す図
【図６】本発明の第２の実施形態の方法を説明する原理説明図
【図７】従来例の方法を説明する原理説明図
【符号の説明】
ｈ 空孔
１ シリコン基板
１Ｓ 素子分離絶縁膜
２ ソース領域
３ ドレイン領域
４ ゲート絶縁膜
５ ゲート電極
６ （層間）絶縁膜
７ プラグ
８ 下部電極
Ｓ シード層
９ 強誘電体膜
１０ 上部電極
１５ フローティングゲート
１６ 強誘電体膜
１７ コントロールゲート[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a ferroelectric thin film and a method for manufacturing a ferroelectric memory, and more particularly to improvement in crystallinity of a ferroelectric thin film.
[0002]
[Prior art]
Ferroelectric memories currently being studied are roughly divided into two. One is a method of detecting the inversion charge amount of a ferroelectric capacitor, and is composed of a ferroelectric capacitor and a selection transistor.
[0003]
The other is a memory that detects a change in resistance of a semiconductor due to spontaneous polarization of a ferroelectric. A typical example of this method is an MFSFET. This is a MIS structure using a ferroelectric as a gate insulating film.
[0004]
In any case, it has been found that the film quality of the ferroelectric material has a great influence on the memory characteristics.
[0005]
Therefore, various methods have been proposed to improve the crystallinity of the ferroelectric thin film. As one of them, a crystallization method of a PZT thin film called a Ti seed method has been proposed.
[0006]
In this method, as shown in FIG. 7, a seed layer 9L made of an ultra-thin titanium film having a film thickness of about 20 nm is formed on the surface of the lower electrode 8 made of platinum Pt or the like by sputtering or the like, and a PZT film 9P is formed thereon by a sol-gel method. Form. Here, a mixed solution of Pb (CH 3 COO) 2 3H 2 O, Zr (t-OC 4 H 9 ) 4 , Ti (i-OC 3 H 7 ) 4 is used as a starting material, and this mixed solution is spun. After coating, it was dried at 150 ° C. and pre-baked at 400 ° C. for 30 minutes in a dry air atmosphere. After repeating this five times, crystal growth from the ultrathin film 9L is caused through a crystallization annealing step at 700 ° C. for about 1 minute in an O 2 atmosphere.
[0007]
[Problems to be solved by the invention]
Since the location where crystallization begins is indefinite, the crystal grain size cannot be controlled, and columnar crystals with a non-uniform size are formed, resulting in large variations in characteristics, particularly sufficient for miniaturization and high integration. There was a problem that characteristics could not be obtained.
[0008]
In addition, there is a portion that does not become a PZT film but becomes a titanium oxide (TiO 2 ) layer or a lead titanate (PbTiO 3 ) layer, and there is a problem that good characteristics cannot be obtained.
[0009]
Moreover, since the temperature had to be raised to about 700 ° C. during the crystallization annealing, there was a problem of adversely affecting the underlying layer such as the underlying wiring.
[0010]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a ferroelectric thin film having uniform crystallinity.
[0011]
[Means for Solving the Problems]
Therefore, in the present invention, prior to the formation of the ferroelectric thin film, a solution containing Ti ultrafine powder is applied to the substrate surface constituting the base, dried and fired to form a seed layer containing Ti ultrafine powder. A ferroelectric thin film is formed on the seed layer, and crystallization is performed using the seed layer as a nucleus.
[0012]
According to such a configuration, the presence of the ultrafine powder allows favorable crystallization to proceed with the ultrafine powder as a nucleus, so that it is possible to obtain a ferroelectric thin film with uniform and good crystallinity.
In the method of forming a ferroelectric thin film according to the present invention, the step of forming the seed layer includes a step of applying a mixed liquid obtained by mixing the Ti ultrafine powder with a surfactant and α-terviol. It is characterized by that.
The present invention is also characterized in that, in the method for forming a ferroelectric thin film, the particle size of the Ti ultrafine powder is from 0.5 nm to 200 nm.
The ultrafine powder preferably has a particle size of about 0.5 nm to 200 nm, more preferably about 1 nm to 50 nm.
In the method for forming a ferroelectric thin film according to the present invention, the particle size of the Ti ultrafine powder is 5 nm, and the concentration of the surfactant is 0.1 wt% to 10 wt%. .
[0013]
By the way, in order for the ultrafine powder to become a nucleus, a certain number of atoms are required, and it is desirable that one atom does not become a nucleus and has a size sufficiently larger than an atom of about 0.1 nm. On the other hand, if the nucleus is too large, the center of the nucleus remains Ti. Therefore, a high annealing temperature is necessary in order not to leave Ti. On the other hand, if it exceeds 200 nm, it becomes impossible to form a flat and uniform ferroelectric thin film. Further, when the nucleus becomes large, there is a disadvantage that it becomes difficult to disperse in the solvent.
Furthermore, it is desirable that this concentration be about 0.00001 wt% (0.1 wt ppm) to about 1 wt%.
[0014]
Desirably, the method includes a step of forming a seed layer containing a titanium ultrafine powder serving as a seed on a substrate surface constituting a base, and a step of forming a PZT thin film on the seed layer. .
[0015]
According to such a configuration, because of the presence of titanium ultrafine powder having a diameter of about 5 nm, crystallization proceeds favorably with the titanium ultrafine powder as a nucleus, and thus a PZT ferroelectric thin film having uniform and good crystallinity can be obtained. It becomes possible.
[0016]
Preferably, the step of forming the seed layer includes a step of applying a solution containing ultrafine titanium powder and a step of drying and baking.
[0017]
According to such a configuration, it becomes possible to arrange the titanium ultrafine powder easily and uniformly.
[0018]
Preferably, the step of forming the PZT thin film includes a sputtering step.
[0019]
Preferably, the method further includes an annealing step for crystallization.
[0020]
According to such a configuration, crystal growth is possible at a temperature of about 450 ° C. at a temperature lower than that of the prior art, so that it is possible to perform crystallization in a heating step in the subsequent electrode formation or insulating film formation step. By introducing an annealing process for crystallization, a ferroelectric thin film having good crystallinity can be easily formed.
[0021]
The following is a reference example of the present invention. According to the method of the present invention, the step of forming the seed layer comprises applying a ferroelectric thin film containing ultrafine powder containing at least one of the constituent elements of the ferroelectric thin film on the surface of the substrate constituting the base. It includes a step of applying a liquid and a baking step.
[0022]
According to such a configuration, since a thin film containing ultrafine powder is formed, crystallization proceeds well from the ultrafine powder, and a uniform and highly reliable thin film can be formed.
[0023]
Desirably, the method includes a step of applying a PZT coating solution containing ultrafine titanium powder serving as a seed to the surface of the substrate constituting the base, and a baking step.
[0024]
According to such a configuration, crystal growth starts from a seed made of ultrafine titanium powder having a particle diameter of about 5 nm and uniformly dispersed throughout the ferroelectric thin film. Accordingly, since the crystallization proceeds well with the titanium ultrafine powder as a nucleus, it is possible to obtain a PZT ferroelectric thin film having uniform and good crystallinity.
[0025]
Preferably, the method further includes an annealing step for crystallization.
[0026]
According to such a configuration, crystal growth is possible at a temperature of about 450 ° C. at a temperature lower than that of the prior art, so that it is possible to perform crystallization in a heating step in the subsequent electrode formation or insulating film formation step. By introducing an annealing process for crystallization, a ferroelectric thin film having good crystallinity can be easily formed.
[0027]
Furthermore, according to the present invention, in a method for manufacturing a ferroelectric memory composed of a FET having an MFMIS structure, prior to the formation of the ferroelectric thin film, the Ti ultrafine powder and the constituent elements of the ferroelectric thin film are formed on the floating gate surface. A solution containing the mixture is applied, dried and baked to form a seed layer containing the Ti ultrafine powder, and crystal growth is performed using the ultrafine powder as a nucleus.
In the method for manufacturing a ferroelectric memory according to the present invention, the step of forming the seed layer includes a step of applying a mixed solution obtained by mixing the Ti ultrafine powder with a surfactant and α-terpioneer. it shall be the feature of the containing.
[0028]
According to such a configuration, the presence of the ultrafine powder having a diameter of about 5 nm allows favorable crystallization to proceed with the ultrafine powder as a nucleus, so that it is possible to obtain a ferroelectric thin film with uniform and good crystallinity. A highly reliable ferroelectric memory can be formed.
[0029]
The following is a reference example of the present invention.
In this onset Ming reference example, in the method of manufacturing a ferroelectric memory comprising a FET of MFMIS structure, the step of forming the ferroelectric film, the substrate surface constituting the base, strong of the constituent elements of the dielectric thin film A ferroelectric thin film coating solution containing at least one kind of ultrafine powder is applied to form a ferroelectric thin film, which is crystallized.
[0030]
According to such a configuration, since crystal growth starts from the seed uniformly dispersed throughout the ferroelectric thin film, a uniform ferroelectric thin film can be obtained, and a highly reliable ferroelectric memory can be obtained even in miniaturization. It becomes possible to form.
[0031]
According to a reference example of the present invention , there is provided a method for manufacturing a ferroelectric memory including a switching transistor and a ferroelectric capacitor, wherein the ferroelectric thin film of the ferroelectric capacitor is formed on the first electrode surface. A ferroelectric thin film is formed by applying a ferroelectric thin film coating liquid containing ultrafine powder containing at least one kind of constituent elements of the dielectric thin film and crystallizing the same.
[0032]
According to such a configuration, since crystal growth starts from the seed uniformly dispersed throughout the ferroelectric thin film, a uniform ferroelectric thin film can be obtained, and a highly reliable ferroelectric memory can be obtained even in miniaturization. It becomes possible to form.
[0033]
According to a reference example of the present invention, there is provided a method for manufacturing a ferroelectric memory including a switching transistor and a ferroelectric capacitor, wherein the ferroelectric thin film of the ferroelectric capacitor is formed on the first electrode surface. A strong seed layer containing ultrafine powder containing at least one of the constituent elements of the dielectric thin film is formed, and a ferroelectric thin film is formed on the seed layer and crystallized to form a uniform grain size. A ferroelectric thin film made of a crystal is formed.
[0034]
According to such a configuration, the presence of the ultrafine powder having a diameter of about 5 nm allows favorable crystallization to proceed with the ultrafine powder as a nucleus, so that it is possible to obtain a ferroelectric thin film with uniform and good crystallinity. A highly reliable ferroelectric memory can be formed.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a ferroelectric memory and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.
Embodiment 1
Next, as a first embodiment of the present invention, a ferroelectric memory using a ferroelectric capacitor using PZT as a dielectric film will be described. FIG. 1 shows a completed diagram of this ferroelectric memory, and FIGS. 2A to 2E show manufacturing process diagrams. This ferroelectric memory has a substrate surface that is connected to one of source / drain regions 2 and 3 of a MOSFET as a switching transistor formed in a silicon substrate 1 and a lower electrode 8a and 8b via a plug 7. The present invention relates to a ferroelectric memory (FRAM) in which a ferroelectric capacitor is formed on an insulating film 6 to be covered, wherein the crystallinity of the ferroelectric thin film 9 of the ferroelectric capacitor is made uniform. It is. Here, 5 is a gate electrode formed on the substrate surface via the gate insulating film 4. The ferroelectric thin film 9 is formed from a crystal having a uniform crystal grain size formed by forming a seed layer containing titanium ultrafine powder on the surface of the lower electrode and generating crystal growth from the titanium ultrafine powder. It is characterized by becoming.
[0036]
That is, as shown in FIG. 1, a plug 7 made of a highly doped polycrystalline silicon layer, a lower electrode 8 made of a two-layer film of iridium 8a and iridium oxide 8b, and titanium ultrafine particles on the lower electrode 8. By crystal growth with a seed layer S made of powder as a nucleus, a uniform crystalline ferroelectric thin film 9 (see FIG. 3), and an upper electrode 10 made of a two-layer film of iridium oxide and iridium on the upper layer, Is formed.
[0037]
Next, the manufacturing process of this ferroelectric memory will be described.
First, the surface of the silicon substrate 1 on which the MOSFET (not shown) is formed in the element region formed by the element isolation insulating film 1S formed by the LOCOS method is thermally oxidized to start from the silicon oxide layer having a thickness of about 600 nm. After forming the insulating film 6, a contact hole H is formed in the insulating film 6. Then, as shown in FIG. 2 (a), a heavily doped polycrystalline silicon layer is buried in the contact hole to form a plug 7, and then the entire surface of the substrate is iridium having a film thickness of about 200 nm by sputtering. A layer 8a is formed, and the surface is further oxidized to form an iridium oxide layer 8b.
[0038]
Subsequently, this is patterned by photolithography to form the lower electrode 8.
[0039]
Thereafter, as shown in FIG. 2 (b), Ti ultrafine powder having a particle size of about 5 nm is mixed with 0.1 wt% to 10 wt% of a surfactant and α-terpione, and a mixed solution is applied. In this way, a seed layer having the Ti ultrafine powder S is formed on the surface.
[0040]
Thereafter, a PZT film 9P for forming the ferroelectric film 9 is formed by a sol-gel method. As a starting material, a mixed solution of Pb (CH 3 COO) 2 .3H 2 O, Zr (t-OC 4 H 9 ) 4 and Ti (i-OC 3 H 7 ) 4 was used. After spin-coating this mixed solution, it was dried at 150 ° C. and pre-baked at 400 ° C. for 30 minutes in a dry air atmosphere. This was repeated 5 times.
[0041]
Thereafter, as shown in FIG. 2D, heat treatment was performed at 450 ° C. for 1 minute in an O 2 atmosphere.
In this way, a 250 nm ferroelectric film 10 was formed as shown in FIG. Here, in PbZr x Ti 1-x O 3 , x is set to 0.52 (hereinafter referred to as PZT (52/48)), and a PZT film is formed.
[0042]
Further, a laminated film of iridium oxide and iridium is formed on the ferroelectric film 9 by sputtering. The laminated film of the iridium oxide layer and the iridium layer is used as the upper electrode 10. Here, the iridium layer and the iridium oxide layer were combined to form a thickness of 200 nm. In this way, a ferroelectric capacitor is obtained.
[0043]
According to such a configuration, because of the presence of the ultrafine powder, crystallization proceeds favorably using the ultrafine powder as a nucleus as shown in FIG. 3, so that a ferroelectric thin film having a uniform and good crystallinity is obtained. It becomes possible.
[0044]
The ultrafine powder preferably has a particle size of about 0.5 nm to 200 nm, more preferably about 1 nm to 50 nm.
By the way, in order for the ultrafine powder to become a nucleus, a certain number of atoms are required, and it is desirable that one atom does not become a nucleus and has a size sufficiently larger than an atom of about 0.1 nm. On the other hand, if the nucleus is too large, the center of the nucleus remains Ti. Therefore, a high annealing temperature is necessary in order not to leave Ti. On the other hand, if it exceeds 200 nm, it becomes impossible to form a flat and uniform ferroelectric thin film. Further, when the nucleus becomes large, there is a disadvantage that it becomes difficult to disperse in the solvent.
[0045]
Furthermore, it is desirable that this concentration be about 0.00001 wt% (0.1 wt ppm) to about 1 wt%. The seed layer was formed by coating the periphery of the Ti ultrafine powder with a surfactant and mixing it with an organic solvent such as α-terpioneel. Other organic solvents include xylene, toluene, It is also possible to use methoxyethanol, butanol or the like.
[0046]
Desirably, when the seed layer is formed, a solution containing ultrafine titanium powder is applied, and then dried and fired.
[0047]
According to such a configuration, it becomes possible to arrange the titanium ultrafine powder easily and uniformly.
[0048]
The step of forming the PZT thin film may be performed by a sputtering method in addition to the sol-gel method.
[0049]
Preferably, it further includes an annealing step for crystallization.
[0050]
According to such a configuration, crystal growth is possible at a temperature of about 450 ° C. at a temperature lower than that of the prior art, so that it is possible to perform crystallization in a heating step in the subsequent electrode formation or insulating film formation step. By introducing an annealing process for crystallization, a ferroelectric thin film having good crystallinity can be easily formed.
[0051]
As the first embodiment of the present invention, the ferroelectric memory using the ferroelectric thin film as PZT has been described. However, in the case where other materials such as a ferroelectric memory using STN as the dielectric film are used. Needless to say, this is also applicable.
[0052]
Reference Example Next, a manufacturing process of a MFMIS structure ferroelectric memory as a reference example will be described. FIG. 4 is a diagram showing a ferroelectric memory formed by the method of the present invention, and FIGS. 5A to 5E are manufacturing process diagrams.
[0053]
In this example, the ferroelectric thin film 16 of the ferroelectric memory having the MFMIS structure is formed by applying a sol-gel solution containing Ti ultrafine powder, firing, and then performing crystallization annealing, thereby achieving uniform and high crystallinity. The ferroelectric thin film 16 is formed.
[0054]
That is, source and drain regions 2 and 3 formed on the surface of the silicon substrate 1, a floating gate 15 formed therebetween through a gate insulating film 4, and a ferroelectric thin film formed on the floating gate 15 16 and a control gate 17 formed on the ferroelectric thin film 16.
[0055]
In manufacturing, first, as shown in FIG. 5A, the surface of the n-type silicon substrate 1 is thermally oxidized to form a silicon oxide layer 4 having a thickness of about 20 nm, and then iridium is deposited on the silicon oxide layer 4. An iridium layer to be the floating gate 15 is formed by sputtering using the target. Next, heat treatment is performed in an O 2 atmosphere at 800 ° C. (the same applies hereinafter) for 1 minute to form an iridium oxide layer on the surface of the iridium layer.
[0056]
Next, a PZT film is formed as the ferroelectric film 16 on the floating gate 15 by a sol-gel method as shown in FIG. As starting materials, 0.5 wt% of ultrafine titanium particles with a particle size of 5 nm, 1 wt% of surfactant, Pb (CH 3 COO) 2 .3H 2 O, Zr (t-OC 4 H 9 ) 4 , Ti (i A mixed solution of —OC 3 H 7 ) 4 was used. After spin-coating this mixed solution, it was dried at 150 degrees and pre-baked at 400 degrees for 30 minutes in a dry air atmosphere. After repeating this five times, as shown in FIG. 5C, heat treatment was performed at 500 ° C. for 1 minute in an O 2 atmosphere. In this way, a 250 nm ferroelectric film 16 was formed. Here, in PbZr x Ti 1-x O 3 , x is set to 0.52 (hereinafter referred to as PZT (52/48)), and a PZT film is formed.
[0057]
Here, crystal growth starts from the seed uniformly dispersed throughout the ferroelectric thin film, so that a uniform ferroelectric thin film can be obtained, and a highly reliable ferroelectric thin film can be formed even when miniaturization is performed. It becomes possible.
[0058]
Further, an iridium layer and an iridium oxide layer are formed on the ferroelectric film 16 by sputtering to form a control gate 17. Here, the iridium layer and the iridium oxide layer were combined to form a thickness of 200 nm.
[0059]
Then, a resist pattern R is formed on this upper layer, and as shown in FIG. 5D, each layer is patterned using this as a mask to expose the surface of the region to be the source / drain.
[0060]
Thereafter, boron (B) ions are implanted using the gate electrode pattern as a mask, thereby forming source / drain regions 2 and 3 made of a p-type diffusion layer as shown in FIG.
[0061]
Further, an interlayer insulating film and a wiring pattern are formed, and a ferroelectric memory is completed.
[0062]
According to such a configuration, the ferroelectric film formed between the floating gate and the control gate is a film having a uniform and good crystallinity. It has become a high thing.
[0063]
Although PZT is used as the ferroelectric film, it can also be applied to a ferroelectric such as STN or SBT or a high dielectric constant dielectric film such as BST. Further, the ultrafine powder may be any powder containing a constituent element of the ferroelectric film.
[0064]
【The invention's effect】
As described above, prior to the formation of the ferroelectric thin film, a seed layer containing ultrafine powder containing the constituent elements of the ferroelectric thin film is formed on the surface of the substrate constituting the base, and an upper layer of the seed layer. In addition, since a ferroelectric thin film is formed and crystallization is performed using this seed layer as a nucleus, crystallization proceeds favorably using this ultrafine powder as a nucleus due to the presence of the ultrafine powder. A ferroelectric thin film having good crystallinity can be obtained.
[0065]
In the method of the present invention, a ferroelectric thin film coating liquid containing ultrafine powder containing at least one kind of constituent element of the ferroelectric thin film is applied to the surface of the substrate constituting the base, and the thin film containing ultrafine powder Therefore, the crystallization proceeds well from the ultrafine powder dispersed throughout the thin film, and a uniform and highly reliable thin film can be formed.
[Brief description of the drawings]
1 is a diagram showing an FRAM using an insulating film formed by the method of the first embodiment of the present invention; FIG. 2 is a diagram showing a manufacturing process of the FRAM of FIG. 1; FIG. 4 is a diagram illustrating the principle of the method according to the embodiment. FIG. 4 is a diagram illustrating the FRAM formed by the method according to the second embodiment of the present invention. FIG. 5 is a diagram illustrating the manufacturing process of the FRAM in FIG. FIG. 7 is a principle explanatory diagram for explaining the method of the second embodiment of the present invention. FIG. 7 is a principle explanatory diagram for explaining a conventional method.
h hole 1 silicon substrate 1S element isolation insulating film 2 source region 3 drain region 4 gate insulating film 5 gate electrode 6 (interlayer) insulating film 7 plug 8 lower electrode S seed layer 9 ferroelectric film 10 upper electrode 15 floating gate 16 Ferroelectric film 17 Control gate

Claims (6)

強誘電体薄膜の形成に先立ち、下地を構成する基板表面に、Ｔｉ超微粒粉を含む溶液を塗布し、乾燥・焼成して、前記Ｔｉ超微粒粉を含むシード層を形成する工程と、
前記シード層の上層に、前記強誘電体薄膜を形成する工程とを含むことを特徴とする強誘電体薄膜の形成方法。Prior to the formation of the ferroelectric thin film, a step of applying a solution containing Ti ultrafine powder to the substrate surface constituting the base, drying and firing, and forming a seed layer containing the Ti ultrafine powder ;
Forming a ferroelectric thin film on the seed layer. The method for forming a ferroelectric thin film. 前記シード層を形成する工程は、前記Ｔｉ超微粒粉を界面活性剤及びαテルビオールと混合してなる混合液を塗布する工程を含むことを特徴とする請求項１に記載の強誘電体薄膜の形成方法。  2. The ferroelectric thin film according to claim 1, wherein the step of forming the seed layer includes a step of applying a mixed solution obtained by mixing the Ti ultrafine powder with a surfactant and α-terviol. Forming method. 前記Ｔｉ超微粒粉の粒径は０．５ｎｍから２００ｎｍであることを特徴とする請求項２に記載の強誘電体薄膜の形成方法。  3. The method for forming a ferroelectric thin film according to claim 2, wherein the Ti ultrafine powder has a particle size of 0.5 nm to 200 nm. 前記Ｔｉ超微粒粉の粒径は５ｎｍであり、
前記界面活性剤の濃度は０．１ｗｔ％〜１０ｗｔ％であることを特徴とする請求項１に記載の強誘電体薄膜の形成方法。The particle size of the Ti ultrafine powder is 5 nm,
The method for forming a ferroelectric thin film according to claim 1, wherein the concentration of the surfactant is 0.1 wt% to 10 wt%. 前記シード層を形成する工程は、前記強誘電体薄膜の構成元素を含む溶液を塗布する工程と、
焼成する工程とを含むことを特徴とする請求項１乃至４のいずれか一項に記載の強誘電体薄膜の形成方法。Forming the seed layer includes applying a solution containing a constituent element of the ferroelectric thin film; and
A method for forming a ferroelectric thin film according to any one of claims 1 to 4, further comprising a firing step. さらに結晶化のためのアニール工程を含むことを特徴とする請求項１乃至５のいずれか一項に記載の強誘電体薄膜の形成方法。  The method for forming a ferroelectric thin film according to any one of claims 1 to 5, further comprising an annealing step for crystallization.
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