JP2003258570A - Offset reduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an offset reduction circuit with a simple circuit configuration capable of reducing an offset of a differential circuit. <P>SOLUTION: The offset reduction circuit reduces an offset of a differential circuit (comprising Q1 to Q4, R1, R2, and Q9) and has a clamp circuit (comprising Q30 to Q33, R20, R21, 22) for clamping a power supply voltage, the power supply voltage clamped by the clamp circuit (comprising Q30 to Q33, R20, R21, 22) is applied to the differential circuit (comprising Q1 to Q4, R1, R2, and Q9) to reduce a fluctuation in collector-emitter voltage of the transistors (Q1, Q2) configuring the differential circuit when the speaker voltage is fluctuated thereby reducing the offset of the differential circuit. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset reduction circuit, and more particularly to an offset reduction circuit for reducing an offset generated by a fluctuation in power supply voltage.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit diagram of an example of a conventional motor driver circuit. In the figure, the reference potential Vr is applied to the terminal 10.
ef is applied, and the input voltage Vin is supplied to the terminal 12. The terminal 10 is connected to the base of the npn transistor Q1, and the terminal 12 is connected to the base of the npn transistor Q2 via the resistor R3.

The emitters of the transistors Q1 and Q2 are commonly connected to the collector of the npn transistor Q9 of the constant current source, and the emitter of the transistor Q9 is grounded.
The collector of the transistor Q1 is a pnp transistor Q3.
Of the transistor Q2 is connected to the collector of the pnp transistor Q4, the emitters of the transistors Q3 and Q4 are connected to the power supply Vcc via the resistors R1 and R2, respectively, and the transistors Q3 and Q4 are It constitutes a current mirror circuit. The base of the transistor Q2 has a collector of the pnp transistor Q5 and transistors Q12 and Q13.
The emitters of are connected. Transistor Q1 above
˜Q4, Q9 and resistors R1, R2 form a voltage-current conversion amplifier.

The base of the transistor Q5 is connected to the base and collector of the pnp transistor Q6, and the emitters of the transistors Q5 and Q6 are connected to the power supply Vcc.
The transistors Q5 and Q6 form a current mirror circuit. The collector of the transistor Q6 is connected to the base of the npn transistor Q7, and the transistor Q7
Has a collector connected to the power supply Vcc and an emitter connected to the collector of a constant current source npn transistor Q10.
The emitter of the transistor Q10 is grounded.

The output signal of the voltage-current conversion amplifier is supplied from the collector of the transistor Q2 to the base of an npn transistor Q8 forming an emitter follower circuit. The collector of the transistor Q8 is connected to the power supply Vcc, and the emitter of the transistor Q8 is the npn transistor Q1.
2, Q13 and the collector of the npn transistor Q11 of the constant current source. Transistor Q1
The emitter of 1 is grounded. A predetermined control voltage is applied from the terminal 11 to the bases of the current source transistors Q9, Q10, Q11.

The collector of the transistor Q12 is connected to the base and collector of the pnp transistor Q14 and the bases of the pnp transistor Q15 and the pnp transistor Q20, and the emitters of the transistors Q15, Q16 and Q20 are connected to the power source Vcc via the resistors R4, R5 and R8, respectively.
The transistors Q14, Q15, and Q20 are connected to and form a current mirror circuit. Transistor Q1
The emitter of 2 is connected to the emitter of the transistor Q13 and also connected to the base of the transistor Q2 to form a feedback loop.
The emitter potential of the transistors Q12 and Q13 is stabilized by virtually short-circuiting the emitter of the transistor 10 and the terminal 10.

The collector of the transistor Q13 is connected to the base and collector of the npn transistor Q16 and the bases of the npn transistor Q17 and the npn transistor Q21, and the emitters of the transistors Q16, Q17 and Q21 are grounded via the resistors R6, R7 and R9, respectively. Thus, the transistors Q16, Q17 and R21 form a current mirror circuit.

The collector of the transistor Q15 is connected to the collector and base of the npn transistor Q18, and the emitter of the transistor Q18 is the npn transistor Q1.
9 is connected to the collector and base of the transistor Q1
The emitter of 8 is connected to the collector of transistor Q17. The transistors Q18 and Q19 are provided to reduce the influence of the Early voltage of the transistors Q15 and Q17.

The collector of the transistor Q20 is the collector of the npn transistor Q24 and the npn transistor Q.
It is connected to 27 bases. The base of the transistor Q24 is connected to the base and collector of the npn transistor Q25, the emitters of the transistors Q24 and Q25 are grounded via the resistors R12 and R13, respectively, and the transistors Q24 and Q25 form a current mirror circuit. The collector of the transistor Q25 is connected to the emitter of the transistor Q27.

The collector of the transistor Q21 is the collector of the pnp transistor Q22 and the pnp transistor Q.
It is connected to the base of 26. The base of the transistor Q22 is connected to the base and collector of the pnp transistor Q23, the emitters of the transistors Q22 and Q23 are connected to the power supply Vcc through the resistors R10 and R11, respectively, and the transistors Q22 and Q23 form a current mirror circuit. There is. The collector of the transistor Q23 is connected to the emitter of the transistor Q26.

The collectors of the transistors Q26 and Q27 are connected, and the collectors of the transistors Q26 and Q27 are connected to the terminal 1 to which the reference potential Vref is applied via the resistor R14.
3 and the non-inverting input terminal of the non-inverting amplifier 17 in the output stage amplifier 16.

The emitter of the transistor Q18 is a resistor R1.
The non-inverting amplifier 1 in the output stage amplifier 16 is connected to the terminal 14 to which the reference potential Vref is applied via
8 non-inverting input terminals. Output stage amplifier 1
Output terminal 1 of each of the non-inverting amplifiers 17 and 18 in 6
A motor is connected to 9 and 20.

Here, the collector current of the transistor Q10 is I1 with respect to the collector current I1 of the transistor Q9.
The base current of the transistor Q7 has the same value as the base current of the transistors Q1 and Q2 when the emitter currents of the transistors Q1 and Q2 are both I1 / 2. By supplying the base current of the transistor Q7 to the base of the transistor Q2 by the current mirror circuit of the transistors Q5 and Q6,
Compensating for a base current of 2. This is to prevent the offset due to the base current of the transistor Q8. Here, the offset means that the emitter potential of the transistor Q8 is 0 when there is no potential difference between the terminals 10 and 12.
It is said to vary from V.

[0014]

In the conventional motor driver circuit, when the power supply voltage Vcc fluctuates, the transistor Q
An offset is generated under the influence of the Early voltage generated by the change in the collector-emitter voltage of 1, Q2.

When the reference potential Vref is applied to the terminal 12, the collector currents of the transistors Q3 and Q4 are the same, and the collector potential of the transistor Q1 is the resistance R2.
Voltage drop Vr2 and the base-emitter voltage Vfq2 of the transistor Q4. Further, the potential of the terminal 40 becomes the reference potential Vref due to the imaginary short circuit of the operational amplifier 40 of the output stage amplifier, and the transistor Q
The collector potential of 2 is determined by the sum of Vref and the base-emitter voltage Vfq8 of the transistor Q8.

Therefore, when the collector potential of the transistor Q1 changes due to the influence of the Early voltage due to the change of the power supply voltage Vcc, the collector potential of the transistor Q1 and the collector potential of the transistor Q2 differ and an offset occurs. Then, the larger the change in the power supply voltage Vcc, the larger the offset becomes, and there is a problem that the motor supplied with the output of the motor driver circuit is erroneously driven.

The present invention has been made in view of the above points, and an object of the present invention is to provide an offset reduction circuit which can reduce the offset of the differential circuit and which has a simple circuit configuration.

[0018]

According to a first aspect of the present invention, there is provided an offset reducing circuit for reducing an offset of a differential circuit (Q1 to Q4, R1, R2, Q9), which is a clamp for clamping a power supply voltage. Circuit (Q30-Q33, R2
0, R21, 22), and the clamp circuit (Q30
To Q33, R20, R21, 22) to supply the power supply clamped to the differential circuits (Q1 to Q4, R1, R2, Q9) to form a differential circuit when the power supply voltage changes. (Q1, Q2) collector
It is possible to reduce the variation of the voltage between the emitters and reduce the offset of the differential circuit.

According to a second aspect of the present invention, in the offset reduction circuit according to the first aspect, the clamp circuit includes a constant current source (22) connected to a power source and the constant current source (2).
A transistor (Q30) having a collector connected to 2) and having a base and a collector and an emitter connected to each other by resistors (R20, R21); and the transistor (Q30).
With one or a plurality of diode elements (Q32, Q33) connected between the emitter and the reference potential, the power supply voltage can be clamped with a simple circuit configuration.

The reference numerals in the parentheses are given for easy understanding and are merely examples, and the present invention is not limited to the illustrated modes.

[0021]

1 is a circuit diagram of an embodiment of a motor driver circuit to which the circuit of the present invention is applied. In the figure,
The same parts as those in FIG. 2 are designated by the same reference numerals.

In FIG. 1, one end of a constant current source 22 is connected to a power supply Vcc, and the other end thereof is an npn transistor Q30.
, The collector of the npn transistor Q31 and one end of the resistor R20 are connected. Transistor Q31
The other end of the resistor R20 and one end of the resistor R21 are connected to the base of, and the other end of the resistor R21 is connected to the emitter of the transistor Q31. The collector of the transistor Q30 is connected to the power supply Vcc.

The emitter of the transistor Q31 has npn
The collector of the transistor Q32 is connected. The transistor Q32 is diode-connected (connection between collector and base) to form a diode element, and the emitter of the transistor Q32 is connected to the collector of an npn transistor Q33 which forms a diode element by diode connection. The emitter of the transistor Q33 is connected to the terminal 24 to which the reference potential Vref is applied.

The reference potential Vref is applied to the terminal 10, and the input voltage Vin is supplied to the terminal 12. The terminal 10 is connected to the base of the npn transistor Q1, and the terminal 12 is connected to the base of the npn transistor Q2 via the resistor R3.

The emitters of the transistors Q1 and Q2 are commonly connected to the collector of the npn transistor Q9 of the constant current source, and the emitter of the transistor Q9 is grounded.
The collector of the transistor Q1 is a pnp transistor Q3.
Of the transistor Q2, the collector of the transistor Q2 is connected to the collector of the pnp transistor Q4, the emitters of the transistors Q3 and Q4 are connected to the emitter of the transistor Q30 via the resistors R1 and R2, respectively. Q4 constitutes a current mirror circuit. The base of the transistor Q2 is connected to the collector of the pnp transistor Q5 and the emitters of the transistors Q12 and Q13. The transistors Q1 to Q4 and Q9 and the resistors R1 and R2 form a voltage-current conversion amplifier.

The base of the transistor Q5 is connected to the base and collector of the pnp transistor Q6, the emitters of the transistors Q5 and Q6 are connected to the emitter of the transistor Q30, and the transistors Q5 and Q6 form a current mirror circuit. The collector of the transistor Q6 is connected to the base of the npn transistor Q7, and the collector of the transistor Q7 is the transistor Q30.
Is connected to the collector of an npn transistor Q10 of a constant current source, and the emitter of the transistor Q10 is grounded.

The output signal of the voltage-current conversion amplifier is supplied from the collector of the transistor Q2 to the base of an npn transistor Q8 forming an emitter follower circuit. The collector of the transistor Q8 is connected to the collector of the transistor Q30, and the emitter of the transistor Q8 is npn.
N of the bases of the transistors Q12 and Q13 and the constant current source
It is connected to the collector of the pn transistor Q11.
The emitter of the transistor Q11 is grounded. A predetermined control voltage is applied from the terminal 11 to the bases of the current source transistors Q9, Q10, Q11.

The collector of the transistor Q12 is connected to the base and collector of the pnp transistor Q14 and the bases of the pnp transistor Q15 and the pnp transistor Q20. The emitters of the transistors Q14, Q15 and Q20 are connected to the transistor Q30 via the resistors R4, R5 and R8, respectively. Connected to the collector of the transistor Q1
4, Q15 and Q20 form a current mirror circuit. The emitter of the transistor Q12 is the transistor Q1.
3 and the base of the transistor Q2 to form a feedback loop, and the emitters of the transistors Q12 and Q13 are virtually short-circuited with the terminal 10 to form the transistors Q12 and Q3.
The emitter potential of 13 is stabilized.

The collector of the transistor Q13 is connected to the base and collector of the npn transistor Q16 and the bases of the npn transistor Q17 and the npn transistor Q21, and the emitters of the transistors Q16, Q17 and Q21 are grounded via the resistors R6, R7 and R9, respectively. Thus, the transistors Q16, Q17 and R21 form a current mirror circuit.

The collector of the transistor Q15 is connected to the collector and base of the npn transistor Q18, and the emitter of the transistor Q18 is the npn transistor Q1.
9 is connected to the collector and base of the transistor Q1
The emitter of 9 is connected to the collector of transistor Q17. The transistors Q18 and Q19 are provided to reduce the influence of the Early voltage of the transistors Q15 and Q17.

The collector of the transistor Q20 is the collector of the npn transistor Q24 and the npn transistor Q.
It is connected to 27 bases. The base of the transistor Q24 is connected to the base and collector of the npn transistor Q25, the emitters of the transistors Q24 and Q25 are grounded via the resistors R12 and R13, respectively, and the transistors Q24 and Q25 form a current mirror circuit. The collector of the transistor Q25 is connected to the emitter of the transistor Q27.

The collector of the transistor Q21 is the collector of the pnp transistor Q22 and the pnp transistor Q.
It is connected to the base of 26. The base of the transistor Q22 is connected to the base and collector of the pnp transistor Q23, and the emitters of the transistors Q22 and Q23 are connected to the transistor Q10 via the resistors R10 and R11, respectively.
Is connected to the collector of the transistor 30, and transistors Q22, Q
Reference numeral 23 forms a current mirror circuit. The collector of the transistor Q23 is connected to the emitter of the transistor Q26.

The collectors of the transistors Q26 and Q27 are connected, and the collectors of the transistors Q26 and Q27 are connected to the terminal 1 to which the reference potential Vref is applied via the resistor R14.
3 and the non-inverting input terminal of the non-inverting amplifier 17 in the output stage amplifier 16.

The emitter of the transistor Q18 is a resistor R1.
The non-inverting amplifier 1 in the output stage amplifier 16 is connected to the terminal 14 to which the reference potential Vref is applied via
8 non-inverting input terminals. Output stage amplifier 1
Output terminal 1 of each of the non-inverting amplifiers 17 and 18 in 6
A motor is connected to 9 and 20.

The operation of the above circuit will be described. Terminal 1
When a sine wave is input to the input voltage Vin of 2, when a current flows from the outside to the terminal 10, the current flows to the transistor Q13 (transistor Q12 is off) and the transistors Q16, Q17, Q19 and Q21 are on. Then, a current equal to the resistance R2 flows from the terminal 14 to the resistance R15, and the voltage Vout2 corresponding to this current is output from the terminal 20. Along with this, the transistor Q2
2, Q23, Q26 are turned on and the resistor R14 to the terminal 13
A current equal to that of the resistor R2 flows out to the terminal, and a voltage Vout1 (= −Vout2) corresponding to this current is output from the terminal 19.

Conversely, when a current flows from the terminal 10 to the outside, the current flows through the transistor Q12 (transistor Q13 is off), and the transistors Q14,
Q15, Q18 and Q20 are turned on, a current equal to that of the resistor R2 flows from the resistor R15 to the terminal 14, and a voltage Vout2 corresponding to this current is output from the terminal 20. At the same time, the transistors Q24, Q25, Q27 are turned on, and a current equal to the resistance R2 flows from the terminal 13 to the resistance R14, and the voltage Vout1 (= -Vou) corresponding to this current is supplied.
t2) is output from the terminal 19.

Here, the turned-on transistors Q30 and Q
Base-emitter voltage Vbe of 31, Q32 and Q33
Each of 30, Vbe31, Vbe32, Vbe33 is approximately 0.7 V, and the current I3 is applied to the resistors R20 and R21.
Since (= Vbe / R21) flows, the transistor Q3
The potential Vq30 of the emitter of 0 is expressed as follows.

Vq30 = Vref1 + Vbe31 + Vb
e32 + Vbe33 + I3.R20-Vbe30 That is, the transistors Q30 to Q33 and the resistors R20, R
21 and the constant current source 22 form a clamp circuit that clamps the power supply voltage Vcc to the voltage Vq30 and outputs it from the emitter of the transistor Q30. The transistor Q
30 is a transistor Q3 which produces a larger current than the constant current source 22.
To Q7 are provided. Further, in FIG. 1, the clamped power is supplied from the transistor Q30 to a single motor driver circuit, but actually it is supplied to a plurality of motor driver circuits.

Further, the collector current I of the transistor Q9
1, the collector current of the transistor Q10 is I1 /
The base current of the transistor Q7 has the same value as the base current of the transistors Q1 and Q2 when the emitter currents of the transistors Q1 and Q2 are both I1 / 2. The base current of the transistor Q7 is supplied to the base of the transistor Q2 by the current mirror circuit of the transistors Q5 and Q6 to compensate the base current of the transistor Q2, thereby preventing an offset caused by the base current of the transistor Q8. This offset is applied to the transistor Q when there is no potential difference between the terminals 10 and 12.
It means that the emitter potential of 8 fluctuates from 0V.

In this embodiment, since the power source clamped by the clamp circuit is supplied to the motor driver circuit, the emitter potential of the transistor Q30 is kept substantially constant at Vq30 even when the power source voltage Vcc changes.
Fluctuations in the collector-emitter voltage of the transistors Q3 and Q4 are reduced, and the offset can be reduced.

[0041]

As described above, according to the first aspect of the present invention, when the power supply voltage changes, the change in the collector-emitter voltage of the transistors forming the differential circuit can be reduced, and the difference can be reduced. The offset of the dynamic circuit can be reduced.

According to the second aspect of the invention, the power supply voltage can be clamped with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a motor driver circuit to which a circuit of the present invention is applied.

FIG. 2 is a circuit diagram of an example of a conventional motor driver circuit.

[Explanation of symbols]

10-14, 24 terminals 16 output stage amplifier 22 constant current source Q1 to Q33 transistors R20-R21 resistance

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Keisuke Yamazato             1601 Sakai, Atsugi, Kanagawa Mitsumi Electric Co., Ltd.             Company Atsugi Office F term (reference) 5J066 AA01 AA12 CA13 CA92 FA00                       FA20 HA08 HA19 HA25 KA05                       KA09 KA21 MA01 MA11 MA21                       ND01 ND12 ND22 PD01                 5J500 AA01 AA12 AC13 AC92 AF00                       AF20 AH08 AH19 AH25 AK05                       AK09 AK21 AM01 AM11 AM21                       DN01 DN12 DN22 DP01

Claims (2)

[Claims] 1. An offset reduction circuit for reducing an offset of a differential circuit, comprising a clamp circuit for clamping a power supply voltage, and supplying the power source clamped by the clamp circuit to the differential circuit. Offset reduction circuit. 2. The offset reduction circuit according to claim 1, wherein the clamp circuit has a constant current source connected to a power source, and a collector connected to the constant current source, and between the base and the collector and the emitter. An offset reduction circuit comprising a transistor connected by a resistor and one or a plurality of diode elements connected between an emitter of the transistor and a reference potential.