JP2003258107A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a capacitor of high reliability in an analog circuit. <P>SOLUTION: After a wiring trench is formed, by sequentially dry-etching an oxide silicon film 22 and a nitride silicon film 21 which are formed on a semiconductor substrate 1, a titanium nitride film and a W film are deposited in the order, on the semiconductor substrate 1 including the inside of the wiring trench, and the wiring trench is filled with the W film. By eliminating the titanium nitride film and the W film, which are positioned outside the wiring trench by a CMP method, and a wiring 25 is formed. After a silicon nitride film 27 and a titanium nitride film 28 are deposited in the order on the semiconductor substrate 1, by patterning the titanium nitride film 28, a capacitor MIM is formed wherein the wiring 25 is set as a lower electrode, the silicon nitride film 27 is made a capacity insulating film and the titanium nitride film 28 is set as an upper electrode. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a technique effectively applied to the manufacture of a semiconductor integrated circuit device having an analog circuit portion.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device having an analog circuit portion is manufactured while paying attention to the following points.
That is, in an operational amplifier generally used in an analog circuit section, (a) an undesired parasitic capacitance so as not to deteriorate the frequency characteristic of a negative feedback circuit composed of an input resistance and a feedback resistance added to the operational amplifier. (B) Characteristics of the resistance variation of the feedback circuit resistance, the pair of transistors forming the differential input of the operational amplifier, and the pair of transistors forming the active load circuit such as the current mirror circuit. The variation is suppressed so that the amplification factor of the operational amplifier is not varied, and (c) the noise signal is reduced.

As a means for reducing the noise signal, there is known a technique of providing a capacitance element (capacitor) in an analog circuit. For example, SIS (Poly Si-Insulato
It is a means of forming capacitors of r-Poly Si) structure.
That is, a lower electrode of a capacitor is formed by depositing a first polycrystalline Si (silicon) film on an interlayer insulating film formed on a semiconductor substrate and patterning the first polycrystalline Si film by etching. . Subsequently, a Si nitride film and a second polycrystalline Si film, which will be a capacitive insulating film, are sequentially deposited on the semiconductor substrate including the lower electrode, and then the second polycrystalline Si film is patterned by etching to form a capacitor. The upper electrode is formed to form a capacitor of SIS structure.

Japanese Patent Laid-Open No. 2001-237375 discloses that
A technique for forming a capacitor having a MIM (Metal-Insulator-Metal) structure is disclosed. That is, a groove is formed in the first interlayer insulating film formed on the semiconductor substrate, and a Cu (copper) film is embedded in the groove to form the lower electrode of the capacitor. Then, after forming a first diffusion prevention film on the lower electrode for preventing Cu from diffusing into the capacitance insulation film, a capacitance insulation film is formed on the first diffusion prevention film. Then, a second layer for preventing diffusion of Cu, which will be the upper electrode of the capacitor, into the capacitive insulating film on the capacitive insulating film.
To form a diffusion prevention film. Then, the second on the semiconductor substrate
Of the MIM structure is formed by forming an interlayer insulating film of, a groove portion reaching the second diffusion barrier film in the second interlayer insulating film, and burying a Cu film in the groove portion to form an upper electrode of the capacitor. It is a capacitor.

Japanese Patent Laid-Open No. 2001-36010 also discloses a technique for forming a capacitor having an MIM structure. That is, a groove for forming a first wiring and a groove for forming a lower electrode of a capacitor are formed in a first interlayer insulating film deposited on a semiconductor substrate, and a conductive film is embedded in these grooves to form a first wiring. After the lower electrode and the lower electrode are formed at one time, a second interlayer insulating film is deposited on the semiconductor substrate, and a groove for forming the second wiring and a groove for forming the upper electrode of the capacitor are formed in the second interlayer insulating film. Formed,
A capacitor having a MIM structure is formed by forming a capacitive insulating film in a groove for forming an upper electrode and then filling a conductive film in the groove to form a second wiring and a lower electrode at a time. .

[0006]

However, the present inventors have found that the following problems exist in the technique of adding a capacitor to the above analog circuit.

That is, in the case of forming a capacitor of SIS structure, the depletion layer spreads from the interface with the capacitive insulating film with the application of voltage. Therefore, the capacitance varies depending on the applied voltage value, and there is a problem that a capacitor having a desired capacitance cannot be provided.
Further, since a parasitic capacitance is generated between the lower electrode and the semiconductor substrate, there is a problem in that a parasitic element such as an undesired parasitic capacitance is excluded as much as possible. Further, when patterning the second polycrystalline Si film serving as the upper electrode, etching residue of the second polycrystalline Si film is generated on the side wall of the lower electrode. Therefore, there is a problem that processing of the second polycrystalline Si film becomes difficult. Further, at the upper end portion of the side wall of the lower electrode, the thickness of the capacitive insulating film becomes thin, so that the withstand voltage becomes insufficient between the upper electrode and the lower electrode, and a leak current flows, resulting in a capacitor. There is a problem that the function of is degraded.

In the case of a MIM structure capacitor having a lower electrode and an upper electrode formed of a Cu film, a capacitor insulating film, for example, is used to prevent foreign matter from adhering to the lower electrode made of the Cu film. At the time of forming, there is a problem that a dedicated film forming apparatus is required considering that the lower electrode is made of a Cu film. Furthermore, if high-temperature heat treatment is performed in the step after the lower electrode is formed, Cu atoms forming the lower electrode may diffuse into the interlayer insulating film. Therefore, the treatment temperature is restricted in the heat treatment. There are challenges that end up.

Further, in the case of a MIM structure capacitor having a lower electrode and an upper electrode formed of a Cu film, in order to prevent diffusion of Cu forming the lower electrode and the upper electrode into the interlayer insulating film, Since it is necessary to form the first diffusion prevention film and the second diffusion prevention film, there is a problem that the number of steps increases by that amount.

It is an object of the present invention to provide a technique capable of forming a highly reliable capacitor in an analog circuit.

Another object of the present invention is to provide a technique capable of forming a capacitor in an analog circuit by a simple process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, (a) at least a part of the first wiring layer formed on the semiconductor substrate is a lower electrode, and (b) a first dielectric film covering the lower electrode is a capacitance insulating film. , (C) a first conductive film disposed on the capacitance insulating film and insulated from the lower electrode is used as an upper electrode, and (d) electrically connected to a plurality of wiring layers formed on the semiconductor substrate. The first wiring layer has a capacitive element, and the first wiring layer includes a first wiring formed by embedding a refractory metal film in a groove provided in a first insulating film formed on a semiconductor substrate.

Further, according to the present invention, the step of forming a first insulating film on a semiconductor substrate, the step of forming a groove in the first insulating film, and the step of forming a refractory metal film in the groove to form a first wiring. Forming a first dielectric film on the semiconductor substrate to cover the first wiring, and depositing a first conductive film on the first dielectric film, By patterning the first conductive film and the first wiring so as to be insulated by the first dielectric film, the first wiring serves as a lower electrode, the first dielectric film serves as a capacitance insulating film, and And a step of forming a capacitive element using the first conductive film as an upper electrode.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. In addition, even a plan view may be hatched in order to make the drawing easy to understand.

(First Embodiment) A semiconductor integrated circuit device according to the first embodiment is, for example, an analog / digital mixed LSI in which an analog circuit portion and a digital circuit portion are formed on the same semiconductor substrate. Regarding the manufacturing process of this LSI,
This will be described with reference to FIGS.

First, as shown in FIG. 1, the semiconductor substrate 1 made of single crystal silicon is heat-treated to form a thin silicon oxide film (pad oxide film) on its main surface. Then, after depositing a silicon nitride film on this silicon oxide film,
The silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using the photoresist film as a mask.

Subsequently, after the element isolation trench 2 is formed in the semiconductor substrate 1 in the element isolation region by dry etching using the silicon nitride film as a mask, the damaged layer formed on the inner wall of the element isolation trench 2 by etching is removed. For this purpose, the semiconductor substrate 1 is heat-treated to form a thin silicon oxide film on the inner wall of the groove.

Subsequently, after depositing the silicon oxide film 3 on the semiconductor substrate 1, the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 3 in order to improve the quality of the silicon oxide film 3. . After that, chemical mechanical polishing using a silicon nitride film as a stopper (Chemical Mechanical
The silicon oxide film 3 is polished by a cal polishing (CMP) method and left inside the element isolation trench 2 to form an element isolation region whose surface is flattened.

Then, after removing the silicon nitride film remaining on the active region of the semiconductor substrate 1 by wet etching,
B (boron) is ion-implanted into the region of the semiconductor substrate 1 where the n-channel type MISFET is to be formed to form the p-type well 4.

Next, the semiconductor substrate 1 is heat-treated to form a gate oxide film on the surface of the p-type well 4.
Then, a polycrystalline silicon film is deposited on the semiconductor substrate 1. Then, P (phosphorus) is ion-implanted into the polycrystalline silicon film to form an n-type semiconductor film. Subsequently, by patterning the polycrystalline silicon film by dry etching, the gate electrode 10 made of the polycrystalline silicon film is formed.
To form. Next, after depositing, for example, a silicon oxide film on the semiconductor substrate 1, the silicon oxide film is anisotropically etched to form sidewall spacers on the sidewalls of the gate electrode 10. Next, P or As (arsenic) is ion-implanted into the p-type well 4 to form an n-type semiconductor region (source, drain) 11. Subsequently, the gate electrode 10 and the n-type semiconductor region 11
Of the silicide film 10A on the surfaces of the gate electrode 10 and the n-type semiconductor region 11 by exposing the surface of the gate electrode 10 and depositing, for example, a Co (cobalt) film and heat-treating.
And a silicide film 11A is formed. This gives n
It is possible to reduce the diffusion resistance and the contact resistance of the type semiconductor region 11. After that, the unreacted Co film is removed. Through the steps so far, the n-channel MISFET (Metal Insulator Semiconducto) is formed in the p-type well 4.
r Field Effect Transistor (semiconductor element) Qn can be formed. This n-channel type MISFETQ
n forms a digital circuit.

Next, the silicon nitride film 1 is formed on the semiconductor substrate 1.
2 and the silicon oxide film 13 are sequentially deposited. continue,
The silicon oxide film 13 and the silicon nitride film 12 are sequentially dry-etched to form a contact hole 1 above the n-type semiconductor region (source, drain) 11.
5 is formed. Next, after depositing, for example, a titanium nitride film on the semiconductor substrate 1 including the inside of the contact hole 15, a W (tungsten) film is deposited on the semiconductor substrate 1,
The contact hole 15 is filled with the W film. afterwards,
The titanium nitride film and the W film on the silicon oxide film 13 other than the contact holes 15 are removed by, for example, the CMP method to form the plug 16.

Next, a silicon nitride film (first insulating film) 21 and a silicon oxide film (first insulating film) 22 are sequentially deposited on the semiconductor substrate 1. Subsequently, the silicon oxide film 22 and the silicon nitride film 21 are sequentially dry-etched to form a wiring groove (groove portion) having a depth of about 200 nm.
A wiring groove 24 reaching 23 and the plug 16 is formed.
Then, on the semiconductor substrate 1 including the inside of the wiring grooves 23 and 24,
For example, after depositing a titanium nitride film, a W (tungsten) film is deposited on the semiconductor substrate 1 and the wiring grooves 23 and 24 are filled with the W film. Then, the titanium nitride film and the W film on the silicon oxide film 2 other than the wiring grooves 23 and 24 are removed by, for example, the CMP method, and a wiring layer (wiring (first wiring) 25 and wiring (second wiring) 26 ( Forming a first wiring layer). Here, the wiring 26 is connected to the plug 16 at the bottom.

Next, as shown in FIG. 2, a film thickness of 35 nm to 50 n is formed on the semiconductor substrate 1 by plasma CVD, for example.
A silicon nitride film (first dielectric film) 27 of about m is deposited. Then, a film thickness of 50 nm is formed on the silicon nitride film 27.
A titanium nitride film (first conductive film) 28 is deposited to a certain degree.

Next, as shown in FIG. 3, the titanium nitride film 28 is dry-etched using the photoresist film as a mask to form the wiring 25 as a lower electrode, the silicon nitride film 27 as a capacitor insulating film, and the titanium nitride film. A capacitor (capacitance element) MIM having 28 as an upper electrode can be formed. The capacitor MIM forms an analog circuit.

In the first embodiment, since the W film is embedded in the wiring groove 23, the titanium nitride film 28 to be the upper electrode is formed on the semiconductor substrate 1 which is flattened by polishing by the CMP method. Titanium nitride film 28 serving as the upper electrode
It is possible to prevent problems such as generation of unnecessary etching residue when patterning by etching. That is, the patterning of the titanium nitride film 28, which will be the upper electrode of the capacitor MIM, can be facilitated.

Further, the silicon nitride film 2 serving as a capacitance insulating film
The film 7 is also formed on the flattened semiconductor substrate 1. Therefore, it is possible to prevent the silicon nitride film 27 from being locally thinned, so that the withstand voltage becomes insufficient in the thinned portion and a leak current flows,
It is possible to prevent the problem that the breakdown voltage between the upper electrode and the lower electrode becomes insufficient. That is, it is possible to prevent the yield of the capacitors MIM of the first embodiment from decreasing.

Further, in the first embodiment, the lower electrode of the capacitor MIM is formed of the W film which is difficult to react with chlorine. Therefore, the titanium nitride film 2 serving as the upper electrode
It is possible to prevent the problem that the lower electrode is corroded even when a chlorine-based etching gas is used in etching 8. Further, since the W film is a high melting point metal having a melting point of about 3400 ° C., even if there is a process involving heat treatment in the process after forming the lower electrode, the treatment temperature during the heat treatment is restricted. It is possible to prevent a defect.

Next, as shown in FIG. 4, an etching stopper film 31 is formed by depositing a silicon nitride film on the semiconductor substrate 1. Etching stopper film 31
Is for avoiding damage to the lower layer and deterioration of processing dimensional accuracy due to over-digging when forming a groove or hole for forming a wiring in the upper insulating film. Then, on the silicon nitride film 31, from the lower layer to F
An interlayer insulating film 32 is formed by sequentially depositing a silicon oxide film to which (fluorine) is added and a silicon oxide film to which F is not added. The interlayer insulating film 3
2 may be formed only from a silicon oxide film to which F is not added. Moreover, since the dielectric constant of the interlayer insulating film 32 can be lowered by adding F, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be lowered, and the wiring delay can be improved. In addition, the interlayer insulating film 32
May be formed of an organic low dielectric constant material.

Subsequently, the inter-layer insulating film 32, the etching stopper film 31, and the silicon nitride film 27 are processed by a dry etching technique using a photoresist film as a mask to form the contact hole 33 and the wiring 26 reaching the upper electrode of the capacitor MIM. Reaching contact hole 34
To form. Then, after depositing a titanium nitride film on the semiconductor substrate 1 including the insides of the contact holes 33 and 34, a W film is further deposited to form the contact holes 33 and 34 by the W
Embed with membrane. After that, the titanium nitride film and the W film on the interlayer insulating film 32 other than the contact holes 33 and 34 are removed by, for example, the CMP method to form the plugs 35 and 36.

Next, as shown in FIG. 5, an etching stopper film 37 and an interlayer insulating film 38 are formed by the same steps as the steps of forming the etching stopper film 31 and the interlayer insulating film 32. Subsequently, by using the photoresist film as a mask, the interlayer insulating film 38 and the etching stopper film 37 are dry-etched to form a wiring groove 39. At this time, a part of the wiring groove 39 contacts the plug 35 or the plug 36 at the bottom.

Then, for example, TaN (tantalum nitride film) is deposited on the entire surface of the semiconductor substrate 1 including the inside of the wiring groove 39. This TaN film is deposited to improve the adhesion of the copper film deposited in the subsequent steps and to prevent the diffusion of copper, and the film thickness thereof can be exemplified to be about 30 nm. Then, a Cu (copper) film to be a seed film is deposited on the entire surface of the semiconductor substrate 1 on which the TaN film is deposited. Further subsequently, the semiconductor substrate 1 on which the seed film is deposited
A Cu film, for example, is formed on the entire surface of so as to fill the wiring groove 39. The Cu film filling the wiring groove 39 can be formed by, for example, an electrolytic plating method. afterwards,
Excess TaN film and Cu film on the interlayer insulating film 32 are removed, and the TaN film and Cu film are left in the wiring groove 39 to form the wiring (third wiring) 40. At this time, TaN
The film and the Cu film are removed by polishing using the CMP method.

Next, as shown in FIG. 6, an etching stopper film 41 and an interlayer insulating film 42 are formed by the same steps as the steps of forming the etching stopper film 31 and the interlayer insulating film 32. Further, similarly, an etching stopper film 43 and an interlayer insulating film 44 are formed on the interlayer insulating film 42. Subsequently, the interlayer insulating films 42 and 44 and the etching stopper films 41 and 43 are dry-etched using the photoresist film as a mask,
Contact hole 45 reaching wiring 40 and wiring groove 4
6 is formed. Then, a TaN film and a Cu film are deposited along a process similar to the process of forming the wiring 40, and then the excess TaN film and the Cu film on the interlayer insulating film 44 are removed to form a wiring 47. .

Next, an etching stopper film 48 and an interlayer insulating film 49 are formed by the same steps as the steps of forming the etching stopper film 31 and the interlayer insulating film 32. Then, the contact holes 33 and 34 (see FIG.
After the contact hole 50 is formed by the same step as the step of forming the plugs), the plug 51 is formed in the contact hole 50 by the same step as the step of forming the plugs 35 and 36.

Next, a Ti (titanium) film, an Al (aluminum) alloy film and a titanium nitride film are sequentially deposited on the interlayer insulating film 49. Subsequently, the Ti film, the Al alloy film, and the titanium nitride film are patterned by dry etching using the photoresist film as a mask, so that T
The wiring 52 made of a laminated film of an i film, an Al alloy film and a titanium nitride film is formed.

Subsequently, a silicon oxide film 53, a silicon nitride film 54 and a polyimide film 55 are sequentially deposited on the semiconductor substrate 1 from the lower layers. Next, these silicon oxide films 5
3, the silicon nitride film 54 and the polyimide film 55 are selectively opened to form an opening 56 reaching the wiring 52. Through this process, the wiring 52 is used as a bonding pad to manufacture the semiconductor integrated circuit device of the first embodiment.

In the above-described first embodiment, the case where the capacitor MIM is formed using the wiring 25 formed by filling the W film in the wiring groove 23 (see FIG. 1) as the lower electrode has been exemplified. However, the semiconductor substrate 1 You may form a capacitor by making a plug connected with the element formed on the main surface of this into a lower electrode. That is, as shown in FIG. 7, the silicon oxide film (first insulating film) 13 and the silicon nitride film (first insulating film) 12 are sequentially formed by dry etching to form the source of the n-channel type MISFET Qn2.
A plug (first plug) formed in a contact hole (hole) reaching the n-type semiconductor region 11 which is a drain.
P1 is used as the lower electrode of the capacitor. The capacitor MIM can be formed by sequentially forming the silicon nitride film 27 and the titanium nitride film 28, which will be the capacitance insulating film, on the plug P1. Here, the n-channel type MISFET (semiconductor element) Qn2 forms an analog circuit.

(Embodiment 2) In Embodiment 2, the capacitor MIM formed in Embodiment 1 (see FIG. 3) is used.
The wiring 25 (see FIG. 3), which will be the lower electrode of FIG. 3), is formed in a different shape in a plane. The manufacturing process is the same as in the first embodiment.

As shown in FIG. 8, in the second embodiment, the wiring 25 is formed by being divided into a plurality of wirings 25A arranged at a predetermined interval on a plane. In FIG. 8, the hatched area indicates the wiring 25. The wiring 25A is formed by burying a W film in a wiring groove formed by etching the silicon oxide film 22 and the silicon nitride film 21 and removing an excess W film outside the wiring groove by a CMP method. At this time, the polishing agent, the oxidizing agent and the like are selected so that the polishing rate of the W film is higher than that of the silicon oxide film 22. for that reason,
When the wiring 25 is formed without being divided, since the wiring width is widened, dishing (recess) is generated on the surface of the wiring 25, which may cause the capacitance value of the capacitor MIM to deviate from a desired value. . Therefore, the wiring 25A is divided into a plurality of wirings 25A to form the wiring 25A.
Since the wiring width of each of the wirings becomes narrow, dishing can be prevented. As a result, the capacitor MIM can be formed with a desired capacitance value.

The wiring 25A is electrically connected to other wirings arranged in the lower layer through the plugs P1 connected at both ends thereof. In addition, the titanium nitride film 28 and the wiring 4
0 (see FIG. 5) is formed at a position where it does not overlap with the wiring 25A on the plane. As a result, even when the contact hole 33 penetrates the titanium nitride film 28 and the silicon nitride film 27 by etching when forming the contact hole 33 (not shown in FIG. 8) in which the plug 35 is formed, Therefore, it is possible to prevent the short circuit between the upper electrode (titanium nitride film 28) and the lower electrode (wiring 25). Furthermore, by forming the plugs 35 in an array on a plane, the resistance between the titanium nitride film 28 and the wiring 40 can be reduced.

(Third Embodiment) An LSI according to the third embodiment will be described below.

As shown in FIG. 9, in the third embodiment, both ends of the plurality of wirings 25A (see FIG. 8) shown in the second embodiment are connected to the ends of the other wirings 25A, respectively. The wiring 25 is formed by patterning as described above. Thereby, as compared with the case of the second embodiment,
Wiring 2 serving as a lower electrode of the capacitor MIM (see FIG. 3)
The resistance of 5 can be reduced.

(Fourth Embodiment) An LSI according to the fourth embodiment will be described below.

FIG. 10 is a plan view of relevant parts showing the shape and the positional relationship of the upper electrode and the lower electrode of the capacitor MIM (see FIG. 1) according to the fourth embodiment. When the area of the upper surface of the wiring 25 serving as the lower electrode is small enough not to cause dishing by CMP when the wiring 25 is formed, the wiring 25 shown in the second embodiment is replaced with a plurality of wirings 25A (see FIG. It is possible to use only one wiring 25 without using a means for dividing the wiring 25 into a single wiring 25. As a result, the area occupied by the capacitor MIM can be made smaller than in the second and third embodiments. As a result, the LSI of the fourth embodiment can be downsized. Further, also in the fourth embodiment, the plug 35 is formed at a position where it does not overlap the wiring 25A on the plane.

(Fifth Embodiment) An LSI according to the fifth embodiment will be described below.

FIG. 11 is a plan view of relevant parts showing the shape and positional relationship of the upper and lower electrodes of the capacitor MIM (see FIG. 1) in the fifth embodiment. In the fifth embodiment, the inside of the wiring 25 serving as the lower electrode is patterned so that the regions where the silicon oxide film 22 (see FIG. 1) appears are arranged at a plurality of positions at predetermined intervals on the plane. In addition, a plug 35 that electrically connects the titanium nitride film 28 serving as the upper electrode and the wiring 40 (see FIG. 5).
Is formed at a position that does not overlap the wiring 25 on the plane including the region where the silicon oxide film 22 appears. As a result, the area of the wiring 25 in the plane can be increased more than in the second and third embodiments. That is, if the area of the wiring 25 in the plane is the same as in the second and third embodiments, the area occupied by the wiring 25 is the second and third embodiments. Can be reduced than in the case of. Thereby, the capacitor MI
Since the area occupied by M can be made smaller than in the cases of the second and third embodiments, the LSI of the fifth embodiment can be miniaturized.

(Sixth Embodiment) The manufacturing process of an LSI according to the sixth embodiment will be described below.

In the third embodiment, the etching stopper film 31 (see FIG. 4) used in the first embodiment is omitted, and the etching stopper film 31 is formed on the silicon nitride film 27 serving as the capacitance insulating film of the capacitor MIM. It has the same function as. That is, the titanium nitride film 28 to be the upper electrode of the capacitor MIM (see FIG. 3).
When patterning is performed by dry etching, the etching selectivity of the titanium nitride film 28 is set to the silicon nitride film 27.
By setting the etching selection ratio to be sufficiently higher than the etching selection ratio, the reduction of the film thickness of the silicon nitride film 27 after the patterning of the titanium nitride film 28 is prevented. This allows the silicon nitride film 27 to be used as an etching stopper film during dry etching for forming the contact hole 34. Further, the titanium nitride film 28 can be used as an etching stopper film when forming the contact hole 33 (FIG. 12).
reference).

According to the sixth embodiment, the number of LSI manufacturing steps can be reduced as compared with the first embodiment.

(Embodiment 7) Hereinafter, a process of manufacturing an LSI according to Embodiment 7 will be described.

The manufacturing process of the LSI of the seventh embodiment is the same as the process of forming the interlayer insulating film 32 in the first embodiment (see FIGS. 1 to 4). After that, the etching stopper film (second insulating film) 37 and the interlayer insulating film (second insulating film) are formed by the same process as the process of forming the etching stopper film (second insulating film) 31 and the interlayer insulating film (second insulating film) 32. A film) 38 is formed. Then, the interlayer insulating film 38 and the etching stopper film 37 are dry-etched by using the photoresist film as a mask to form a contact at the wiring groove (first groove portion) 39, the wiring groove 39A, and a bottom portion of the wiring groove 39. A contact hole (first hole portion) 34 that is opened at the bottom of the hole (second hole portion) 33 and the wiring groove (second groove portion) 39A is formed.

Subsequently, for example, a TaN film is deposited on the entire surface of the semiconductor substrate 1 including the insides of the contact holes 33 and 34 and the wiring groove 39. Then, after depositing a Cu film serving as a seed film on the entire surface of the semiconductor substrate 1 on which the TaN film is deposited, a Cu film (second conductive film) is formed by, for example, an electrolytic plating method in the contact holes 33 and 34 and wiring. Groove 39
Are formed so as to be embedded. Then, excess TaN film and C on the interlayer insulating film 32 are polished by polishing using the CMP method.
The u film is removed, and the TaN film and the Cu film are left in the contact holes 33 and 34 and the wiring groove 39 to form the wiring 40 (see FIG. 13).

According to the sixth embodiment, the plugs 35 and 36 shown in the first embodiment (see FIG. 4).
Since the wiring 40 and the wiring 40 can be formed in the same step, the number of manufacturing steps of the LSI can be reduced as compared with the case of the first embodiment.

(Embodiment 8) Hereinafter, a process of manufacturing an LSI according to Embodiment 8 will be described.

The manufacturing process of the LSI according to the eighth embodiment is the same as the manufacturing process of the wirings 25 and 26 in the first embodiment (see FIG. 1). Then, the semiconductor substrate 1
Silicon nitride film 27A and silicon nitride film 27B
Are sequentially deposited to form a silicon nitride film 27 having a total film thickness of about 35 nm to 50 nm from these silicon nitride films 27A and 27B. Subsequently, as in the case of the first embodiment, a titanium nitride film 28 is deposited, and the titanium nitride film 28 is patterned to form a capacitor MIM.
Are formed (see FIG. 14).

When the silicon nitride film 27 is formed of a single layer of silicon nitride film, for example, when a void is generated in the silicon nitride film, the upper electrode (titanium nitride film 28) and the lower electrode of the capacitor MIM are formed. Withstand voltage becomes insufficient between (wiring 25) and leak current flows,
There is a concern that the function as a capacitor may be degraded. On the other hand, when the above-mentioned means for forming the silicon nitride film 27 from the two-layer silicon nitride film is used, even if a void is generated in the lower silicon nitride film 27A, for example, in the upper silicon nitride film 27B. The possibility that voids will occur at the same positions as the voids generated in the silicon nitride film 27A on the plane is low. That is, by forming the silicon nitride film 27 from the two-layered silicon nitride film, it is possible to prevent the breakdown voltage between the upper electrode and the lower electrode from being lowered, so that it is possible to prevent the function of the capacitor MIM from being lowered. Become.

In the eighth embodiment, the silicon nitride film is formed into two layers.
Although it is a layer, it may be formed of three or more layers.

(Ninth Embodiment) The manufacturing process of an LSI according to the ninth embodiment will be described below.

The manufacturing process of the LSI of the ninth embodiment is the same as the process of forming the wirings 25 and 26 in the first embodiment (see FIG. 1). Then, the semiconductor substrate 1
A silicon oxide film 27C having a film thickness of about 5 nm and a film thickness of 20
nm to 50 nm and a silicon nitride film 27 having a thickness of 5
A silicon oxide film 27D having a thickness of about nm is sequentially deposited. A plasma CVD method, for example, can be used to deposit the silicon oxide films 27C and 27D. Then, as in the case of the first embodiment, a titanium nitride film 28 is deposited, and the titanium nitride film 28 and the silicon oxide film 27D are patterned, whereby the silicon oxide film 27C, the silicon nitride film 27, and the silicon oxide film 27 are formed. A capacitor MIM having the film 27D as a capacitive insulating film is formed (see FIG. 15).

As described above, by forming the capacitor insulating film of the capacitor MIM from the three thin films (the silicon oxide film 27C, the silicon nitride film 27 and the silicon oxide film 27D), the upper part is formed as in the eighth embodiment. Since it is possible to prevent the breakdown voltage between the electrode and the lower electrode from decreasing, it is possible to prevent the function of the capacitor MIM from decreasing.

(Embodiment 10) Hereinafter, Embodiment 1 will be described.
The manufacturing process of the 0 LSI will be described.

The manufacturing process of the LSI according to the tenth embodiment is as follows.
By omitting the step of depositing the silicon oxide film 27D (see FIG. 15) in the manufacturing process of the LSI of the ninth embodiment,
The silicon oxide film 27C is formed with a film thickness (about 10 nm) including the film thickness of the silicon oxide film 27D (see FIG. 16).

According to the tenth embodiment as described above,
By forming the capacitor insulating film of the capacitor MIM from two thin films (the silicon oxide film 27C and the silicon nitride film 27), the gap between the upper electrode and the lower electrode is formed as in the eighth and ninth embodiments. Since it is possible to prevent the breakdown voltage of the capacitor from decreasing, it is possible to prevent the function of the capacitor MIM from decreasing. In addition, L of the ninth embodiment
Since the step of depositing the silicon oxide film 27D in the SI manufacturing step is omitted, the number of LSI manufacturing steps can be reduced as compared with the case of the ninth embodiment.

(Embodiment 11) Hereinafter, Embodiment 1 will be described.
The manufacturing process of the first LSI will be described.

The manufacturing process of the LSI according to the eleventh embodiment is as follows.
The same is true up to the step (see FIG. 1) of forming the wirings 25 and 26 in the first embodiment. The wiring 25 is
For example, as shown in the second embodiment, it may be formed by being divided into a plurality of wirings 25A. Then, a titanium nitride film 25B having a film thickness of about 50 nm and a film thickness of 35 nm to 5 nm
A silicon nitride film 27 having a thickness of about 0 nm and a titanium nitride film 28 having a thickness of about 50 nm are sequentially deposited. Subsequently, the titanium nitride film 25B, the silicon nitride film 27, and the titanium nitride film 28 are patterned by dry etching,
Using the titanium nitride film 25B as a lower electrode, the silicon nitride film 2
A capacitor MIM having a capacitor insulating film 7 and a titanium nitride film 28 as an upper electrode is formed. At this time, the titanium nitride film 25B covers all the upper surfaces of the wiring 25A after patterning (see FIG. 17).

According to the eleventh embodiment as described above,
Since the upper electrode and the lower electrode of the capacitor MIM are formed of the same material, it is possible to reduce the difference in the characteristics of the capacitor MIM when the potential relationship between the upper electrode and the lower electrode is reversed. This makes it possible to obtain a higher performance analog circuit.

(Embodiment 12) Hereinafter, Embodiment 1 will be described.
A method of manufacturing the second LSI will be described.

In the first embodiment, the wiring 25,
26 (see FIG. 1) is formed by using W as the main conductive layer, but in the twelfth embodiment, Cu is formed as the main conductive layer by the same step as the step of forming the wiring 40. In the first embodiment, the plug 36 is formed by using W as the main conductive layer and the wiring 40 is formed by using Cu as the main conductive layer in different steps, but in the twelfth embodiment,
Embedding a thin film (first metal film) having Cu as a main conductive layer in the hole formed in the etching stopper film 31 and the interlayer insulating film 32 and the wiring groove formed in the etching stopper film 37 and the interlayer insulating film 38. Then, the plug and the wiring are integrally formed as a wiring (third wiring) 40A. The plug 47A connected to the wiring 40A and the wiring (first wiring,
The second plug) 47B is formed in the etching stopper film (first insulating film) 43 and the interlayer insulating film (first insulating film) 44 by the same process as the process of forming the wirings 25 and 26 in the first embodiment. It can be formed by embedding a thin film (second metal film) having W as a main conductive layer in the formed wiring grooves 46A and 46B.

After forming the plug 47A and the wiring 47B, the silicon nitride film 27 in the first embodiment is formed.
Then, a silicon nitride film (first dielectric film) 47C and a titanium nitride film (first conductive film) 47D are sequentially deposited by a process similar to the process of depositing the titanium nitride film 28. Subsequently, by patterning the titanium nitride film 47E by dry etching, a capacitor (capacitance element) using the wiring 47B as a lower electrode, the silicon nitride film 47C as a capacitive insulating film, and the titanium nitride film 47D as an upper electrode.
MIM2 can be formed. This capacitor MI
M2 forms an analog circuit.

Next, after forming an etching stopper film 48 and an interlayer insulating film 49 similar to those of the first embodiment,
By dry etching the etching stopper film 48 and the interlayer insulating film 49 using a photoresist film, the contact hole 50A reaching the plug 47A and the contact hole 50B reaching the titanium nitride film 47D.
To form. Then, the plugs 51A and 51B are respectively formed in the contact holes 50A and 50B by the same process as the process of forming the plug 51 in the first embodiment.
To form. After that, the steps after the step of forming the wiring 52 are the same as those in the first embodiment (see FIG. 18).

As described above, in the twelfth embodiment, the capacitor MIM2 is formed by using the uppermost wiring 47B except the wiring 52 serving as the bonding pad. Thereby, it is possible to form various circuits by using the wiring in the lower layer than the wiring 47B. That is,
According to the twelfth embodiment, it becomes possible to easily form various circuits as compared with the case where the lowermost wiring is used as the lower electrode of the capacitor.

(Embodiment 13) Hereinafter, Embodiment 1 will be described.
A method of manufacturing the third LSI will be described.

The manufacturing process of the LSI according to the thirteenth embodiment is as follows.
Process of forming contact holes 50A and 50B (FIG. 1)
Up to (8), it is the same as in the twelfth embodiment. Then, contact holes 50A, 50 are formed on the interlayer insulating film 49.
An Al film for burying B is deposited. The contact holes 50A and 50B have a diameter sufficient to fill the Al film. Subsequently, the Al film is patterned by dry etching using a photoresist film to form the wiring 52A (see FIG. 19). Wiring 52
The process after forming A is the same as that in the twelfth embodiment.

According to the thirteenth embodiment as described above,
The plugs 51 and 51A shown in the twelfth embodiment
Since the wiring 52 and the wiring 52 (see FIG. 18) can be integrally formed, the number of manufacturing steps of the LSI can be reduced as compared with the twelfth embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the case where the titanium nitride film is used as the upper electrode of the capacitor has been described, but a W film, a WN (tungsten nitride) film,
A Ta (tantalum) film or TaN film may be used.

Further, for example, in the twelfth embodiment,
Although the wiring layer arranged below the capacitor is formed by using Cu as the main conductive layer, Al may be formed as the main conductive layer.

[0079]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) A high melting point metal film is embedded in a wiring groove (groove portion) formed in an interlayer insulating film (first insulating film), and the high melting point metal film outside the wiring groove is removed by polishing by, for example, a CMP method to form a capacitor ( After forming the lower electrode of the capacitive element), a titanium nitride film (first conductive film) to be the capacitor upper electrode is formed on the flattened semiconductor substrate. Therefore, when the titanium nitride film is patterned by etching. In addition, it is possible to prevent problems such as generation of unnecessary etching residue. That is, it is possible to easily pattern the titanium nitride film serving as the upper electrode of the capacitor. (2) Since the capacitive insulating film of the capacitor (capacitive element) is formed on the flattened semiconductor substrate, it is possible to prevent the capacitive insulating film from becoming locally thin. That is, it is possible to prevent the breakdown voltage from becoming insufficient in the thinned portion and a leak current to flow, and the breakdown voltage between the upper electrode and the lower electrode of the capacitor from becoming insufficient. (3) Since the lower electrode of the capacitor (capacitance element) is formed by using the W film (high melting point metal film) which is difficult to react with chlorine as the main conductive layer, the titanium nitride film (first conductive film) serving as the upper electrode is etched. Even if a chlorine-based etching gas is used in this case, it is possible to prevent the lower electrode from being corroded. (4) Since the lower electrode of the capacitor (capacitive element) is formed by using the refractory metal film as the main conductive layer, even if there is a step involving heat treatment in the step after forming the lower electrode, the processing temperature during the heat treatment is restricted. It is possible to prevent it.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 2;

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 3;

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 6 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 5;

FIG. 7 is a cross-sectional view of essential parts in a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a plan view of relevant parts for explaining a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 9 is a main-portion plan view illustrating a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 10 is a plan view of relevant parts for explaining a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 11 is a plan view of relevant parts for explaining a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view of essential parts in a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 13 is a main-portion cross-sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention during a manufacturing step.

FIG. 14 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 15 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view during a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 17 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 18 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 19 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 element isolation groove 3 silicon oxide film 4 p-type well 10 gate electrode 10A silicide film 11 n-type semiconductor region (source, drain) 11A silicide film 12 silicon nitride film (first insulating film) 13 silicon oxide film (first 1 insulating film) 15 contact hole 16 plug 21 silicon nitride film (first insulating film) 22 silicon oxide film (first insulating film) 23 wiring groove (groove portion) 24 wiring groove 25, 25A wiring (first wiring) 26 wiring ( Second wiring) 25B Titanium nitride film 27, 27A, 27B Silicon nitride film (first dielectric film) 27C, 27D Silicon oxide film 28 Titanium nitride film (first conductive film) 31 Etching stopper film (second insulating film) 32 interlayer insulating film (second insulating film) 33 contact hole (second hole) 34 contact hole (first hole) 35, 3 6 plug 37 etching stopper film (second insulating film) 38 interlayer insulating film (second insulating film) 39 wiring groove (first groove portion) 39A wiring groove (second groove portion) 40, 40A wiring (third wiring) 41 etching stopper Film 42 Interlayer insulation film 43 Etching stopper film (first insulation film) 44 Interlayer insulation film (first insulation film) 45 Contact holes 46, 46A, 46B Wiring groove 47 Wiring 47A Plug 47B Wiring (first wiring, second plug) 47C Silicon nitride film (first dielectric film) 47D Titanium nitride film (first conductive film) 48 Etching stopper film 49 Interlayer insulating films 50, 50A, 50B Contact holes 51, 51A, 51B Plug 52, 52A Wiring 53 Silicon oxide Film 54 Silicon Nitride Film 55 Polyimide Film 56 Openings MIM, MIM2 Capacitor (Capacitance Element) P Plug (first plug) Qn n-channel type MISFET (semiconductor device) Qn2 n-channel type MISFET (semiconductor element)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/88 SF term (reference) 4M104 AA01 BB01 BB30 BB40 CC01 CC05 DD08 DD16 DD17 5F033 HH04 HH09 HH11 HH18 HH19 HH25 HH32 HH33 JJ19 JJ33 KK01 KK19 KK33 LL04 MM08 MM12 MM13 NN06 NN07 PP27 QQ08 QQ09 QQ10 QQ16 QQ25 QQ37 QQ48 RR04 RR06 RR11 RR22 TT08 VV10 5F038 AC02 AC04 AC05 AC15 AC14 E12 CD16 E18 CD18 CD16 E18 CD20

Claims (12)

[Claims] 1. A first wiring layer formed on a semiconductor substrate is at least a part of a lower electrode, a first dielectric film covering the lower electrode is a capacitive insulating film, and the first dielectric film is disposed on the capacitive insulating film. A first conductive film insulated from a lower electrode is used as an upper electrode, and a capacitive element electrically connected to a plurality of wiring layers formed on the semiconductor substrate is provided, and the first wiring layer is on the semiconductor substrate. A semiconductor integrated circuit device comprising: a first wiring formed by embedding a refractory metal film in a groove provided in the first insulating film formed in the above. 2. The semiconductor integrated circuit device according to claim 1, wherein the lower electrode is formed of a plurality of the first wirings, and the plurality of first wirings forming the lower electrode are spaced apart from each other by a predetermined distance. A semiconductor integrated circuit device characterized by being arranged. 3. A plurality of wiring layers formed on a semiconductor substrate and at least a part of a first wiring layer arranged at the bottom of the plurality of wiring layers are used as lower electrodes, and a first electrode covering the lower electrodes is provided. A dielectric film as a capacitance insulating film, a first conductive film disposed on the capacitance insulating film and insulated from the lower electrode as an upper electrode, and a capacitive element electrically connected to the plurality of wiring layers; And a first wiring layer including a first wiring formed by embedding a refractory metal film in a groove provided in a first insulating film formed on the semiconductor substrate. Integrated circuit device. 4. The semiconductor integrated circuit device according to claim 3, wherein the lower electrode is formed from a plurality of the first wirings, and the plurality of first wirings forming the lower electrode are spaced apart from each other by a predetermined distance. A semiconductor integrated circuit device characterized by being arranged. 5. An electrode formed by using a plurality of wiring layers formed on a semiconductor substrate and a first plug layer arranged between the wiring layers and electrically connecting the wiring layers as a lower electrode, A first dielectric film covering the lower electrode is a capacitive insulating film, a first conductive film disposed on the capacitive insulating film and insulated from the lower electrode is an upper electrode, and electrically connected to the plurality of wiring layers. A semiconductor integrated circuit device, comprising: a capacitive element to be connected; wherein the first plug layer is formed in a groove provided in a first insulating film formed on the semiconductor substrate. 6. A step of (a) forming a first insulating film on a semiconductor substrate, (b) a step of forming a groove in the first insulating film, and (c) embedding a refractory metal film in the groove. First
Forming a wiring, (d) forming a first dielectric film on the semiconductor substrate to cover the first wiring, and (e) after depositing a first conductive film on the first dielectric film. , The first
By patterning a conductive film so as to be insulated by the first dielectric film, the first wiring serves as a lower electrode, the first dielectric film serves as a capacitive insulating film, and the first dielectric film serves as a capacitive insulating film.
A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a capacitive element having a conductive film as an upper electrode. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the step (c) includes (c1) the first
Manufacturing of a semiconductor integrated circuit device comprising: a step of forming the refractory metal film filling the inside of the groove on an insulating film; and (c2) removing the refractory metal film other than inside the groove. Method. 8. (a) a step of forming a first insulating film on a semiconductor substrate, (b) a step of forming a plurality of groove portions in the first insulating film, (c) a refractory metal in the plurality of groove portions. A step of burying a film to form a first wiring and a second wiring, (d)
Forming a first dielectric film on the semiconductor substrate to cover the first wiring; (e) depositing a first conductive film on the first dielectric film, and then forming the first conductive film on the first dielectric film. A capacitive element having the first wiring as a lower electrode, the first dielectric film as a capacitive insulating film, and the first conductive film as an upper electrode by patterning so as to be insulated by the first dielectric film. And (f) after the step (e), a step of forming a second insulating film on the semiconductor substrate, (g) etching the second insulating film to form the first groove portion, the second groove portion, the Forming a first hole reaching the second wiring from a first groove and a second hole reaching the first conductive film from the second groove, (h) the first groove, the second groove, Embedding a second conductive film in the first hole and the second hole,
A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a third wiring. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (c) includes (c1) the first
Manufacturing of a semiconductor integrated circuit device comprising: a step of forming the refractory metal film filling the inside of the groove on an insulating film; and (c2) removing the refractory metal film other than inside the groove. Method. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the second hole portion is formed in a region which does not overlap the first wiring in a plane. Production method. 11. (a) a step of forming a second insulating film on a semiconductor substrate, (b) a step of forming a plurality of first groove portions in the second insulating film, (c) an inside of the plurality of first groove portions. A step of burying a first metal film to form a third wiring, (d) a step of forming a first insulating film on the semiconductor substrate, (e) a step of forming a plurality of trenches in the first insulating film, (F) a step of burying a second metal film in the plurality of grooves to form a second plug electrically connected to the third wiring, (g) depositing a first dielectric film on the semiconductor substrate Covering the second plug by: (h) depositing a first conductive film on the first dielectric film, and then depositing the first conductive film and the second plug on the first dielectric film. By patterning so as to be insulated by a film, the second plug serves as a lower electrode, and 1. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a capacitive element having a dielectric film as a capacitive insulating film and the first conductive film as an upper electrode. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein in the step (c), (c1) the first metal film is formed on the second insulating film so as to fill the inside of the first groove portion. And (c2) removing the first metal film other than the inside of the first groove portion, the step (f) includes (f1) filling the inside of the plurality of groove portions on the first insulating film. A method of manufacturing a semiconductor integrated circuit device, comprising: the step of forming the second metal film; and (f2) the step of removing the second metal film except in the plurality of groove portions.